DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office Action has been issued in response to RCE filed 04 February 2026.
Claims 1 – 18 are pending.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04 February 2026 has been entered.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1 – 18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding claim 1, “wherein the page request issuing circuitry is directly responsive to the translation circuitry, in response to the address translation request, identifying a page fault associated with the first address, to automatically issue a page request requesting that the page table information corresponding to the first address is updated to correct the page fault” lacks written support and introduces new matter. As recited, the limitation refers to page request issuing circuitry directly responding to translation circuity. While the instant specification discloses MMU directly issuing page request where page request issuing circuity is responsible for issuing said page request (see spec page 5 ln 29-36), there is no written support for said page request issuing circuitry (issuing said page request) responding directly to translation circuitry within said MMU (see spec Fig. 3 and corresponding paragraphs). In other words, there is no disclosure of one internal MMU component directly causing a another internal MMU component to issue said page request. Therefore, the limitation in question lacks written support and introduces new matter.
Claim 17 is the non-transitory computer-readable medium claim corresponding to MMU claim 1, and is rejected on the same grounds as claim 1.
Regarding claim 18, “directly in response to identifying the page fault associated with the first address, automatically issuing a page request requesting that the page table information corresponding to the first address is updated to correct the page fault” is not supported in the instant specification and introduces new matter. As recited, the limitation refers to issuing page request in direct response to page fault. While the instant specification discloses MMU generating PRI in response to a page fault (see spec Fig. 6 and corresponding paragraphs), there is no disclosure that said PRI is directly responsive to said page fault. Rather the instant specification discloses that there is an intermediate ATS response page fault between said PRI and said page fault, rending said PRI issuance not directly responsive to said page fault (see spec Fig. 6 and corresponding paragraphs). Therefore, the limitation in question lacks written support and introduces new matter.
Claims, dependent upon above identified claims, are also rejected on the same grounds as said above identified claims.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1 – 17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, “wherein the page request issuing circuitry is directly responsive to the translation circuitry, in response to the address translation request, identifying a page fault associated with the first address, to automatically issue a page request requesting that the page table information corresponding to the first address is updated to correct the page fault” is unclear and indefinite. In particular, i) “in response to the address translation request” is unclear as to what (page request issuing circuitry responsive to translation circuitry or identification of page fault) is being triggered by (or responsive to) said address translation request, ii) “to automatically issue a page request” is unclear as to what (page request issuing circuity or directly responsive) corresponds to auto issuing of said page request, and iii) “directly” is unclear whether it is referring to “responsive to the translation circuity” or “to automatically issue a page request”. Therefore, claim 1 is unclear and indefinite. For the purposes of examination, Examiner is interpreting the limitation to refer to i) page fault is responsive to address translation request (see claim 1), ii) page request issuing circuitry is to automatically issue page request (see Fig. 6 and corresponding paragraphs), and iii) “directly” refers to automatic issuance of page request (see spec page 5 ln 28-36).
Claim 17 is the non-transitory computer-readable medium claim corresponding to MMU claim 1, and is rejected on the same grounds as claim 1.
Claims, dependent upon above identified claims, are also rejected on the same grounds as said above identified claims.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 8 – 10, 14 and 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Swaine (US 20200387457).
Regarding claim 1, Swaine teaches
A memory management unit (memory management unit = Fig. 1 SMMU 120) comprising:
an interface configured to receive an address translation request from a device, the address translation request specifying a first address to be translated; (Swaine teaches endpoint 100 (device) sending ATS translation request (translation request) (see Fig. 3, ¶[43]), which comprise virtual address (first address) that requires translation (to be translated) (see ¶[40]), to transaction interface 532 (interface) of SMMU 120 (see Fig. 5, ¶[50]).)
translation circuitry configured to translate the first address specified by the address translation request into a second address, wherein the translation is based on page table information corresponding to the first address,
wherein in response to the translation circuitry performing the translation in response to the address translation request without identifying a page fault associated with the first address, the interface is configured to send an address translation response to the device, the address translation response comprising the second address; and (Examiner is interpreting “without identifying a page fault” to refer to translation can be completed (see spec page 8 ln 19-20).) (Swaine teaches servicing ATS translation request, comprising virtual address (first address) to be translated (see ¶[40]), by performing page table walk (translate) to identify address translation (from said virtual address to physical address (second address)) (see Fig. 3, ¶[43-44]) from translation tables (page table information) wherein said page walk is performed by translation circuitry 534 (translation circuity) in SMMU 120 (see Fig. 5, ¶[50]). Swaine also teaches said address translation as response (address translation response) is returned (send), to endpoint 100 (device) (see Fig. 3, ¶[43]), via transaction interface 532 (interface) (see ¶[55]). Note that said address translation is able to be completed (without identifying a page fault).)
the memory management unit comprises page request issuing circuitry, wherein the page request issuing circuity is directly responsive to the translation circuitry, in response to the address translation request, identifying a page fault associated with the first address, to automatically issue a page request requesting that the page table information corresponding to the first address is updated to correct the page fault (112(b) interpretation: i) in response to the address translation request refers to page fault, ii) to automatically issue a page request refers to page request issuing circuity, and iii) directly refers to issuance of page request.) (Examiner is interpreting “page request issuance circuity is directly…to automatically issue a page request” to refer to memory management unit directly issuing said page request where said page request is issued by said page request issuance circuity (see spec page 5 ln 28-36).) (Swaine teaches responsive to ATS translation request (address translation request), comprising virtual address (first address) to be translated (see ¶[40]), being (responsive to) unable to be serviced (due to missing address translation or translation fault (page fault) (see ¶[41]) where translation circuity (translation circuitry) is responsible for accessing said address translation (see ¶[50])), sending, via control circuity 539 (page request issuing circuity) of SMMU 120 (see Fig. 5, ¶[74]), PRI event (page request) that results in positive PRI response indicating availability/populating of (update) said address translation (see Fig. 4, ¶[41], [44-45]) in translation tables (page table information) (see ¶[50]) wherein said positive PRI response allows for said ATS translation request to be reissued (see Fig.4, ¶[46]) (correct page fault). Note that said PRI event (page request) (sent via said control circuitry 539 (page request issuing circuity)) originates directly (directly) from said SMMU 120 (memory management unit) (see Fig. 4) wherein said PRI event issued via a reaction (automatically) by said SMMU (see ¶[45]).)
Claim 14 is the data processing apparatus corresponding to memory management unit claim 1 and is rejected on the same grounds as claim 1. Swaine also teaches
A data processing apparatus (data processing apparatus = Fig. 1 circuitry) comprising:
a memory management unit (memory management unit = Fig. 1 SMMU 120) according to claim 1, and processing circuitry (processing circuitry = Fig. 1 CPU 160) to execute program instructions (Swaine teaches CPU running (execute) software (program) that provide configuration (instructions) such as translation tables and supporting information (see ¶[41]). Note that said configuration includes plural items (i.e. instructions).)
Regarding claim 18, Swaine teaches
A method for a memory management unit comprising: (This preamble does not limit the claim because the body of the claim fully and intrinsically sets forth all of the limitations of the claimed invention, and the preamble merely states the purpose or intended use of the invention (see MPEP 2111.02(II). In this instance, said preamble states the intended use of claim 18 is in a memory management unit.)
receiving an address translation request from a device, the address translation request specifying a first address to be translated; (Swaine teaches endpoint 100 (device) sending virtual address, to be translated, as ATS translation request (address translation request) to SMMU 120 (see Fig. 2, Fig. 3, ¶[40], [43]).)
identifying a page fault associated with the first address; and
directly in response to identifying the page fault associated with the first address, automatically issuing a page request requesting that the page table information corresponding to the first address is updated to correct the page fault (Swaine teaches responsive to said ATS translation request, comprising virtual address (first address) to be translated (see ¶[40]), being unable to be serviced (due to missing address translation or translation fault (page fault) (see ¶[41])), providing a negative response 410 that cause (directly in response) issuing (issuing) of page request (or PRI) (page request) that results in a positive PRI response indicating availability/populating of (update) said address translation (se Fig. 4, ¶[41], [44-45]) in translation tables (page table information) (see ¶[50]) wherein said positive PRI response allows for said ATS translation request to be reissued (see Fig. 4, ¶[46]) (correct page fault). Note that said negative response 410 prompts (automatically) issuance of said page request (see ¶[45]).)
Regarding claim 8, Swaine teaches the memory management unit according to claim 1 where Swaine also teaches
wherein the translation circuitry is configured to identify a page fault in response to determining that the first address does not correspond to valid page table information or that the page table information corresponding to the first address indicates that the device is not allowed to access a memory location corresponding to the first address (Swaine teaches providing ATS translation request with virtual address (first address) that requires translation and there is a translation fault (page fault) due to address translation (page table information) being not available (does not correspond) (see ¶[40-41]) wherein i) said address translation is in access translation tables (table) (see ¶[50]) and ii) said translation fault is detected by translation circuitry 534 (translation circuitry) (see ¶[51]).)
Regarding claim 9, Swaine teaches the memory management unit according to claim 1 where Swaine also teaches
wherein responsive to the translation circuitry identifying a non-correctable page fault associated with the first address, the interface is configured to send a non-correctable page fault response to the device indicating that a non-correctable page fault was encountered (Swaine teaches responsive to ATS translation request, comprising virtual address (first address) to be translated (see ¶[40]), being unable to be serviced (due to missing address translation or translation fault (page fault) (see ¶[41])), sending, via transaction interface 532 (interface) of SMMU 120 (see Fig. 5, ¶[55]), negative response 410 (page fault response) to endpoint 100 (device) (see Fig. 4, ¶[41], [44-45]) wherein said translation fault is fatal translation error (non-correctable) (see Fig. 6, ¶[60], [62]).)
Regarding claim 10, Swaine teaches the memory management unit according to claim 1 where Swaine also teaches
wherein the first address is a virtual address and the second address is any one of a physical address directly indicating a memory location, and an intermediate address different from the physical address (Swaine already teaches in claim 1, servicing ATS translation request, comprising virtual address (first address) to be translated (see ¶[40]), by performing page table walk (translate) to identify address translation (from said virtual address to physical address (second address)) (see Fig. 3, ¶[43-44]) of memory 110 (memory location) (see ¶[35]).)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Swaine in view of Landers (20190155640).
Regarding claim 3, Swaine teaches the memory management unit of claim 1 where page request issuing circuity issues a page request but does not appear to explicitly teach using token with said page request in the following manner.
wherein the page request issuing circuitry is configured to generate a page request token and assign the page request token to the page request
However, Landers teaches
wherein [the page] request issuing circuitry is configured to generate a page request token and assign the page request token to [the page] request (Landers teaches converter module (request issuing circuity) assigning transaction ID (request token) to memory requests (request) (see ¶[35]) wherein said transaction ID is selected (generate) from a pool of available transaction IDs (see ¶[45]).)
In view of Landers, Swaine is modified such that said page request issuing circuity assigns, to said page request, transaction ID (page request token) selected (generated) from a pool of available transaction IDs.
Swaine and Landers are analogous art to the claimed invention because they are in the same field of endeavor, memory management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Swaine in the manner described supra because use of transaction ID allows for request to be performed out-of-order in order to hide MMU miss latency (Landers, ¶[33]).
Regarding claim 5, Swaine in view of Landers teach the memory management unit according to claim 3 where Swaine also teaches
wherein the interface is configured to send, to the device, a page corrected response in response to determining that the page fault associated with the first address has been corrected (Swaine teaches if there is translation fault (page fault) (or no address translation), for virtual address (first address) as ATS translation request (see ¶[40]), sending PRI event that results a PRI response (page corrected response) that indicates said ATS translation request to page is available (corrected) (see Fig. 4, ¶[45-46]) wherein said PRI response is sent via transaction interface 532 (interface) (see Fig. 5, ¶[55]).) (Swaine teaches responsive to ATS translation request, comprising virtual address (first address) to be translated (see ¶[40]), being unable to be serviced (due to missing address translation or page fault (page fault) (see ¶[41])), sending PRI event (page request) that results in positive PRI response (page corrected response) indicating said ATS translation request to page is available (corrected) (see Fig. 4, ¶[41], [44-45]).)
Landers also teaches
[the page corrected] response indicates [the] page request token assigned to [the page] request (Landers teaches returning translation (response) with same transaction ID (page request token) that is assigned to memory request that triggered said translation (see ¶[36]).)
In view of Landers, modified Swaine is further modified such that said page corrected response is sent with same transaction ID (page request token) as said page request that caused said page corrected response.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Swaine in the manner described supra because use of transaction ID allows for requests to be performed out-of-order in order to hide MMU miss latency (Landers, ¶[33]).
Claims 6 – 7 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over Swaine in view of Sharma (US 20240168891).
Regarding claim 6, Swaine teaches the memory management unit according to claim 1 where page request issuing circuity issues page request but does not appear to explicitly teach said page request is issued to a queue (see also limitation below).
wherein the page request issuing circuitry is configured to issue the page request to a page request queue
However, Sharma teaches
wherein [the] page request issuing circuitry is configured to issue [the] page request to a page request queue (Sharma teaches PRI handler (page request issuing circuitry) queueing (issue) page request groups (page request) of page miss requests within host requests queue 1074 (page request queue) (see Fig. 10, ¶[133]).)
In view of Sharma, Swaine is modified such that said page request issuing circuitry queues said page request in host requests queue (queue).
Swaine and Sharma are analogous art to the claimed invention because they are in the same field of endeavor, storage management.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Swaine in the manner described supra because use of PRI handler would prevent pinning large amounts of memory by only pinning pages as needed (Sharma, ¶[31]).
Regarding claim 7, Swaine in view of Sharma teach the memory management unit according to claim 6 where Sharma also teaches
wherein [the] page request queue comprises a queue structure in a region of memory accessible to device management circuitry responsible for controlling assignment of memory pages (Sharma teaches host request queue 1074 (queue) is in controller memory 1012 (region of memory) (see Fig. 10) where page miss requests are transferred from said host request queue 1074 to outbound buffer 1014 (see ¶[137]). Sharma further teaches that said page miss requests are sent (accessible) from said outbound buffer 1014 to translation agent (device management circuitry) which causes re-pinning (controlling assignment) of physical pages (memory pages) corresponding to said page miss requests (see ¶[138]).)
In view of Sharma, modified Swaine is further modified such that said host request queue 1074 (queue), in controller memory (region of memory), has page miss requests that are transferred to (accessible to) translation agent (device management circuitry) which causes re-pinning (controlling assignment) of physical pages (memory pages) corresponding to said page miss requests.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Swaine in the manner described supra because use of PRI handler would prevent pinning large amounts of memory by only pinning pages as needed (Sharma, ¶[31]).
Regarding claim 13, Swaine teaches the memory management unit according to claim 1 where page request is issued due to page fault of first address but does not appear to explicitly teach using translation context in the following manner.
wherein the page request identifies a translation context associated with the first address
However, Sharma teaches
wherein [the] page request identifies a translation context associated with the first address (Sharma teaches PRI handler creating a set of page miss requests (page request) that contains (identifies) virtual address (first address) and PSAID (translation context) (see ¶[133-134]). Note that said virtual address and said PSAID are associated with each other by being part of said set of page miss requests.)
In view of Sharma, Swaine is modified such that said page request includes PSAID (translation context) and said first address.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which said subject matter pertains to modify Swaine in the manner described supra because use of PRI handler would prevent pinning large amounts of memory by only pinning pages as needed (Sharma, ¶[31]).
Claims 15 – 16 are rejected under 35 U.S.C. 103 as being unpatentable over Swaine in view of Takaku (US 20140040680) and Huang (US 20210064527).
Regarding claim 15, Swaine teaches the memory management unit of claim 1.
Swaine teaches a base apparatus with memory management unit (see claim 1). The claimed invention improves upon said base apparatus by integrating said memory management unit in the following manner.
A system comprising:
the memory management unit of claim 1, implemented in at least one packaged chip;
at least one system component; and
a board, wherein the at least one packaged chip and the at least one system component are assembled on the board
This improvement to said base method is merely an application of known technique from Takaku – storing memory controller with chip set on bridge chip. In particular, Takaku teaches
A system comprising:
the memory management unit [of claim 1, implemented in at least one packaged chip];
at least one system component; and
a board, wherein the [at least one packaged chip] and the at least one system component are assembled on the board (Takaku teaches bridge chip (board) with memory controller (memory management unit) and chip set (at least one system component) (see Fig. 2) wherein said bridge chip is part of system board (further board) that also has CPU/DIMM (at least one other product component) (see Fig. 3).)
One of ordinary skill in the art would recognize that this known technique of integrating one type of memory controller can also be applied to integrate another type of memory controller, and the result would have been predictable. In this instance, integration of memory controller with chip set on a bridge chip that is in a system board with CPU/DIMM can be applied to integrate Swaine’s memory management unit. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Takaku’s known technique would have yielded i) predictable result of integrating said memory management unit with chip set (at least one system component) on a bridge chip (board) that is part of system board (further board) that contains CPU/DIMM (at least one other product component), and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Swaine in view of Takaku teach a base apparatus with memory management unit on a bridge chip (board) that is part of system board (further board) that contains CPU/DIMM (at least one other product component) (see claim 15). The claimed invention improves upon said base apparatus by implementing said memory management unit as one packaged chip.
This improvement to said base method is merely an application of known technique from Huang – implementing MMU (memory management unit) as integrated chip (IC) (at least one packaged chip) (see Huang, ¶[87]).
One of ordinary skill in the art would recognize that this known technique of implementing one type of memory controller can also be applied to implement another type of memory controller, and the result would have been predictable. In this instance, implementation of memory management unit as IC can also be applied to implement modified Swaine’s memory management unit. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Huang’s known technique would have yielded i) predictable result of implementing said memory management unit (on a bridge chip (board), with chip set (at least one system component), that is part of system board (further board) that contains CPU/DIMM (at least one other product component)) as IC, and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Regarding claim 16, Swaine in view of Takaku and Huang already teach in claim 15
A chip-containing product comprising the system of claim 15 assembled on a further board with at least one other product component (see claim 15)
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Swaine in view of Chan (US 20200334058).
Regarding claim 17, Swaine teaches
a memory management unit comprising:
an interface configured to receive an address translation request from a device, the address translation request specifying a first address to be translated;
translation circuitry configured to translate the first address specified by the address translation request into a second address, wherein the translation is based on page table information corresponding to the first address,
wherein in response to the translation circuitry performing the translation in response to the address translation request without identifying a page fault associated with the first address, the interface is configured to send an address translation response to the device, the address translation response comprising the second address; and
the memory management unit comprises page request issuing circuitry responsive to the translation circuitry, in response to the address translation request, identifying a page fault associated with the first address, to issue a page request requesting that the page table information corresponding to the first address is updated to correct the page fault (see Swaine mapping for claim 1)
Swaine teaches a base apparatus with memory management unit (see claim 17). The claimed invention improves upon said base apparatus by implementing said memory management unit using code in computer readable medium.
This improvement to said base method is merely an application of known technique from Chan – IOMMU (memory management unit) being fabricated by electronic device reading high-level design language (computer-readable code) in non-transitory computer readable storage medium (see Chan, ¶[78]).
One of ordinary skill in the art would recognize that this known technique of implementing one type of memory controller can also be applied to implement another type of memory controller, and the result would have been predictable. In this instance, use of high-level design language in non-transitory computer readable storage medium to fabricate IOMMU can also be applied to fabricate Swaine’s memory management unit. It would have been obvious to one of ordinary skill in the art at the time of filing to recognize that applying Chan’s known technique would have yielded i) predictable result of fabricating said memory management unit using high-level design language (computer-readable code) in non-transitory computer-readable medium, and ii) the improved claimed invention (see MPEP 2143(I)(D)).
Allowable Subject Matter
Claims 2, 4 and 11 – 12 have been indicated as allowable over prior art in Office Action mailed 10 July 2025.
Response to Remarks
Applicant’s remarks have been fully considered but are not persuasive. Applicant alleges that the claims have been amended to recite that MMU is directly responsive to identifying a page fault to automatically issue a page request. Claims 1 and 17 are not limited to this interpretation. As noted supra, claims 1 and 17 are indefinite due to multiple interpretations, in which one of said interpretations is taught by prior art of record. Claim 18 recites MMU in the preamble which does not further limit claim 18. As such, prior art of record teaches claim 18.
Additional Remarks
In the interest of compact prosecution, it is noted that Swaine further discloses that PRI (from endpoint) is expected but not required (see Swaine ¶[4]) which would result in SMMU issuing PRI event (page request) (see Swaine Fig. 4 and corresponding paragraphs) without said PRI from said endpoint. This would result in MMU itself issuing said PRI event directly responsive to said page fault. Applicant is advised to incorporate one of allowable claims indicated supra.
Conclusion
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/CHIE YEW/ Primary Examiner, Art Unit 2139