DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a response to the amendment filed 2/5/2026. Claims 1, 4-6, 9-12, 14-16 and 18-19 are pending and are under examination.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 4-5, 11, 15, 18 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Rajagopal et al. (USP 10,581,643).
Regarding claims 1, 11, Rajagopal et al.’s figure 3 shows a gate driver circuit comprising a signal source (314A) to generate one or more control signals, an isolation circuit arrangement, configured to receive one or more input signals on a low voltage side (314A capable of being low voltage side) and deliver one or more output signals on a high voltage side (314B capable of being high voltage side), the isolation circuit arrangement comprising an isolation barrier, comprising: a first capacitor (C1B), arranged along a first input line (306); a second capacitor (C2B) arranged along a second input line (308), in electrically parallel fashion to the first capacitor; a first inductor (first inductor on the left of 316B) having a first end that is coupled to a first electrode of the first capacitor and having a second end that is coupled to a first electrode of the second capacitor; a first center tap (350; see column 8, lines 49-56; column 9, line 8, mentions “center output tap”; column 9, line 25-27 also suggests the center tap output can also be connected directly to ground) comprising a connection between first and second ends of the first inductor and configured to redirect current caused in negative common-mode transient events directly to ground (310), (Rajagopal et al.’s column 8, lines 14-34, teaches the center output tap of transformer 316A provides “common mode rejection and to help protect against circuit faults”. Furthermore, the functional limitations of “to redirect current caused in negative common-mode transient events directly to ground” does not add or modify any structural limitations to the first inductor of the claim; they are simply a manner of operation of the center tap. According to MPEP 2114 (II), the manner of operating the device does not differentiate apparatus claims from the prior art. “Apparatus claim cover what a device is, not what a device does.” Hewlett-Packard Co. V. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex Parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987)” ; a second inductor (second coil on the right of 316B) that is inductively coupled to the first inductor and is arranged with a first output end and a second output end on a high voltage side of the isolation circuit arrangement; a third inductor (coil on the right of 316A) having a first end that is coupled to a second electrode of the first capacitor and having a second end that is coupled to a second end of the second capacitor a second center tap (350), connected to the third inductor, wherein the second center tap comprising a connection between the first and second ends of the third inductor and configured to redirect current caused in positive common-mode transient events directly to ground (330, see column 8, lines 49-56; column 9, line 8, mentions “center output tap”; column 9, line 25-27 also suggests the center tap output can also connected directly to ground; Rajagopal et al.’s column 8, lines 14-34, teaches the center output tap of transformer 316A provides “common mode rejection and to help protect against circuit faults. Furthermore, the functional limitations of “to redirect current caused in positive common-mode transient events directly to ground” does not add or modify any structural limitations to the second inductor of the claim; they are simply a manner of operation of the center tap. According to MPEP 2114 (II), the manner of operating the device does not differentiate apparatus claims from the prior art. “Apparatus claim cover what a device is, not what a device does.” Hewlett-Packard Co. V. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex Parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987)”; and a fourth inductor (right coil of 316A) that is inductively coupled to the third inductor and is arranged with a first input end and a second input end on a low voltage side (314A) of the isolation circuit arrangement.as called for in claims 1 and 11.
Regarding claim 4, wherein the first capacitor (C1B), second capacitor (C2B), first inductor (first coil of 316B) and second inductor (a second coil of 316B) are arranged in a first isolation circuit, and the third capacitor, fourth capacitor, third inductor and fourth inductor are arranged in a second isolation circuit.
Regarding claims 5, 15, 18, wherein the first isolation circuit and the second isolation circuit together form the isolation barrier, wherein the first isolation circuit is disposed in a first semiconductor chip (200B, figure 2), the second isolation circuit is disposed in a second semiconductor chip (220A; figure 2), and wherein the first isolation circuit is connected to the second isolation circuit via a pair of conductive connectors (204; figure 2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 9-10, 14, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rajagopal et al. (USP 10,581,643) in view of Takeda et al. (USP 8,774,288).
Regarding claim 14, Rajagopal et al. reference shows an isolation circuit comprising all the aspects of the present invention as noted above except wherein the third inductor, fourth inductor, the first capacitor and second capacitor are disposed in a first semiconductor chip, and wherein the first inductor and second inductor are disposed in a second semiconductor chip as called for in claim 14.
Takeda et al.’s figures 18, 19, 20, 21 and 24-25 teach that isolation circuit can be formed either by itself, on a first chip with a transmitter or on a second chip with a receiver without altering its intended functions. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to have wherein the third inductor, fourth inductor, and the first capacitor and second capacitor are disposed in a first semiconductor chip, and wherein the first inductor and second inductor are disposed in a second semiconductor chip as taught by Takeda et al. reference.
Regarding claims 9 and 10, Rajagopal et al. reference shows an isolation circuit comprising all the aspects of the present invention as noted above except the first semiconductor chip or the second semiconductor chip is a silicon-on-insulator chip as called for in claims 9 and 10.
Takeda et al.’s figures 18, 19, 20, 21 and 24-25 teach that isolation circuit can be formed either by itself, on a first chip with a transmitter or on a second chip with a receiver without altering its intended functions. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to have the first semiconductor chip or the second semiconductor chip is a silicon-on-insulator chip as taught by Takeda et al. reference.
Regarding claim 16, Rajagopal et al. reference shows an isolation circuit comprising all the aspects of the present invention as noted above except wherein the isolation barrier is arranged in a single semiconductor chip as called for in claim 16.
Takeda et al.’s figures 18, 19, 20, 21 and 24-25 teach that isolation circuit can be formed either by itself, on a first chip with a transmitter or on a second chip with a receiver without altering its intended functions. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to have the isolation barrier is arranged in a single semiconductor chip as taught by Takeda et al. reference.
Claim(s) 6, 12 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Rajagopal et al. (USP 10,581,643) in view of May et al. (US 2023/0387782).
Regarding claims 6, 12 and 19, Rajagopal et al.’s discloses a gate driver comprising an isolation circuit comprising all the aspects of the invention as noted above except for a demodulator, arranged on the high voltage side; and a gate driver, coupled to the demodulator, and arranged to output a gate drive signal to a high side switch as called for in claims 6, 12 and 19.
May et al.’s figures 2A, 10 and 12 shows a receiver coupled to an isolation circuit. The receiver comprises demodulation circuit (1007), gate driver (1010) and arranged to output a gate drive signal (1020) to a high side switch (232, figure 2a). Thus, it would have been obvious to person skilled in the art before the effective filing date of the invention to have May et al.’s demodulator, gate driver and high side switch arranged in Rajagopal et al.’s circuit arrangement as taught by May et al. reference.
Claim(s) 1, 4-6, 11-12, 15-16 and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Manikandan et al. (US 2023/002575) in view of Brown (US 2006/0109918) and Glasband (RE39108).
Regarding claims 1, 11-12, Manikandan et al.’s figures 1A and 1B disclose a gate driver comprising a signal source (132, figure 1A) to generate one or more control signals, an isolation circuit arrangement (166), configured to receive one or more input signals on a low voltage side (102; figure 1A being low voltage side) and deliver one or more output signals on a high voltage side (104, figure 1B capable of being high voltage side), the isolation circuit arrangement comprising an isolation barrier, comprising: a first capacitor (156), arranged along a first input line (150); a second capacitor (158) arranged along a second input line (154), in electrically parallel fashion to the first capacitor; a first inductor (162a) having a first end that is coupled to a first electrode of the first capacitor and having a second end that is coupled to a first electrode of the second capacitor; and a second inductor (162B) that is inductively coupled to the first inductor and is arranged with a first output end and a second output end on a high voltage side of the isolation circuit arrangement, a third inductor (138b) having a first end that is coupled to a second electrode of the first capacitor and having a second end that is coupled to a second end of the second capacitor, and a fourth inductor that is inductively coupled to the third inductor and is arranged with a first input end and a second input end on a low voltage side of the isolation circuit arrangement, a demodulator (168) coupled to the second inductor; and a gate driver (172), coupled to the demodulator, and arranged to output a gate drive signal to a power switch (176).
Manikandan et al. does not show a first center tap comprising a connection between first and second ends of the first inductor and configured to redirect current caused by negative common mode transients directly to ground; and a second center tap comprising a connection between first and second ends of the third inductor and configured to redirect current caused in positive common mode transient events directly to ground as called for in claims 1, 11 and 12. However, it is a common knowledge in an electrical distribution systems, grounding the center tap provides a reference point for the system and helps prevent unwanted voltage potentials, i.e., achieving symmetrical outputs (see abstract of Glasband et al. RE39108). The connection of a center to ground is also illustrated in Brown’s figure 5. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to have a center tap connected to the first inductor for the purpose of preventing unwanted voltage potentials.
Note, the functional limitations of the first center tap redirects current caused by negative common mode transients directly to ground; and the second center tap redirects current caused by positive common mode transients directly to ground does not add or modify any structural limitations to the first inductor/the second inductor of the claim; they are simply a manner of operation of the center tap. According to MPEP 2114 (II), the manner of operating the device does not differentiate apparatus claims from the prior art. “Apparatus claim cover what a device is, not what a device does.” Hewlett-Packard Co. V. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex Parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Thus, the limitations of redirecting current caused by negative common mode transients directly to ground; and redirecting current caused by positive common mode transients directly to ground are also met.
Regarding claim 16, wherein the isolation barrier is arranged in a single semiconductor chip (Manikandan et al.’s figure 3).
Regarding claim 4, Manikandan et al.’s figures 1A and 1B shows wherein the first capacitor, second capacitor, first inductor and second inductor are arranged in a first isolation circuit, and the second isolation circuit comprising: the third capacitor (144), the fourth capacitor (146); the third inductor (138b) and the fourth inductor are arranged in a second isolation circuit.
Regarding claims 5 and 18, Manikandan et al.’s figures 1A and 1B shows the first isolation circuit and the second isolation circuit together form an isolation barrier, wherein the first isolation circuit is disposed in a first semiconductor chip (transmitter side), the second isolation circuit is disposed in a second semiconductor chip (receiver side), and wherein the first isolation circuit is connected to the second isolation circuit via a pair of conductive connectors.
Regarding claims 6, 12 and 19, Manikandan et al.’s figures 1A and 1B shows a transmitter, and the second semiconductor chip further comprising a demodulator (168) and a gate driver (172).
Regarding claim 15, , Manikandan et al.’s figures 1A and 1B wherein the first capacitor, second capacitor, first inductor and second inductor are arranged in a first isolation circuit, wherein the first isolation circuit is arranged in a first chip (104), and wherein the third inductor and the fourth inductor are arranged in a second semiconductor chip (102).
Claim(s) 9-10, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Manikandan et al. (US 2023/002575), Glasband (RE39108), Brown (US 2006/0109918) and further in view of Takeda et al. (USP 8,774,288).
Regarding claim 14, the combination of Manikandan et al. (US 2023/002575) and Brown and Glasband references shows an isolation circuit comprising all the aspects of the present invention as noted above except wherein the third inductor, the fourth inductor, the first capacitor and the second capacitor are disposed in a first semiconductor chip, and wherein the first inductor and second inductor are disposed in a second semiconductor chip as called for in claim 14.
Takeda et al.’s figures 18, 19, 20, 21 and 24-25 teach that isolation circuit can be formed either by itself, on a first chip with a transmitter or on a second chip with a receiver without altering its intended functions. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to have wherein the third inductor, the fourth inductor, the first capacitor and the second capacitor are disposed in a first semiconductor chip, and wherein the first inductor and second inductor are disposed in a second semiconductor chip as taught by Takeda et al. reference.
Regarding claims 9 and 10, the combination of Manikandan et al. (US 2023/002575), Brown and Glasband references shows an isolation circuit comprising all the aspects of the present invention as noted above except the first/second semiconductor chip is a silicon-on-insulator chip as called for in claims 9 and 10.
Takeda et al.’s figures 18, 19, 20, 21 and 24-25 teach that isolation circuit can be formed either by itself, on a first chip with a transmitter or on a second chip with a receiver without altering its intended functions. Therefore, it would have been obvious to person skilled in the art before the effective filing date of the invention to have either the first or second semiconductor chip is a silicon-on-insulator chip as taught by Takeda et al. reference.
Response to Arguments
Applicant's arguments filed 12/5/2025 have been fully considered but they are not persuasive. Regarding the rejection of claims 1, 4-5, 11, 15, 18 as being anticipated by Rajagopal et al. (USP 10,581,643), applicant argues that Rajagopal does not teach/disclose “the first center tap redirects current caused by negative common mode transients directly to ground”; and “the second center tap redirects current caused by positive common mode transients directly to ground” found not persuasive. The recited functional limitation does not add or modify any structural limitations to the first inductor/the second inductor of the claim; they are simply a manner of operation of the center tap. According to MPEP 2114 (II), the manner of operating the device does not differentiate apparatus claims from the prior art. “Apparatus claim cover what a device is, not what a device does.” Hewlett-Packard Co. V. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex Parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Thus, the limitations of redirecting current caused by negative common mode transients directly to ground; and redirecting current caused by positive common mode transients directly to ground are met.
Regarding the rejection of 1, 4-6, 11-12, 15-16 and 18-19 as being unpatentable over Manikandan et al. (US 2023/002575) in view of Brown (US 2006/0109918) and Glasband (RE39108), applicant argues that the combination of references does not teach or disclose the functional limitations “the first center tap redirects current caused by negative common mode transients directly to ground”; and “the second center tap redirects current caused by positive common mode transients directly to ground” found not persuasive. The recited functional limitation does not add or modify any structural limitations to the first inductor/the second inductor of the claim; they are simply a manner of operation of the center tap. According to MPEP 2114 (II), the manner of operating the device does not differentiate apparatus claims from the prior art. “Apparatus claim cover what a device is, not what a device does.” Hewlett-Packard Co. V. Bausch & Lomb Inc., 909 F.2d 1464, 1469, 15 USPQ2d 1525, 1528 (Fed. Cir. 1990). A claim containing a “recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus” if the prior art apparatus teaches all the structural limitations of the claim. Ex Parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Thus, the limitations of redirecting current caused by negative common mode transients directly to ground; and redirecting current caused by positive common mode transients directly to ground are met.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TUAN THIEU LAM whose telephone number is (571)272-1744. The examiner can normally be reached Monday-Friday, 8:30 am to 5:00 pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Regis Betsch can be reached at 571-270-7101. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/TUAN T LAM/Primary Examiner, Art Unit 2842 4/12/2026
Prosecution Insights