DETAILED ACTION
Claims 1-20 are pending, with claims 10-12 being withdrawn.
The office acknowledges the following papers:
Claims, specification, and remarks filed on 2/26/2026.
Withdrawn objections and rejections
The specification objections have been withdrawn due to amendment.
New Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-9 and 13-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without either reciting additional elements that integrate the judicial exception into a practical application or reciting additional elements that amount to significantly more than the judicial exception. Independent claims 1, 15-16, and 18 recite a mental process of selectively processing fused instructions to generate separate m separate instructions. All of the claims are directed towards a process, machine manufacture, or a composition of matter.
The step of selectively processing fused instructions to generate separate m separate instructions is a process that, under its broadest reasonable interpretation, covers a mental process of the mind with the aid of pen and paper but for the recitation of generic computer components (e.g. hardware circuitry, pre-processing hardware circuitry, processing pipeline). Additionally, dependent claims 2-4 and 19-20 only add further abstractions that can be performed as a mental process of the mind with the aid of pen and paper (e.g. category data, passing fused operations for execution, generate instructions from fused instructions capable of execution) but for the recitation of generic computer components (e.g. hardware circuitry, pre-processing hardware circuitry).
This judicial exception is not integrated into a practical application. In particular, the claim only recites “hardware circuitry, pre-processing hardware circuitry, processing pipeline, etc.” to perform the “selectively processing fused instructions to generate separate m separate instructions” steps. The “hardware circuitry, pre-processing hardware circuitry, processing pipeline, etc.” is recited at a high-level of generality such that it amounts to no more than mere instructions to apply the exception using a generic computer component. Therefore, this additional element doesn’t integrate the abstract idea into a practical application because it doesn’t impose any meaningful limits on practicing the abstract idea.
The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. Dependent claims 6-9, 13-14, and 16-17 include additional elements (e.g. coprocessor, processor, buffer circuitry, decoder circuitry, boards, packaged chip, routing, multiple apparatuses, etc.) that do not amount to significantly more than the judicial exception. Thus, the claims are directed towards an abstract idea and aren’t patent eligible.
New Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-9, 15, and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Kesiraju et al. (U.S. 2022/0137975), herein Kesiraju (975), in view of Kesiraju et al. (U.S. 2022/0083343), herein Kesiraju (343).
As per claim 1:
Kesiraju (975) and Kesiraju (343) disclosed apparatus comprising:
communication hardware circuitry configured to receive instructions including fused instructions communicated by further hardware circuitry (Kesiraju (975): Figures 1-2 and 6 elements 10-12, 20, 34-36, 40, and 122, paragraphs 27-28, 31, 35, 41, 46, 51, 56, and 69)(Kesiraju (975) disclosed a coprocessor instruction buffer (i.e. communication hardware circuitry) that receives coprocessor instruction bundles (i.e. instructions/fused instructions) from the CPU processor (i.e. further hardware circuitry). Additionally, the CPU processor can fuse coprocessor instructions together to increase bundling efficiency.);
processing hardware circuitry including a processing pipeline configured to execute instructions and perform data processing operations corresponding to the instructions (Kesiraju (975): Figure 6 element 130, paragraphs 81 and 91)(The coprocessor includes a pipeline to execute coprocessor instructions.); and
fused instruction pre-processing hardware circuitry configured to selectively process a given fused instruction received from the communication hardware circuitry and representing a fusion of n individual instructions, where n is an integer greater than 1, and to generate m separate instructions for execution by the processing hardware circuitry, where m is an integer greater than one and less than or equal to n (Kesiraju (343): Figure 10 elements 112-116, paragraphs 26, 29, and 58)(Kesiraju (975): Figures 1 and 6 elements 10, 122, and 130, paragraphs 27, 69, 81, and 91)(Kesiraju (343) disclosed a coprocessor receiving coprocessor bundles. Kesiraju (343) also disclosed a coprocessor decoder (i.e. pre-processing hardware circuitry) to decode instructions from the buffer into one or more operations for processing. The combination implements the decoder and Op Queue of Kesiraju (343) into the coprocessor of Kesiraju (975). The coprocessor decoder allows for generating one-for-one decoded operations (i.e. m instructions) for each instruction in the coprocessor bundle (i.e. n instructions). Additionally, fused coprocessor instructions in a coprocessor bundle can be decoded into one or more operations for execution.).
Kesiraju (975) discusses that the coprocessor may include a pipeline to decode coprocessor operations, perform register renaming, and executing coprocessor operations, but doesn’t provide a more specific implementation in the drawings/specification (see paragraph 91). One of ordinary skill in the art at the time of the effective filing date would have been motivated by this lack of teaching to find a copending application by the same inventor that describes coprocessor operations further in depth. Thus, it would have been obvious to one of ordinary skill in the art at the time of the effective filing date to implement the coprocessor details of Kesiraju (343) into the coprocessor of Kesiraju (975) for the advantage of filling in the coprocessor details that are lacking.
As per claim 2:
Kesiraju (975) and Kesiraju (343) disclosed the apparatus of claim 1, in which the fused instruction pre-processing hardware circuitry is responsive to category data defining one or more categories of fused instructions which the processing hardware circuitry is capable of executing (Kesiraju (343): Figure 10 elements 112-116, paragraphs 26, 29, and 58)(Kesiraju (975): Figures 1 and 6 elements 10, 122, and 130, paragraphs 27, 69, 81, and 91)(Kesiraju (343) disclosed a coprocessor receiving coprocessor bundles. Kesiraju (343) also disclosed a coprocessor decoder to decode instructions from the buffer into one or more operations for processing. The combination implements the decoder and Op Queue of Kesiraju (343) into the coprocessor of Kesiraju (975). The coprocessor decoder allows for generating one-for-one decoded operations (i.e. m instructions) for each instruction in the coprocessor bundle (i.e. n instructions). Additionally, fused coprocessor instructions in a coprocessor bundle can be decoded into one or more operations for execution. The coprocessor instruction types include at least vector, matrix, and load/store operations (i.e. categories).).
As per claim 3:
Kesiraju (975) and Kesiraju (343) disclosed the apparatus of claim 2, in which the fused instruction pre-processing hardware circuitry is configured to detect a category associated with a fused instruction received from the further hardware circuitry with the category data and, when the category associated with the fused instruction received from the further hardware circuitry indicates that the processing hardware circuitry is capable of executing that fused instruction, to pass that fused instruction to the processing hardware circuitry for execution (Kesiraju (343): Figure 10 elements 112-120, paragraphs 26, 29, and 58)(Kesiraju (975): Figures 1 and 6 elements 10, 122, and 130, paragraphs 27, 69, 81, and 91)(Kesiraju (343) also disclosed a coprocessor decoder to decode instructions from the buffer into one or more operations for processing. The combination implements the decoder and Op Queue of Kesiraju (343) into the coprocessor of Kesiraju (975). The decoded coprocessor instruction is passed to the compute circuit for execution.).
As per claim 5:
Kesiraju (975) and Kesiraju (343) disclosed the apparatus of claim 1, in which m is equal to n (Kesiraju (343): Figure 10 elements 112-116, paragraphs 26, 29, and 58)(Kesiraju (975): Figures 1 and 6 elements 10, 122, and 130, paragraphs 27, 69, 81, and 91)(Kesiraju (343) disclosed a coprocessor receiving coprocessor bundles. Kesiraju (343) also disclosed a coprocessor decoder to decode instructions from the buffer into one or more operations for processing. The combination implements the decoder and Op Queue of Kesiraju (343) into the coprocessor of Kesiraju (975). The coprocessor decoder allows for generating one-for-one decoded operations (i.e. m instructions) for each instruction in the coprocessor bundle (i.e. n instructions).
As per claim 6:
Kesiraju (975) and Kesiraju (343) disclosed the apparatus of claim 1, in which the apparatus is a coprocessor and the hardware further circuitry is a processor (Kesiraju (975): Figures 1-2 and 6 elements 10-12, 20, 34-36, 40, and 122, paragraphs 27-28, 31, 35, 41, 46, 51, 56, and 69)(Kesiraju (975) disclosed a coprocessor instruction buffer within the coprocessor (i.e. apparatus) that receives coprocessor instruction bundles from the CPU processor (i.e. further circuitry).).
As per claim 7:
Kesiraju (975) and Kesiraju (343) disclosed the apparatus of claim 6, wherein the hardware communication circuitry is configured to receive additional instructions communicated to the apparatus by the further circuitry (Kesiraju (975): Figures 1-2 and 6 elements 10-12, 20, 34-36, 40, and 122, paragraphs 27-28, 31, 35, 41, 46, 51, 56, and 69)(Kesiraju (975) disclosed a coprocessor instruction buffer (i.e. communication circuitry) that receives and buffers coprocessor instruction bundles from the CPU processor (i.e. further circuitry). Additional instruction bundles are received over time.).
As per claim 8:
Kesiraju (975) and Kesiraju (343) disclosed the apparatus of claim 1, comprising buffer circuitry configured to buffer instructions communicated to the apparatus from the hardware further circuitry (Kesiraju (975): Figures 1-2 and 6 elements 10-12, 20, 34-36, 40, and 122, paragraphs 27-28, 31, 35, 41, 46, 51, 56, and 69)(Kesiraju (975) disclosed a coprocessor instruction buffer (i.e. buffer circuitry) that receives and buffers coprocessor instruction bundles from the CPU processor (i.e. hardware further circuitry).).
As per claim 9:
Kesiraju (975) and Kesiraju (343) disclosed the apparatus of claim 1, comprising hardware decoder circuitry configured to decode instructions for execution by the hardware processing circuitry (Kesiraju (343): Figure 10 elements 112-116, paragraphs 26, 29, and 58)(Kesiraju (975): Figures 1 and 6 elements 10, 122, and 130, paragraphs 27, 69, 81, and 91)(Kesiraju (343) also disclosed a coprocessor decoder to decode instructions from the buffer into one or more operations for processing. The combination implements the decoder and Op Queue of Kesiraju (343) into the coprocessor of Kesiraju (975).).
As per claim 15:
Claim 15 essentially recites the same limitations of claim 1. Therefore, claim 15 is rejected for the same reasons as claim 1.
As per claim 18:
Claim 18 essentially recites the same limitations of claim 1. Therefore, claim 18 is rejected for the same reasons as claim 1.
Claims 4, 13-14, 16-17, and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Kesiraju et al. (U.S. 2022/0137975), herein Kesiraju (975), in view of Kesiraju et al. (U.S. 2022/0083343), herein Kesiraju (343), further in view of Official Notice.
As per claim 4:
Kesiraju (975) and Kesiraju (343) disclosed the apparatus of claim 3, in which, when the category associated with the fused instruction received from the further hardware circuitry indicates that the processing hardware circuitry is incapable of executing that fused instruction, the fused instruction pre-processing hardware circuitry is configured to process that fused instruction to generate separate instructions of a category which the category data indicates is capable of execution by the processing hardware circuitry (Kesiraju (343): Figure 10 elements 112-120, paragraphs 26, 29, and 58)(Kesiraju (975): Figures 1 and 6 elements 10, 122, and 130, paragraphs 27, 69, 81, and 91)(Kesiraju (343) also disclosed a coprocessor decoder to decode instructions from the buffer into one or more operations for processing. The combination implements the decoder and Op Queue of Kesiraju (343) into the coprocessor of Kesiraju (975). The decoded coprocessor instruction is passed to the compute circuit for execution. Official notice is given that processing systems can decode large, complex instructions not supported by execution circuitry into multiple ISA supported instructions for the advantage of executing all received operations. Thus, it would have been obvious that the instructions broken into multiple operations for coprocessor execution of Kesiraju (975) are instructions not supported by the coprocessor.).
As per claim 13:
Kesiraju (975) and Kesiraju (343) disclosed a system comprising a plurality of apparatuses (Kesiraju (975): Figure 9 elements 202 and 208, paragraphs 108-110)(Official notice is given that processing systems can be duplicated across multiple motherboards in processing servers for the advantage of providing high performance processing results. Thus, it would have been obvious to one of ordinary skill in the art to implement multiple motherboards in a server.) each according to claim 2, in which:
each apparatus is associated with respective data defining one or more categories of fused instructions which the hardware processing circuitry of that apparatus is capable of executing (Kesiraju (975): Figures 1-2 and 6 elements 10-12, 20, 34-36, 40, and 122, paragraphs 27-28, 31, 35, 41, 46, 51, 56, and 69)(Kesiraju (975) disclosed a coprocessor instruction buffer (i.e. communication circuitry) that receives coprocessor instruction bundles (i.e. instructions/fused instructions) from the CPU processor (i.e. further circuitry). Additionally, the CPU processor can fuse coprocessor instructions together to increase bundling efficiency. In view of the above official notice, each coprocessor of the processing systems receives coprocessor bundles.), the respective data for one apparatus of the plurality of apparatuses defining at least one category of fused instructions different to those defined by the respective data for another different apparatus of the plurality of apparatuses (Kesiraju (975): Figures 1-2 and 6 elements 10-12, 20, 34-36, 40, and 122, paragraphs 27-28, 31, 35, 41, 46, 51, 56, and 69)(Kesiraju (975) disclosed a coprocessor instruction buffer (i.e. communication circuitry) that receives coprocessor instruction bundles (i.e. instructions/fused instructions) from the CPU processor (i.e. further circuitry). Additionally, the CPU processor can fuse coprocessor instructions together to increase bundling efficiency. In view of the above official notice, each coprocessor of the processing systems receives coprocessor bundles. Further, official notice is given that systems implementing multiple coprocessors can include heterogeneous coprocessors for the advantage of implementing additional accelerated functions at a lower cost. Thus, it would have been obvious to one of ordinary skill in the art to implement heterogenous coprocessors in the duplicated processing system of Kesiraju (975).).
As per claim 14:
Kesiraju (975) and Kesiraju (343) disclosed the system of claim 13, comprising:
one or more further hardware circuitries (Kesiraju (343): Figure 1 elements 10A-N, paragraph 26)(Kesiraju (975): Figure 1 element 12, paragraph 26)(Kesiraju (343) disclosed a plurality of processors that can send coprocessor bundles to a single coprocessor. The combination implements multiple processors into the processing system of Kesiraju (975).); and
routing hardware circuitry configured to selectively allow a given one of the further circuitries to communicate instructions to a given one of the plurality of apparatuses (Kesiraju (343): Figure 1 elements 10A-N and 12, paragraphs 26-27)(Kesiraju (975): Figure 1 element 12, paragraph 26)(Kesiraju (343) disclosed a plurality of processors that can send coprocessor bundles to a single coprocessor. Kesiraju (343) also disclosed a coprocessor arbiter that selects a coprocessor to send coprocessor bundles to the coprocessor. The combination implements multiple processors and arbiter into the processing system of Kesiraju (975).).
As per claim 16:
Claim 16 essentially recites the same limitations of claim 1. Claim 16 additionally recites the following limitations:
at least one system component (Kesiraju (975): Figure 9 element 208, paragraph 110); and
a board (Kesiraju (975): Figure 9 elements 202 and 208, paragraphs 108-110)(Official notice is given that processors and RAM can be assembled on motherboards for the advantage of providing data transfers between external memory and processing elements. Thus, it would have been obvious to one of ordinary skill in the art to implement a motherboard within Kesiraju (975) to provide data transfers between components.),
wherein the at least one packaged chip and the at least one system component are assembled on the board (Kesiraju (975): Figure 9 elements 202 and 208, paragraphs 108-110)(In view of the above official notice, a motherboard is implemented to provide data transfers between components (i.e. processor, coprocessor, external memory).).
As per claim 17:
Kesiraju (975) and Kesiraju (343) disclosed a chip-containing product comprising the system of claim 16, wherein the system is assembled on a further board with at least one other product component (Kesiraju (975): Figure 9 elements 202 and 208, paragraphs 108-110)(Official notice is given that processing systems can be duplicated across multiple motherboards in processing servers for the advantage of providing high performance processing results. Thus, it would have been obvious to one of ordinary skill in the art to implement multiple motherboards in a server.).
As per claim 19:
Kesiraju (975) and Kesiraju (343) disclosed the apparatus of claim 1, in which the fused instruction pre-processing hardware circuitry is configured to generate the m separate instructions for execution by the processing hardware circuitry in response to determining that the fused instruction pre-processing circuitry that the hardware processing circuitry is not capable of executing the given fused instruction (Kesiraju (343): Figure 10 elements 112-120, paragraphs 26, 29, and 58)(Kesiraju (975): Figures 1 and 6 elements 10, 122, and 130, paragraphs 27, 69, 81, and 91)(Kesiraju (343) also disclosed a coprocessor decoder to decode instructions from the buffer into one or more operations for processing. The combination implements the decoder and Op Queue of Kesiraju (343) into the coprocessor of Kesiraju (975). The decoded coprocessor instruction is passed to the compute circuit for execution. Official notice is given that processing systems can decode large, complex instructions not supported by execution circuitry into multiple ISA supported instructions for the advantage of executing all received operations. Thus, it would have been obvious that the instructions broken into multiple operations for coprocessor execution of Kesiraju (975) are instructions not supported by the coprocessor.).
As per claim 20:
The additional limitation(s) of claim 20 basically recite the additional limitation(s) of claim 19. Therefore, claim 20 is rejected for the same reason(s) as claim 19.
Response to Arguments
The arguments presented by Applicant in the response, received on 2/26/2026 are not considered persuasive.
Applicant argues regarding the 101 rejections:
“Amended claims 1 and 15 refer to communication hardware circuitry, processing hardware circuitry, and fused instruction pre-processing hardware circuitry. The circuitries recited in these claims would have been understood by a POSITA to be hardware. In addition, claim 1 now recites "processing hardware circuitry configured to execute instructions and perform data processing operations corresponding to the instructions." Analogous language is recited in claim 15.
These claim features are not "a mental process." Rather, claims 1 and 15 require specific hardware circuitry implemented, for example, in a coprocessor, such as the example shown in Fig. 7. The human mind does not include such hardware circuitries which cannot be practically performed in the human mind.1 Nor can the human mind practically perform the functions of the claimed hardware fused instruction pre-processing circuitry including "selectively process a given fused instruction received from the communication circuitry and representing a fusion of n individual instructions, where n is an integer greater than 1, and [] generate m separate instructions for execution by the processing circuitry, where m is an integer greater than one and less than or equal to n."
Contrary to the assertions in the OA, the combination of features recited in claims 1 and 15 improve the processing capabilities of data processors. As explained on page 7, lines 14 to 16 of the specification, "Processors such as the processor of Figure 4 or indeed any of the coprocessors shown in Figures 1 to 3 may support so-called instruction fusion. A 'fusible group' of instructions may be more efficiently handled as a fused instruction rather than as individual instructions." That efficiency only makes sense in the context of a data processing apparatus and not in the human mind.
Regarding dependent claims 4, 19, and 20, as further explained on page 22, lines 18-20: "The fused instruction processor compares a received fused instruction with the coprocessor capability data and, when the received fused instruction lies outside the capabilities of the coprocessor, at least partially unfuses the instruction." Page 23, lines 33-36 explains: "This unfusing capability opens up the possibility of so-called aggressive fusing at the processor. Here, fusing is carried out to a potentially greater extent than the capabilities at the coprocessor would allow execution. To cope with the fused instructions, unfusing is applied at the coprocessor where necessary."”
This argument is not found to be persuasive for the following reason. The added hardware circuitry limitations amount to generic hardware that doesn’t amount significantly more than the judicial exception nor integrating the judicial exception into a practical application. The step of unfusing instructions is a mental step that can be performed in the mind or with the use of pen and paper. For example, one can mentally, or with the use of pen and paper, unfuse a MAC instruction into separate multiply and addition instructions. Additionally, one can mentally look at a list of ISA instructions on paper and perform the same unfusing of a MAC instruction, for example. Thus, the 101 rejections, updated with more detail, have largely been maintained.
Applicant argues regarding claims 1 and 15:
“The OA refers to the bundling of instructions described in paragraph [0026] of Kesiraju 343 and maps this bundle of instructions to the claimed "fused instruction." This is not reasonable. A plurality of separate instructions grouped into a bundle of instructions is not a fused instruction (where multiple instructions are fused together into a single instruction). A POSITA would have understood that instruction bundling and instruction fusion are different techniques that cannot be mapped to one another.
In fact, both Kesiraju 975 and Kesiraju 343 do not disclose "instruction fusion." Kesiraju 343 discloses that instruction bundling simply sending a group of instructions (e.g., a cache line) to the coprocessor arbiter 12. There is no teaching or suggestion that these bundled instructions are fused into a single instruction.”
This argument is not found to be persuasive for the following reason. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e. instruction fusion) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Instead, the claims only recite receiving fused instructions, but not the active step of fusing instructions together.
The examiner agrees that the general techniques of instruction bundling and fusion are different. However, the claims, as is, using a BRI of fusion allows for both techniques to read upon the claimed language. Multiple instructions are fused into an instruction bundle before being sent to the coprocessor. Additionally, Kesiraju (975) allows for the CPU to perform instruction fusing (see paragraph 41). Such fused instructions would also be added to an instruction bundle to be passed to the coprocessor. Lastly, Kesiraju (343) disclosed decoding received instructions into a plurality of operations in an embodiment. Thus, the combination reads upon the claimed limitations.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The following is text cited from 37 CFR 1.111(c): In amending in reply to a rejection of claims in an application or patent under reexamination, the applicant or patent owner must clearly point out the patentable novelty which he or she thinks the claims present in view of the state of the art disclosed by the references cited or the objections made. The applicant or patent owner must also show how the amendments avoid such references or objections.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACOB A. PETRANEK whose telephone number is (571)272-5988. The examiner can normally be reached on M-F 8:00-4:30.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jyoti Mehta can be reached on (571) 270-3995. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JACOB PETRANEK/Primary Examiner, Art Unit 2183
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