Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Claims 1 and 10 have been amended. Claims 1-26 are pending.
Regarding claims 1, 5-6, 10 and 14-15, Applicant’s arguments, filed 01/13/2026, have been fully considered and are moot in view of new rejection as presented infra.
Regarding claims 19 and 22, Applicant argued that:
“original claim 19 recites, in relevant part, a memory controller that enables writing of each event, or event-related data, associated with a certain pixel to a certain address in a memory, wherein the memory controller assigns each pixel a dedicated address of the memory.
Claim 19 is not anticipated by Park for at least the reason that Park does not disclose “assign[ing] each pixel a dedicated address of the memory.” Park describes determining “event address information” for storage based on “time information” (e.g., via a hash function) and using “image address information” mapped to “range information” (time ranges) to identify memory areas for images corresponding to time windows. While Park may include sensing-element address information in event signals, Park does not describe dedicating a particular memory address to each pixel (as opposed to writing events into memory areas indexed by time/time-range).”
The Examiner respectfully disagrees. As presented by the Examiner in the previous office action Park the image address information is uniquely mapped to a range information, and indicate a memory area in which the image including the event signals belonging to the range information is to be stored. The storing apparatus determines event address information corresponding to the time information T=106 using a hash function 220. The hash function 220 refers to a function to output event address information corresponding to input time information. For example, a look-up table in which time information and event address information are mapped to each other is used. The time information and the event address information is uniquely mapped to each other (as illustrated by Figs. 1-2&7, [0058]-[0062]).
Furthermore, Park disclosed that the vision sensor 140 may utilize address information or address/time information of a sensing element sensing a light change event ([0048]). The communicator 110 may receive an event signal from the vision sensor 140. The communicator 110 may receive from the vision sensor 140, the event signal time-asynchronously generated in response to a light change event ([0049]). The processor 120 may store the event signal in the memory 130 based on event address information corresponding to time information related to a time at which the event signal is received ([0050]); and the processor 120 may verify whether an image including the event signals is stored in the memory 130 based on image address information corresponding to the range information. The image address information may be uniquely mapped to the range information, and indicate a memory area in which the image including the event signals belonging to the range information is to be stored ([0056]). Accordingly, Park’s suggest using vision sensor address information or address/time information in the event signal later used in the unique mapping operation (Examiner note at least indirectly).
In response to applicant's argument that the references fail to show certain features of applicant's invention, it is noted that the features upon which applicant relies “writing events into memory areas indexed by time/time-range” are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993).
Based on the foregoing analysis, the Examiner believe that instant references teaches the structural limitations as cited above, and therefore meets the claim limitations as recited.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory obviousness-type double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); and In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on a nonstatutory double patenting ground provided the conflicting application or patent either is shown to be commonly owned with this application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement.
Effective January 1, 1994, a registered attorney or agent of record may sign a terminal disclaimer. A terminal disclaimer signed by the assignee must fully comply with 37 CFR 3.73(b).
Regarding Claims 1-9, 10-14, 15, 16-19, 20, 21 and 22, are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable respectively over claims 1-9, 14-18, 15, 20-23, 1&8, 1&22 and 14&21 of U.S. Patent No. 11,212,468 B2 (See Tab. below). Although the conflicting claims are not identical, they are not patentably distinct from each other because claims 1-9, 10-14, 15, 16-19, 20, 21 and 22 of the instant application are obviousness by respectively over claims 1-9, 14-18, 15, 20-23, 1&8, 1&22 and 14&21 of U.S. Patent 11,212,468 B2, in that claims 1-9, 14-18, 15, 20-23, 1&8, 1&22 and 14&21 of the U.S. Patent contain all the limitations of claims 1-9, 10-14, 15, 16-19, 20, 21 and 22 of the instant application. Claims 1-9, 10-14, 15, 16-19, 20, 21 and 22 of the instant application are therefore not patently distinct from the earlier U.S. Patent claim and such is unpatentable for obvious-type double patenting.
Instant Application
US 11,212,468 B2
1. An event-based vision sensor system, comprising: an event-based pixel array comprising pixels that detect light; a readout circuit for reading out events associated with light received by each pixel and with the position it occupies in the array; and a memory controller that enables writing of each event, or event-related data, associated with a certain pixel to a certain address in a memory; wherein the memory controller implements a mapping between pixels of the event-based pixel array and addresses in the memory,
.
2. The as claimed in claim 1, wherein the memory controller that ensures that the position of that address in the memory in which that event or event-related data is written, is a function of the position in the pixel array occupied by the pixel that generated that event.
3. The as claimed in claim 1, wherein the memory can be written by the memory controller and independently read from outside.
4. The as claimed in claim 1, which is implemented as three-dimensional integrated circuit.
5. The as claimed in claim 1, wherein the memory controller implements a one-to-one mapping between pixels of the event-based pixel array and addresses in the memory.
6. The as claimed in claim 1, wherein the memory controller assigns each pixel a dedicated address or range of addresses of the memory and wherein the memory address dedicated to a certain pixel is a function of a location of that certain pixel in the array.
7. The as claimed in claim 1, wherein the memory controller stores timestamps in the memory.
8. The as claimed in claim 1, wherein the memory controller maintains a buffer index in the memory for last time stamp map also stored in the memory.
9. The as claimed in claim 1, wherein the memory controller sends timestamps followed by addresses of pixels that detected a change to the memory.
10. A method of operation of an event-based vision sensor system, comprising: detecting light with an event-based pixel array; reading out events associated with light received by each pixel and with the position it occupies in the array with a readout circuit; and a memory controller writing of each event, or event-related data, associated with each pixel to different mapped address in a memory,
11. A method as claimed in claim 10, further comprising the memory controller ensuring that the position of that address in the memory in which that event or event-related data is written, is a function of the position in the pixel array occupied by the pixel that generated that event.
12. A method as claimed in claim 10, wherein the memory can be written by the memory controller and independently read from outside.
13. A method as claimed in claim 10, which is implemented as three-dimensional integrated circuit.
14. A method as claimed in claim 10, further comprising the memory controller mapping between pixels of the event-based pixel array and addresses in the memory on a one-to-one basis.
15. A method as claimed in claim 10, further comprising the memory controller assigning each pixel a dedicated memory address of the memory and wherein the memory address or range of addresses dedicated to a certain pixel is a function of a location of that certain pixel in the array.
16. A method as claimed in claim 10, further comprising the memory controller storing timestamps in the memory.
17. A method as claimed in claim 10, further comprising the memory controller maintaining a buffer index in the memory for last time stamp map also stored in the memory.
18. A method as claimed in claim 10, further comprising the memory controller sending timestamps followed by addresses of pixels that detected a change to the memory.
19. An event-based vision sensor system, comprising: an event-based pixel array comprising pixels that detect light; a readout circuit for reading out events associated with light received by each pixel and with the position it occupies in the array; and a memory controller that enables writing of each event, or event-related data, associated with a certain pixel to a certain address in a memory, wherein the memory controller assigns each pixel a dedicated address of the memory.
1. An event-based vision sensor system, comprising: an event-based pixel array comprising pixels that detect light; a readout circuit for reading out events associated with light received by each pixel and with the position it occupies in the array; and a memory controller that enables writing of each event, or event-related data, associated with a certain pixel to a certain address in a memory, the events relating to whether On events or Off events occurred in each pixel; wherein the memory controller is on the same chip as the event-based pixel array and adds the addresses to an index buffer and a processing unit reads the index buffer and updates a read pointer in the index buffer to a last memory address that has been read.
2. The system as claimed in claim 1, wherein the memory controller that ensures that the address in the memory in which that event or event-related data is written is a function of the position in the pixel array occupied by the pixel that generated that event.
3. The system as claimed in claim 1, wherein the memory can be written by the memory controller and independently read from outside.
4. The system as claimed in claim 1, which is implemented as three-dimensional integrated circuit.
5. The system as claimed in claim 1, wherein the memory controller implements a one-to-one mapping between pixels of the event-based pixel array and addresses in the memory.
2. The system as claimed in claim 1, wherein the memory controller that ensures that the address in the memory in which that event or event-related data is written is a function of the position in the pixel array occupied by the pixel that generated that event.
7. The system as claimed in claim 1, wherein the memory controller stores timestamps in the memory.
8. The system as claimed in claim 1, wherein the memory controller maintains a buffer index in the memory for last time stamp map also stored in the memory.
9. The system as claimed in claim 1, wherein the memory controller sends timestamps followed by addresses of pixels that detected a change to the memory.
14. A method of operation of an event-based vision sensor system, comprising: detecting light with an event-based pixel array; reading out events associated with light received by each pixel and with the position it occupies in the array with a readout circuit; and a memory controller writing of each event, or event-related data, associated with each pixel to different address in a memory; wherein the memory controller is on the same chip as the event-based pixel array and adds the addresses to an index buffer and a processing unit reads the index buffer and updates a read pointer in the index buffer to a last memory address that has been read.
15. The method as claimed in claim 10, further comprising the memory controller ensuring that the position of that address in the memory in which that event or event-related data is written, is a function of the position in the pixel array occupied by the pixel that generated that event.
16. The method as claimed in claim 10, wherein the memory can be written by the memory controller and independently read from outside.
17. The method as claimed in claim 10, which is implemented as three-dimensional integrated circuit.
18. The method as claimed in claim 14, further comprising the memory controller mapping between pixels of the event-based pixel array and addresses in the memory on a one-to-one basis.
15. The method as claimed in claim 10, further comprising the memory controller ensuring that the position of that address in the memory in which that event or event-related data is written, is a function of the position in the pixel array occupied by the pixel that generated that event.
20. The method as claimed in claim 14, further comprising the memory controller storing timestamps in the memory.
21. The method as claimed in claim 14, further comprising the memory controller maintaining a buffer index in the memory for last time stamp map also stored in the memory.
22. The method as claimed in claim 14, further comprising the memory controller sending timestamps followed by addresses of pixels that detected a change to the memory.
23. An event-based vision sensor system, comprising: an event-based pixel array comprising pixels that detect light; a readout circuit for reading out events associated with light received by each pixel and with the position it occupies in the array; and a memory controller that enables writing of each event, or event-related data, associated with a certain pixel to a certain address in a memory with a one-to-one mapping between pixels of the event-based pixel array and addresses in the memory; wherein the memory controller is on the same chip as the event-based pixel array and the memory can be written by the memory controller and independently read from outside, and the memory controller adds the addresses to an index buffer and a processing unit reads the index buffer and updates a read pointer in the index buffer to a last memory address that has been read.
20. the event-based vision sensor system as claimed in claim 1, wherein the memory controller maintains a timestamp map of the most recent events generated by each pixel, the map being accessible by an external processing unit to perform temporal analysis.
21. The system as claimed in claim 1, wherein the memory controller includes a buffer index that tracks and stores memory locations where pixel events have been updated, allowing an external processing unit to access recently updated memory addresses.
22. A method of operating an event-based vision sensor system, comprising the steps of detecting pixel-level changes in an event-based pixel array, writing event data directly to a mapped memory address by a memory controller,
and maintaining a one-to-one correspondence between pixel location and memory address, such that an external processing unit is relieved from address calculation and memory management.
8. The system as claimed in claim 1, wherein the memory controller maintains a buffer index in the memory for last time stamp map also stored in the memory.
1…wherein the memory controller is on the same chip as the event-based pixel array and adds the addresses to an index buffer and a processing unit reads the index buffer and updates a read pointer in the index buffer to a last memory address that has been read…
1…wherein the memory controller is on the same chip as the event-based pixel array and adds the addresses to an index buffer and a processing unit reads the index buffer and updates a read pointer in the index buffer to a last memory address that has been read.
14. A method of operation of an event-based vision sensor system, comprising: detecting light with an event-based pixel array; reading out events associated with light received by each pixel and with the position it occupies in the array with a readout circuit; and a memory controller writing of each event, or event-related data, associated with each pixel to different address in a memory; wherein the memory controller is on the same chip as the event-based pixel array and adds the addresses to an index buffer and a processing unit reads the index buffer and updates a read pointer in the index buffer to a last memory address that has been read.
21. The method as claimed in claim 14, further comprising the memory controller maintaining a buffer index in the memory for last time stamp map also stored in the memory.
Regarding Claims 1-4, 5, 6-8, 10-13, 14, 15-17 and 19, are rejected also on the ground of nonstatutory obviousness-type double patenting as being unpatentable respectively over claims 1-4, 1, 5-7, 8-11, 8, 12-14 and 15 of U.S. Patent No. 11,936,995 B2 (See Tab. below). Although the conflicting claims are not identical, they are not patentably distinct from each other because claims 1-4, 5, 6-8, 10-13, 14, 15-17 and 19 of the instant application are obviousness by respectively over claims 1-4, 1, 5-7, 8-11, 8, 12-14 and 15 of U.S. Patent 11,936,995 B2, in that claims 1-4, 1, 5-7, 8-11, 8, 12-14 and 15 of the U.S. Patent contain all the limitations of claims 1-4, 5, 6-8, 10-13, 14, 15-17 and 19 of the instant application. 1-4, 5, 6-8, 10-13, 14, 15-17 and 19 of the instant application are therefore not patently distinct from the earlier U.S. Patent claim and such is unpatentable for obvious-type double patenting.
Instant Application
US 11,936,995 B2
1. An event-based vision sensor system, comprising: an event-based pixel array comprising pixels that detect light; a readout circuit for reading out events associated with light received by each pixel and with the position it occupies in the array; and a memory controller that enables writing of each event, or event-related data, associated with a certain pixel to a certain address in a memory; wherein the memory controller implements a mapping between pixels of the event-based pixel array and addresses in the memory, wherein the mapping is between a pixel address that represents the position of a pixel in the event-based pixel array and a memory address that represents a location in the memory.
2. The as claimed in claim 1, wherein the memory controller that ensures that the position of that address in the memory in which that event or event-related data is written, is a function of the position in the pixel array occupied by the pixel that generated that event.
3. The as claimed in claim 1, wherein the memory can be written by the memory controller and independently read from outside.
4. The as claimed in claim 1, which is implemented as three-dimensional integrated circuit.
5. The as claimed in claim 1, wherein the memory controller implements a one-to-one mapping between pixels of the event-based pixel array and addresses in the memory…
6. The as claimed in claim 1, wherein the memory controller assigns each pixel a dedicated address or range of addresses of the memory and wherein the memory address dedicated to a certain pixel is a function of a location of that certain pixel in the array.
7. The as claimed in claim 1, wherein the memory controller stores timestamps in the memory.
8. The as claimed in claim 1, wherein the memory controller maintains a buffer index in the memory for last time stamp map also stored in the memory.
10. A method of operation of an event-based vision sensor system, comprising: detecting light with an event-based pixel array; reading out events associated with light received by each pixel and with the position it occupies in the array with a readout circuit; and a memory controller writing of each event, or event-related data, associated with each pixel to different mapped address in a memory, including implementing a mapping between pixels of the event-based pixel array and addresses in the memory, wherein the mapping is between a pixel address that represents the position of a pixel in the event-based pixel array and a memory address that represents a location in the memory.
11. A method as claimed in claim 10, further comprising the memory controller ensuring that the position of that address in the memory in which that event or event-related data is written, is a function of the position in the pixel array occupied by the pixel that generated that event.
12. A method as claimed in claim 10, wherein the memory can be written by the memory controller and independently read from outside.
13. A method as claimed in claim 10, which is implemented as three-dimensional integrated circuit.
14. A method as claimed in claim 10, further comprising the memory controller mapping between pixels of the event-based pixel array and addresses in the memory on a one-to-one basis.
15. A method as claimed in claim 10, further comprising the memory controller assigning each pixel a dedicated memory address of the memory and wherein the memory address or range of addresses dedicated to a certain pixel is a function of a location of that certain pixel in the array.
16. A method as claimed in claim 10, further comprising the memory controller storing timestamps in the memory.
17. A method as claimed in claim 10, further comprising the memory controller maintaining a buffer index in the memory for last time stamp map also stored in the memory.
19. An event-based vision sensor system, comprising: an event-based pixel array comprising pixels that detect light; a readout circuit for reading out events associated with light received by each pixel and with the position it occupies in the array; and a memory controller that enables writing of each event, or event-related data, associated with a certain pixel to a certain address in a memory, wherein the memory controller assigns each pixel a dedicated address of the memory.
1. An event-based vision sensor system, comprising: an event-based pixel array comprising pixels that detect light; a readout circuit for reading out events associated with light received by each pixel and with the position it occupies in the array; and a memory controller that enables writing of each event, including a timestamp and an address of any pixel that detected a change, to a certain address in a memory and providing one-to-one mapping between pixels of the event-based pixel array and addresses in the memory; wherein the memory controller is on the same chip as the event-based pixel array.
2. The system as claimed in claim 1, wherein the memory controller that ensures that the position of that address in the memory in which that event or event-related data is written, is a function of the position in the pixel array occupied by the pixel that generated that event.
3. The system as claimed in claim 1, wherein the memory can be written by the memory controller and independently read from outside.
4. The system as claimed in claim 1, which is implemented as three-dimensional integrated circuit.
1. … providing one-to-one mapping between pixels of the event-based pixel array and addresses in the memory…
5. The system as claimed in claim 1, wherein the memory controller assigns each pixel a dedicated address or range of addresses of the memory and wherein the memory address dedicated to a certain pixel is a function of a location of that certain pixel in the array.
6. The system as claimed in claim 1, wherein the memory controller stores timestamps in the memory.
7. The system as claimed in claim 1, wherein the memory controller maintains a buffer index in the memory for last time stamp map also stored in the memory.
8. A method of operation of an event-based vision sensor system, comprising: detecting light with an event-based pixel array; reading out events associated with light received by each pixel and with the position it occupies in the array with a readout circuit; and a memory controller writing of each event, including a timestamp and an address of any pixel that detected a change, to different address in a memory and providing one-to-one mapping between pixels of the event-based pixel array and addresses in the memory, wherein the memory controller is on the same chip as the event-based pixel array.
9. The method as claimed in claim 8, further comprising the memory controller ensuring that the position of that address in the memory in which that event or event-related data is written, is a function of the position in the pixel array occupied by the pixel that generated that event.
10. The method as claimed in claim 8, wherein the memory can be written by the memory controller and independently read from outside.
11. The A method as claimed in claim 8, which is implemented as three-dimensional integrated circuit.
8.
…providing one-to-one mapping between pixels of the event-based pixel array and addresses in the memory…
12. The method as claimed in claim 8, further comprising the memory controller assigning each pixel a dedicated memory address of the memory and wherein the memory address or range of addresses dedicated to a certain pixel is a function of a location of that certain pixel in the array.
13. The method as claimed in claim 8, further comprising the memory controller storing timestamps in the memory.
14. The method as claimed in claim 8, further comprising the memory controller maintaining a buffer index in the memory for last time stamp map also stored in the memory.
15. An event-based vision sensor system, comprising: an event-based pixel array comprising pixels that detect light; a readout circuit for reading out events associated with light received by each pixel and with the position it occupies in the array; and a memory controller, on the same chip as the event-based pixel array, that enables writing of each event to a certain address in a memory, wherein the memory controller assigns each pixel a dedicated address of the memory and wherein the memory address or range of addresses dedicated to a certain pixel.
20. the event-based vision sensor system as claimed in claim 1, wherein the memory controller maintains a timestamp map of the most recent events generated by each pixel,
22. A method of operating an event-based vision sensor system, comprising the steps of detecting pixel-level changes in an event-based pixel array, writing event data directly to a mapped memory address by a memory controller, and maintaining a one-to-one correspondence between pixel location and memory address,
7. The system as claimed in claim 1, wherein the memory controller maintains a buffer index in the memory for last time stamp map also stored in the memory.
8. A method of operation of an event-based vision sensor system, comprising: detecting light with an event-based pixel array; reading out events associated with light received by each pixel and with the position it occupies in the array with a readout circuit; and a memory controller writing of each event, including a timestamp and an address of any pixel that detected a change, to different address in a memory and providing one-to-one mapping between pixels of the event-based pixel array and addresses in the memory, wherein the memory controller is on the same chip as the event-based pixel array.
Claims 1 and 10 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over the US 11,212,468 B2 or US 11,936,995 B2 hereinafter respectively “’468 and ’995” as applied above, in view of MAJUMDER et al. (US 20190043583 A1, hereinafter “MAJUMDER”).
Regarding claims 1 and 10 , the ’468 or ’995 teaches limitations as claimed in claims 1 and 10, except , wherein the mapping is between a pixel address that represents the position of a pixel in the event-based pixel array and a memory address that represents a location in the memory.
However, MAJUMDER discloses wherein the mapping is between a pixel address that represents the position of a pixel in the event-based pixel array and a memory address that represents a location in the memory (Figs. 2-3&5A, [0024]-[0031]&[0040]: A match may occur if the spatial coordinates of an event 200 is within a defined range of values of coordinates in an entry. a motion event 200.sub.i, including a first coordinate 202, e.g., X coordinate, and a second coordinate 204, e.g., Y coordinate and a content addressable memory (CAM) entry 300.sub.i, generated from a motion event 200.sub.i, and includes a first coordinate 302, e.g., X coordinate, and a second coordinate 304, e.g., Y coordinate).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate , wherein the mapping is between a pixel address that represents the position of a pixel in the event-based pixel array and a memory address that represents a location in the memory as taught by MAJUMDER into the ’468 or ’995. The suggestion/ motivation for doing so would be to reduce memory footprint and bandwidth requirement (MAJUMDER: [0018]).
Claims 9 and 18 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over ’468 or ’995 and MAJUMDER combination as applied above, in view of Orfaig et al. (US 2019/0075271 A1, hereinafter “Orfaig”).
Regarding claim 9, the ’995 and MAJUMDER combination teaches the system as claimed in claim 1, except wherein the memory controller sends timestamps followed by addresses of pixels that detected a change to the memory.
However, Orfaig discloses wherein the memory can be written by the memory controller and independently read from outside ([0032]: VFB 100 supplies an interface to a data bus 102 connected to an external device. the interface to data bus 102 is through read and write ports R and W while event addresses are received directly from DVS 110 via an address bus 104).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate wherein the memory can be written by the memory controller and independently read from outside as taught by Orfaig into the ’995 and MAJUMDER combination. The suggestion/ motivation for doing so would be to allow parallelize and simplify access to an event local environment (patch) during processing. (Orfaig: [0005]).
Regarding claim 18, Method claim 18 id drawn to the method of using the corresponding apparatus claimed in claim 9. Therefore, method claim 18 correspond to apparatus claim 9 and are rejected for the same reasons of obviousness as used above.
Claims 20 and 22 are rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable the US 11,936,995 B2 hereinafter “’995” as applied above, in view of Park et al. (US 20180262705 A1, hereinafter “Park”).
Regarding claim 20, the ’995 and MAJUMDER combination teaches an event-based vision sensor system as claimed in claim 1, in addition ’995 discloses wherein the memory controller maintains a timestamp map of the most recent events generated by each pixel (claim 7. The system as claimed in claim 1, wherein the memory controller maintains a buffer index in the memory for last time stamp map also stored in the memory.), except the map being accessible by an external processing unit to perform temporal analysis.
However, Park discloses wherein the memory controller maintains a timestamp map of the most recent events generated by each pixel ([0119]:The on-event map may include coordinates of pixels where an on-event where an increase in the intensity of light occurs and information about a time when the event occurs. In the on-event and off-event maps, for example, two subscripts (e.g., “i” and “j”) of each element indicate coordinates of each pixel of the pixel array 111, and a variable (e.g., “T”) of each element indicates a time when an on-event occurs. Examiner notes that the maps are maintained at least temporally in the memory 130), the map being accessible by an external processing unit to perform temporal analysis (Figs. 1&21, [0114]: since the event maps are saved in the memory 130/1300 of RAM type, therefore it can be accessed through a communication block such as presented in Fig. 21).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the map being accessible by an external processing unit to perform temporal analysis as taught by Park into the ’995 and MAJUMDER combination. The suggestion/ motivation for doing so would be to allow data information to be shared and transferred for further processing.
Regarding claim 22, claim 22 has been analyzed with regard to claim 20 and is rejected for the same reasons of obviousness as used above.
Claim 23 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable over the ’995 and MAJUMDER combination as applied above, in view of Mason; Jack (US 20150160967 A1, hereinafter “Mason”).
Regarding claim 23, the ’995 and MAJUMDER combination teaches the system as claimed in claim 1, except wherein the memory controller maintains a last-timestamp map in memory, and further maintains an index buffer comprising memory addresses corresponding to updated locations in the map, such that an external processing unit reads from the index buffer to identify memory addresses updated since a last read and thereby accesses only portions of the map that have changed.
However, Mason discloses wherein the memory controller maintains a last-timestamp map in memory, and further maintains an index buffer comprising memory addresses corresponding to updated locations in the map, such that an external processing unit reads from the index buffer to identify memory addresses updated since a last read and thereby accesses only portions of the map that have changed (as illustrated by Fig. 4B, [0034]: a speculative write buffer 405c in which each entry in the buffer also includes a first update timestamp and a last update timestamp. The first update timestamp can be set when the thread first updates the value at the associated address. Then, at each subsequent update to the value, the last update timestamp can be set.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Mason into the ’995 and MAJUMDER combination, such that the memory controller maintains a last-timestamp map in memory, and further maintains an index buffer comprising memory addresses corresponding to updated locations in the map, such that an external processing unit reads from the index buffer to identify memory addresses updated since a last read and thereby accesses only portions of the map that have changed. The suggestion/ motivation for doing so would be to efficiently perform further optimization using multiple timestamps (Mason: [0034]).
Claim 25 is rejected on the ground of nonstatutory obviousness-type double patenting as being unpatentable the ’995 and MAJUMDER combination as applied above, in view of Solhusvik et al. (US 20130068929 A1, hereinafter “Solhusvik”).
Regarding claim 25, ’995 and MAJUMDER combination teaches the system as claimed in claim 4, except wherein the three-dimensional integrated circuit comprises a top wafer including back-side illuminated photo- diodes, a middle wafer including circuitry to bias and operate the photo-diodes, a read-out circuit, and the memory controller, and a bottom wafer including a memory integrated circuit
in addition Solhusvik discloses wherein the three-dimensional integrated circuit comprises a top wafer including back-side illuminated photo- diodes (as illustrated by Fig. 4, [0034]: Image pixel array 17 can be a front-side illuminated (FSI) image pixel array or a backside illuminated (BSI) image pixel array in which image light 21 is received by photosensitive elements), a middle wafer including circuitry to bias and operate the photo-diodes, a read-out circuit, and the memory controller (as illustrated by Fig. 4, [0035]-[0039]: Control circuitry 44), and a bottom wafer including a memory integrated circuit (as illustrated by Fig. 4, [0038]-[0041]: storage and processing circuitry 50 stacked with control circuitry 44).
However, Solhusvik discloses which is implemented as three-dimensional integrated circuit (as illustrated by Fig. 4, [0017]: stacked-chip image sensor having a vertical chip stack that includes an image pixel array, control circuitry, and digital processing circuitry.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate which is implemented as three-dimensional integrated circuit as taught by Solhusvik into the ’995 and MAJUMDER combination The suggestion/ motivation for doing so would be to decrease the lateral footprint of the image sensor and provide improved imaging systems with enhanced pixel communication efficiency (Solhusvik: [0061]).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 5-12, 14-18, 20 and 24 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by MAJUMDER et al. (US 20190043583 A1, hereinafter “MAJUMDER”).
Regarding claim 1, MAJUMDER teaches an event-based vision sensor system (Figs. 1-3, [0021]: a system 100 having a vision processing unit 102), comprising:
an event-based pixel array comprising pixels that detect light (Figs. 1-3, [0021]: a video capture 104 unit (“pixel array”) that detects an image from a camera lens.);
a readout circuit for reading out events associated with light received by each pixel and with the position it occupies in the array (Figs. 1-3, [0021]: the vision processing unit 102 includes an event generator 106 to process the image signals and generate motion events 200.);
and a memory controller that enables writing of each event, or event-related data, associated with a certain pixel to a certain address in a memory (Figs. 1-3, [0021]: The motion events 200 are stored in a content addressable memory, such as a computational content addressable memory (c-CAM) 112, having control logic 114 to process the motion events 200 and store event information in entries 300.sub.i of a memory array 300 of memory cells. Each entry 300.sub.i in the memory array stores pixel information, such as an intensity value for a cluster of pixels in an image frame.);
wherein the memory controller (114) implements a mapping between pixels of the event-based pixel array and addresses in the memory (Figs. 1-3, [0024]-[0031]: The control logic 114 clusters events 200 having matching spatial coordinates within a predefined range in the entries 300i of the memory array 300.), wherein the mapping is between a pixel address that represents the position of a pixel in the event-based pixel array and a memory address that represents a location in the memory (Figs. 2-3&5A, [0024]-[0031]&[0040]: A match may occur if the spatial coordinates of an event 200 is within a defined range of values of coordinates in an entry. a motion event 200.sub.i, including a first coordinate 202, e.g., X coordinate, and a second coordinate 204, e.g., Y coordinate and a content addressable memory (CAM) entry 300.sub.i, generated from a motion event 200.sub.i, and includes a first coordinate 302, e.g., X coordinate, and a second coordinate 304, e.g., Y coordinate).
Regarding claim 2, MAJUMDER teaches the system as claimed in claim 1, in addition MAJUMDER discloses wherein the memory controller that ensures that the position of that address in the memory in which that event or event-related data is, is a function of the position in the pixel array occupied by the pixel that generated that event (as illustrated by Figs. 2-4, [0033]: the control logic 114 to determine an entry 300i in the memory array 300 in which to cluster the content from a received motion event 200.sub.i. Upon receiving (at block 400) an event 200.sub.i including coordinates 202, 204, an image value 206, and timestamp 208, the control logic 114 determines (at block 402) whether there is a valid entry 300i, i.e., having a valid bit 310 indicating valid, in the content addressable memory 300 having first 302 and second 304 coordinates within a defined range of values of the first 202 and second 204 coordinates of the event 200.sub.i, i.e., the coordinates 202, 204 of the event 200.sub.i are bound or anchored within the range of coordinates 302, 304 in the entry 300i. If the event coordinates 202, 204 are within the predefined range of the entry coordinates 302, 304 of a valid entry 300i, then the received first 202 and 204 second coordinates, image value 206 (polarity change value) for the coordinates, and timestamp 208 in the event 200.sub.i, are written to, or clustered with, the located valid entry 300.sub.i. The first (CX) and second (CY) coordinate spreads for the first and second coordinates 302, 304, respectively, are read (at block 406) from the cluster tags 312 for the valid entry 300.sub.i.).
Regarding claim 3, MAJUMDER teaches the system as claimed in claim 1, in addition MAJUMDER discloses wherein the memory can be written by the memory controller and independently read from outside (as illustrated by Fig. 1, [0027]-[0028]: the system 100 and content addressable memory 112 may be used for processing other than video related processing, and may not include image processing related components, such as a video capture 104, event generator 106, convolution neural network 108, etc. Other applications may utilize associative memory needed in brain-inspired hyper-dimensional computing. The system 100 may also communicate with Input/Output (I/O) devices, which may comprise input devices (e.g., keyboard, touchscreen, mouse, etc.), display devices, graphics cards, ports, network interfaces, etc., and similar memory augmented neural networks).
Regarding claim 5, MAJUMDER teaches the system as claimed in claim 1, in addition MAJUMDER discloses wherein the memory controller implements a one-to-one mapping between pixels of the event-based pixel array and addresses in the memory (Figs. 2-3&5A, [0024]-[0031]&[0040]: A match occurs if the spatial coordinates of an event 200 is within a defined range of values of coordinates in an entry. a motion event 200.sub.i, including a first coordinate 202, e.g., X coordinate, and a second coordinate 204, e.g., Y coordinate and a content addressable memory (CAM) entry 300i, generated from a motion event 200.sub.i, and includes a first coordinate 302, e.g., X coordinate, and a second coordinate 304, e.g., Y coordinate).
Regarding claim 6, MAJUMDER teaches the system as claimed in claim 1, in addition MAJUMDER discloses wherein the memory controller assigns each pixel a dedicated address or range of addresses of the memory and wherein the memory address dedicated to a certain pixel is a function of a location of that certain pixel in the array (Figs. 1-3&5A, [0024]-[0031]&[0040]: The control logic 114 clusters events 200 having matching spatial coordinates within a predefined range in the entries 300i of the memory array 300. A match may occur if the spatial coordinates of an event 200 is within a defined range of values of coordinates in an entry. a motion event 200i, including a first coordinate 202, e.g., X coordinate, and a second coordinate 204, e.g., Y coordinate and a content addressable memory (CAM) entry 300.sub.i, generated from a motion event 200i, and includes a first coordinate 302, e.g., X coordinate, and a second coordinate 304, e.g., Y coordinate).
Regarding claim 7, MAJUMDER teaches the system as claimed in claim 1, in addition MAJUMDER discloses wherein the memory controller stores timestamps in the memory (Figs. 1-3, [0024]-[0031]&[0033]: at a pixel defined by the first 202 and second 204 coordinates at a time indicated by the timestamp 208. a content addressable memory (CAM) entry 300.sub.i, generated from a motion event 200.sub.i, and includes a first coordinate 302, e.g., X coordinate, and a second coordinate 304, e.g., Y coordinate; event metadata 306, such as a polarity change, intensity change, etc., at a pixel defined by the first 302 and second 304 coordinates at a time indicated by the timestamp 308).
Regarding claim 8, MAJUMDER teaches the system as claimed in claim 1, in addition MAJUMDER discloses wherein the memory controller maintains a buffer index in the memory for last time stamp map also stored in the memory (Figs. 1-3, [0024]-[0031]&[0033]: a new event for pixel 5023 is received for time t2 that is within the predefined range of one on the Y coordinate from the entry 5021 and is then merged with entry 3001, which also updates the timestamp 308 (Examiner notes timestamp 308 showing old received time t0 and new event received time t2)).
Regarding claim 9, MAJUMDER teaches the system as claimed in claim 1, in addition MAJUMDER discloses wherein the memory controller sends timestamps followed by addresses of pixels that detected a change to the memory (as illustrated by Figs. 3-5, [0033]-[0034]: If the event coordinates 202, 204 are within the predefined range of the entry coordinates 302, 304 of a valid entry 300.sub.i, then the received first 202 and 204 second coordinates, image value 206 (polarity change value) for the coordinates, and timestamp 208 in the event 200.sub.i, are written to, or clustered with, the located valid entry 300.sub.i. to fields 302, 304, 306, 308, respectively).
Regarding claims 10-12, 15-17 and 18, Method claims 10-12, 15-17 and 18 are drawn to the method of using the corresponding apparatus claimed in claims 1-3, 6-8 and 9. Therefore, method claims 10-12, 15-17 and 18 correspond to apparatus claims 1-3, 6-8 and 9 and are rejected for the same reasons of anticipation as used above.
Regarding claim 14, MAJUMDER teaches the method as claimed in claim 10, in addition MAJUMDER discloses further comprising the memory controller mapping between pixels of the event-based pixel array and addresses in the memory on a one-to-one basis (as illustrated by Figs. 3-5, [0033]-[0034]&[0040]: The control logic 114 clusters events 200 having matching spatial coordinates within a predefined range in the entries 300i of the memory array 300. A match may occur if the spatial coordinates of an event 200 is within a defined range of values of coordinates in an entry.. Events, i.e., changed pixel values that occur within an image frame 500 at X and Y coordinates, are stored in entries 300i of the content addressable memory (CAM) 300).
Regarding claim 20, MAJUMDER teaches the event-based vision sensor system as claimed in claim 1, in addition MAJUMDER discloses wherein the memory controller maintains a timestamp map of the most recent events generated by each pixel (as illustrated by Figs. 5, [0040]-[0044]: memory 112 storing event signals at different timing t0, t1, t2 and tn. Examiner notes that the maps are maintained at least temporally in the in entries 300.sub.i of a memory array 300 of memory cells), the map being accessible by an external processing unit to perform temporal analysis (as illustrated by Fig. 1, [0027]-[0028]: the system 100 and content addressable memory 112 may be used for processing other than video related processing, and may not include image processing related components, such as a video capture 104, event generator 106, convolution neural network 108, etc. Other applications may utilize associative memory needed in brain-inspired hyper-dimensional computing. The system 100 may also communicate with Input/Output (I/O) devices, which may comprise input devices (e.g., keyboard, touchscreen, mouse, etc.), display devices, graphics cards, ports, network interfaces, etc., and similar memory augmented neural networks).
Regarding claim 24, MAJUMDER teaches the system as claimed in claim 1, in addition MAJUMDER discloses wherein the memory controller implements a mapping in which multiple pixels of the pixel array are mapped to a common memory address or a set of addresses, such that events from a certain area of the array are stored in shared memory locations (Figs. 1-3&5, [0021]-[0031]&[0033]: The control logic 114 clusters events 200 having matching spatial coordinates within a predefined range in the entries 300i of the memory array 300. In one example, an 8×8 frame size may have a cluster size of 2×2, such that each entry 300.sub.i, in the memory array 300 stores information for motion events 200 generated for a cluster of pixels associated with the entry 300.sub.i.).
Claims 19 and 22 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Park et al. (US 20170127005 A1, hereinafter “Park”).
Regarding claim 19, Park teaches an event-based vision sensor system (Figs. 1-2&7), comprising:
an event-based pixel array comprising pixels that detect light (Figs. 1-2&7, [0043]: vision sensor 140 includes a plurality of sensing elements. A single sensing element senses an occurrence of a predetermined event and output an event signal);
a readout circuit for reading out events associated with light received by each pixel and with the position it occupies in the array (as illustrated by Figs. 1-2&7, [0045]-[0048]: The vision sensor 140 utilizes address information or address/time information of a sensing element sensing a light change event. this example, the vision sensor 140 outputs a time at which the event signal is generated as a relative number. The vision sensor 140 outputs an event signal);
and a memory controller that enables writing of each event, or event-related data, associated with a certain pixel to a certain address in a memory (as illustrated by Figs. 1-2&7, [0049]-[0053]: a storing apparatus 100 includes a processor 120 that stores the event signal in a memory area indicated by the determined event address information. The memory 130 stores the event signal received from the vision sensor 140. The memory 130 stores the event signal in the memory area indicated by the event address information corresponding to the time information.), wherein the memory controller assigns each pixel a dedicated address of the memory (as illustrated by Figs. 1-2&7, [0058]-[0062]: The image address information is uniquely mapped to a range information, and indicate a memory area in which the image including the event signals belonging to the range information is to be stored. The storing apparatus determines event address information corresponding to the time information T=106 using a hash function 220. The hash function 220 refers to a function to output event address information corresponding to input time information. For example, a look-up table in which time information and event address information are mapped to each other is used. The time information and the event address information is uniquely mapped to each other.).
Regarding claim 22, Park teaches a method of operating an event-based vision sensor system, comprising the steps of detecting pixel-level changes in an event-based pixel array (as illustrated by Figs. 1-3&7, [0045]&[0095]: vision sensor 140 to detect a light change which is stored in a memory 130),
writing event data directly to a mapped memory address by a memory controller,
and maintaining a one-to-one correspondence between pixel location and memory address (as illustrated by Figs. 1-2&7, [0058]-[0062]: The image address information is uniquely mapped to a range information, and indicate a memory area in which the image including the event signals belonging to the range information is to be stored. The storing apparatus determines event address information corresponding to the time information T=106 using a hash function 220. The hash function 220 refers to a function to output event address information corresponding to input time information. For example, a look-up table in which time information and event address information are mapped to each other may be used. The time information and the event address information is uniquely mapped to each other.), such that an external processing unit is relieved from address calculation and memory management (as illustrated by Figs. 1-2, [0055]: communicator 110 receives range information related to event signals to be accessed from a user or from an external device of the storing apparatus 100).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4, 13 and 25 are rejected under 35 U.S.C. 103 as being unpatentable over MAJUMDER et al. (US 20190043583 A1, hereinafter “MAJUMDER”), in view of Solhusvik et al. (US 20130068929 A1, hereinafter “Solhusvik”).
Regarding claim 4, MAJUMDER teaches the system as claimed in claim 1, except which is implemented as three-dimensional integrated circuit.
However, Solhusvik discloses which is implemented as three-dimensional integrated circuit (as illustrated by Fig. 4, [0017]: stacked-chip image sensor having a vertical chip stack that includes an image pixel array, control circuitry, and digital processing circuitry.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate which is implemented as three-dimensional integrated circuit as taught by Solhusvik into the MAJUMDER image sensor. The suggestion/ motivation for doing so would be to decrease the lateral footprint of the image sensor and provide improved imaging systems with enhanced pixel communication efficiency (Solhusvik: [0061]).
Regarding claim 13, claim 13 has been analyzed with regard to claim 4 and is rejected for the same reasons of obviousness as applied above to claim 4.
Regarding claim 25, MAJUMDER and Solhusvik combination teaches the system as claimed in claim 4, in addition Solhusvik discloses wherein the three-dimensional integrated circuit comprises a top wafer including back-side illuminated photo- diodes (as illustrated by Fig. 4, [0034]: Image pixel array 17 can be a front-side illuminated (FSI) image pixel array or a backside illuminated (BSI) image pixel array in which image light 21 is received by photosensitive elements), a middle wafer including circuitry to bias and operate the photo-diodes, a read-out circuit, and the memory controller (as illustrated by Fig. 4, [0035]-[0039]: Control circuitry 44), and a bottom wafer including a memory integrated circuit (as illustrated by Fig. 4, [0038]-[0041]: storage and processing circuitry 50 stacked with control circuitry 44). The suggestion/ motivation for doing so would be to decrease the lateral footprint of the image sensor and provide improved imaging systems with enhanced pixel communication efficiency (Solhusvik: [0061]).
Claims 21 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over MAJUMDER et al. (US 20190043583 A1, hereinafter “MAJUMDER”), in view of Mason; Jack (US 20150160967 A1, hereinafter “Mason”).
Regarding claim 21, MAJUMDER teaches the system as claimed in claim 1, except wherein the memory controller includes a buffer index that tracks and stores memory locations where pixel events have been updated.
However, Mason discloses wherein the memory controller includes a buffer index that tracks and stores memory locations where pixel events have been updated (as illustrated by Fig. 4B, [0034]: a speculative write buffer 405c in which each entry in the buffer also includes a first update timestamp and a last update timestamp. The first update timestamp can be set when the thread first updates the value at the associated address. Then, at each subsequent update to the value, the last update timestamp can be set.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Mason into the MAJUMDER image sensor such that wherein the memory controller includes a buffer index that tracks and stores memory locations where pixel events have been updated. The suggestion/ motivation for doing so would be to efficiently perform further optimization using multiple timestamps (Mason: [0034]).
Regarding claim 23, MAJUMDER teaches the system as claimed in claim 1, except wherein the memory controller maintains a last-timestamp map in memory, and further maintains an index buffer comprising memory addresses corresponding to updated locations in the map, such that an external processing unit reads from the index buffer to identify memory addresses updated since a last read and thereby accesses only portions of the map that have changed.
However, Mason discloses wherein the memory controller maintains a last-timestamp map in memory, and further maintains an index buffer comprising memory addresses corresponding to updated locations in the map, such that an external processing unit reads from the index buffer to identify memory addresses updated since a last read and thereby accesses only portions of the map that have changed (as illustrated by Fig. 4B, [0034]: a speculative write buffer 405c in which each entry in the buffer also includes a first update timestamp and a last update timestamp. The first update timestamp can be set when the thread first updates the value at the associated address. Then, at each subsequent update to the value, the last update timestamp can be set.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Mason into the MAJUMDER image sensor such that the memory controller maintains a last-timestamp map in memory, and further maintains an index buffer comprising memory addresses corresponding to updated locations in the map, such that an external processing unit reads from the index buffer to identify memory addresses updated since a last read and thereby accesses only portions of the map that have changed. The suggestion/ motivation for doing so would be to efficiently perform further optimization using multiple timestamps (Mason: [0034]).
Claim 26 is rejected under 35 U.S.C. 103 as being unpatentable over MAJUMDER et al. (US 20190043583 A1, hereinafter “MAJUMDER”), in view of Doege; Jens (US 20190342513 A1, hereinafter “Doege”).
Regarding claim 26, MAJUMDER teaches the system as claimed in claim 1, in addition MAJUMDER discloses wherein the readout circuit outputs a stream of event data packages including a timestamp followed by the addresses of all pixels that generated events between two consecutive timestamps (as illustrated by Figs. 1-3&5, [0038]: The content addressable memory 112 provides fast access to the clustered motion events to the convolution neural network 108 to use for image analysis).
MAJUMDER does not teach the memory controller writes the timestamp and each address sequentially to successive memory locations in a ring buffer.
However, Doege discloses the memory controller writes the timestamp and each address sequentially to successive memory locations in a ring buffer ([0033]: readout arrangement may store or cause to store successive analog values represented by the image sensor analog signals or based on the image sensor analog signals successively into an analog memory region (e.g., assigned to a respective column of the image sensor) driven or configured as a ring buffer.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of Doege into the MAJUMDER image sensor. such that the memory controller writes the timestamp and each address sequentially to successive memory locations in a ring buffer. The suggestion/ motivation for doing so would be to efficiently manage the high-speed, asynchronous data streams in an event-based sensor.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Contact
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ABDELAAZIZ TISSIRE whose telephone number is (571)270-7204. The examiner can normally be reached on Monday through Friday from 8 AM to 5 PM.
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/ABDELAAZIZ TISSIRE/ Primary Examiner, Art Unit 2638
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