DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This office action is in respond to the amendment filed on 12/16/25.
Claim Objections
Claims 2 and 21 are objected to because of the following informalities:
Claim 2, line 2, the recitation “wherein pair” should be changed to “wherein the pair” (see claim 1, line 6).
Claim 21, line 3, the recitation “the control signal” should be changed to “the isolation control signal” (see line 1).
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-6, 8-10, 12, 16, 17 and 21 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Wang et al. (US 2010/0026366).
For claim 1, Figure 3 of Wang et al. teaches a method for level-shifting a received signal (IN) from a first voltage domain (VCCL) to a second voltage domain (VCCH), the method comprising: controlling a cross-coupled pair of transistors (112, 116) according to an input signal (IN) and a complementary input signal (/IN which is output of inverter 130) to generate a signal on a pair of complementary nodes (OUT, junction connection node of 112 and 212), the cross-coupled pair of transistors (112, 116) having a first doping type (p-type) and the controlling using a pair of transistors (332, 336) having a second doping type (n-type), the second doping type (n-type) being complementary to the first doping type (p-type); and isolating the pair of transistors (332, 336) from the pair of complementary nodes (OUT, junction connection node of 112 and 212) using a pair of isolation transistors (212, 222) and a pair of cascode transistors (312, 322), the pair of isolation transistors (212, 222) and the pair of cascode transistors (312, 322) being coupled between the pair of transistors (332, 336) and the pair of complementary nodes (OUT, junction connection node of 112 and 212); wherein the pair of isolation transistors (212, 222) is selectively disabled by an isolation control signal (POCHB).
For claim 2, Figure 3 of Wang et al. teaches wherein the pair of transistors (332, 336) comprise low-voltage transistors, and wherein the cross-coupled pair of transistors (112, 116), the pair of isolation transistors (212, 222), and the pair of cascode transistors (312, 322) comprise high-voltage transistors (also see [0022]).
For claim 3, Figure 3 of Wang et al. teaches wherein the pair of transistors (332, 336) are in the first voltage domain (VCCL), and wherein the cross-coupled pair of transistors (112, 116), the pair of cascode transistors (312, 322), and the pair of isolation transistors (212, 222) are in the second voltage domain (VCCH).
For claim 4, Figure 3 of Wang et al. teaches wherein the first voltage domain (VCCL) has an input power supply voltage level (VCCL) above an input ground (VSS) and the second voltage domain (VDDH) has an output power supply voltage level (VDDH) above an output ground (VSS), the output power supply voltage level (VDDH) being greater than the input power supply voltage level (VCCL), (see [0004]).
For claim 5, Figure 3 of Wang et al. teaches wherein the pair of isolation transistors (212, 222) reduce stress on the pair of cascode transistors (312, 322).
For claim 6, Figure 3 of Wang et al. teaches receiving the input signal (IN) in the first voltage domain (VCCL); and generating the complementary input signal (output of inverter 130) based on the input signal (IN) in the first voltage domain (VCCL), wherein the input signal (IN) and the complementary input signal (output of 130) have a first voltage swing (VSS-VCCL) between an input power supply voltage level (VCCL) and an input ground (VSS).
For claim 8, Figure 3 of Wang et al. teaches wherein the pair of isolation transistors (212, 222) is configured as a second pair of cascode transistors (212, 222) with respect to the pair of cascode transistors (312, 322), thereby reducing stress on the pair of cascode transistors (312, 322).
For claim 9, Figure 3 of Wang et al. teaches a level shifter comprising: a cross-coupled pair of transistors (112, 116) coupled between a first power supply node (VCCH) and a first pair of nodes (OUT, junction connection node of 112 and 212), the cross-coupled pair of transistors (112, 116) having a first doping type (p-type); a pair of isolation transistors (212, 222) coupled between the first pair of nodes (OUT, junction connection node of 112 and 212) and a second pair of nodes (junction connection node of 312 and 212, junction connection node of 322 and 222), the pair of isolation transistors (212, 222) having a second doping type (n-type), the second doping type (n-type) being complementary to the first doping type (p-type), wherein the pair of isolation transistors (212, 222) is selectively disabled by an isolation control signal (POCHB); a pair of cascode transistors (312, 322) coupled between the second pair of nodes (junction connection node of 312 and 212, junction connection node of 322 and 222) and a third pair of nodes (junction connection node of 312 and 332, junction connection node of 322 and 336),
the pair of cascode transistors (312, 322) having the second doping type (n-type); and a pair of transistors (332, 336) coupled between the third pair of nodes (junction connection node of 312 and 332, junction connection node of 322 and 336) and a second power supply node (VSS), the pair of transistors (332, 336) having the second doping type (n-type), the pair of transistors (332, 336) being configured to receive an input signal (IN) and a complementary input signal (output of 130).
For claim 10, Figure 3 of Wang et al. teaches an input circuit (inverter 130) coupled between the second power supply node (VSS) and a third power supply node (VCCL) and configured to generate the complementary input signal (output of 130) based on the input signal (IN).
For claim 12, Figure 3 of Wang et al. teaches wherein the first power supply node (VCCH) is configured to receive an output power supply voltage level (VCCH) above an output ground (VSS) and the third power supply node (VCCL) is configured to receive an input power supply voltage level (VCCL) above an input ground (VSS), the output power supply voltage level (VCCH) being greater than the input power supply voltage level (VCCL), the second power supply node (VSS) being coupled to input ground (ground VSS).
For claim 16, Figure 3 of Wang et al. teaches wherein the pair of isolation transistors (212, 222) is configured as a second pair of cascode transistors (212, 222) with respect to the pair of cascode transistors (312, 322), thereby reducing stress on the pair of cascode transistors (312, 322).
For claim 17, Figure 3 of Wang et al. teaches a level shifter comprising: a first circuit (332, 336) comprising low-voltage transistors (332, 336), the first circuit (332, 336) being coupled between a pair of complementary nodes (junction connection node of 312 and 332, junction connection node of 322 and 336) and a first ground (VSS), and the first circuit (332, 336) being responsive to an input signal (IN) and a complementary input signal (output of 130) generated in a first voltage domain (VCCL); and a second circuit (312, 322, 212, 222, 112, 116) comprising high-voltage transistors (312, 322, 212, 222, 112, 116), the second circuit (312, 322, 212, 222, 112, 116) being coupled between the pair of complementary nodes (junction connection node of 312 and 332, junction connection node of 322 and 336) and an output power supply node (VCCH) in a second voltage domain (VCCH); wherein the second circuit (312, 322, 212, 222, 112, 116) further comprises: a cross-coupled pair of transistors (112, 116) coupled between the output power supply node (VCCH) and a second pair of complementary nodes (OUT, junction connection node of 112 and 212), the cross-coupled pair of transistors (112, 116) having a first doping type (p-type); and a pair of isolation transistors (212, 222) coupled between the second pair of complementary nodes (OUT, junction connection node of 112 and 212) and the pair of complementary nodes (junction connection node of 312 and 332, junction connection node of 322 and 336), the pair of isolation transistors (212, 222) having a second doping type (n-type) and being selectively disabled by an isolation control signal (POCHB).
For claim 21, Figure 3 of Wang teaches wherein the isolation control signal (POCHB) is coupled to gate nodes of the pair of isolation transistors (212, 222) and the method further comprises: using the control signal (POCHB) to disable the pair of isolation transistors (212, 222); and while the pair of isolation transistors (212, 222) is disabled, forcing the second pair of complementary nodes (OUT, junction connection node of 212 and 112) to a predetermined state in response to a second control signal (POCH, by using 242).
Claims 1, 4-13 and 16-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Ogawa (USP 9,076,529).
For claim 1, Figure 16 of Ogawa teaches a method for level-shifting a received signal (DIN) from a first voltage domain (VDD) to a second voltage domain (VPP), the method comprising: controlling a cross-coupled pair of transistors (221, 211) according to an input signal (IN) and a complementary input signal (output of inverter 14) to generate a signal on a pair of complementary nodes (12a, 11a), the cross-coupled pair of transistors (221, 211) having a first doping type (p-type) and the controlling using a pair of transistors (21, 22) having a second doping type (n-type), the second doping type (n-type) being complementary to the first doping type (p-type); and isolating the pair of transistors (21, 22) from the pair of complementary nodes (12a, 11a) using a pair of isolation transistors (31, 32) and a pair of cascode transistors (41, 42), the pair of isolation transistors (31, 32) and the pair of cascode transistors (41, 42) being coupled between the pair of transistors (21, 22) and the pair of complementary nodes (12a, 11a); wherein the pair of isolation transistors (21, 22) is selectively disabled by an isolation control signal (LAT).
For claim 4, Figure 16 of Ogawa teaches wherein the first voltage domain (VDD) has an input power supply voltage level (VVDD) above an input ground and the second voltage domain (VPP) has an output power supply voltage level (VPP) above an output ground, the output power supply voltage level (VPP) being greater than the input power supply voltage level (VDD), (see Col. 9, lines 54-67).
For claim 5, Figure 16 of Ogawa teaches wherein the pair of isolation transistors (31, 32) reduce stress on the pair of cascode transistors (41, 42).
For claim 6, Figure 16 of Ogawa teaches receiving the input signal (DIN) in the first voltage domain (VDD); and generating the complementary input signal (output of inverter 14) based on the input signal (DIN) in the first voltage domain (VDD), wherein the input signal (DIN) and the complementary input signal (output of 14) have a first voltage swing (ground-VDD) between an input power supply voltage level (VDD) and an input ground (VSS).
For claim 7, Figure 16 of Ogawa teaches the method further comprising: buffering (using 214) an intermediate signal on a first node (11a) of the pair of complementary nodes (12a, 11a) in the second voltage domain (VPP) to generate an output signal (DOUT), wherein the output signal (DOUT) has a second voltage swing between an output power supply voltage level (VPP) and an output ground (ground), wherein the receiving and generating uses low-voltage transistors (21, 22), and wherein the buffering uses high-voltage transistors (transistors in inverter 214).
For claim 8, Figure 16 of Ogawa teaches wherein the pair of isolation transistors (31, 32) is configured as a second pair of cascode transistors (31, 32) with respect to the pair of cascode transistors (41, 42), thereby reducing stress on the pair of cascode transistors (41, 42).
For claim 9, Figure 16 of Ogawa teaches a level shifter comprising: a cross-coupled pair of transistors (221, 211) coupled between a first power supply node (VPP) and a first pair of nodes (12a, 11a), the cross-coupled pair of transistors (221, 211) having a first doping type (p-type); a pair of isolation transistors (31, 32) coupled between the first pair of nodes (12a, 11a) and a second pair of nodes (junction connection node of 21 and 31, junction connection node of 22 and 32), the pair of isolation transistors (21, 31) having a second doping type (n-type), the second doping type (n-type) being complementary to the first doping type (p-type), wherein the pair of isolation transistors (21, 31) is selectively disabled by an isolation control signal (LAT); a pair of cascode transistors (41, 42) coupled between the second pair of nodes (junction connection node of 21 and 31, junction connection node of 22 and 32) and a third pair of nodes (junction connection node of 221 and 223, junction connection node of 211 and 213),
the pair of cascode transistors (41, 42) having the second doping type (n-type); and a pair of transistors (21, 22) coupled between the third pair of nodes (junction connection node of 221 and 223, junction connection node of 211 and 213) and a second power supply node (ground), the pair of transistors (21, 22) having the second doping type (n-type), the pair of transistors (21, 22) being configured to receive an input signal (DIN) and a complementary input signal (output of 14).
For claim 10, Figure 16 of Ogawa teaches an input circuit (inverter 14) coupled between the second power supply node (ground) and a third power supply node (VDD) and configured to generate the complementary input signal (output of 14) based on the input signal (DIN).
For claim 11, Figure 16 of Ogawa teaches an output circuit (214) coupled between the first power supply node (VPP) and a fourth power supply node (ground) and configured to generate an output signal (DOUT) on an output node (DOUT) based on a signal on the first pair of nodes (11a, 12a).
For claim 12, Figure 16 of Ogawa teaches wherein the first power supply node (VPP) is configured to receive an output power supply voltage level (VPP) above an output ground (ground) and the third power supply node (VDD) is configured to receive an input power supply voltage level (VDD) above an input ground (ground), the output power supply voltage level (VPP) being greater than the input power supply voltage level (VDD), the second power supply node (ground) being coupled to input ground (ground ).
For claim 13, Figure 16 of Ogawa teaches wherein the input circuit (14) receives the input signal (DIN), the input signal (DIN) having a first voltage swing (ground-VDD) between an input power supply voltage level (VDD) on the third power supply node (VDD) and an input ground (ground) on the second power supply node (ground), wherein the output signal (DOUT) has a second voltage swing (ground-VPP) between an output power supply voltage level (VPP) on the first power supply node (VPP) and an output ground (ground) on the fourth power supply node (ground), and wherein the input power supply voltage level (VDD) is less than the output power supply voltage level (VPP), (see Col. 9, lines 54-67).
For claim 16, Figure 16 of Ogawa teaches wherein the pair of isolation transistors (31, 32) is configured as a second pair of cascode transistors (31, 32) with respect to the pair of cascode transistors (41, 42), thereby reducing stress on the pair of cascode transistors (41, 42).
For claim 17, Figure 16 of Ogawa teaches a level shifter comprising: a first circuit (21, 22) comprising low-voltage transistors (21, 22), the first circuit (21, 22) being coupled between a pair of complementary nodes (junction connection node of 21 and 31, junction connection node of 22 and 32) and a first ground (ground), and the first circuit (21, 22) being responsive to an input signal (DIN) and a complementary input signal (output of 14) generated in a first voltage domain (VDD); and a second circuit (31, 32, 41, 42, 223, 213, 221, 211) comprising high-voltage transistors (41, 42, 223, 213, 221, 211), the second circuit (31, 32, 41, 42, 223, 213, 221, 211) being coupled between the pair of complementary nodes (junction connection node of 21 and 31, junction connection node of 22 and 32) and an output power supply node (VPP) in a second voltage domain (VPP); wherein the second circuit (31, 32, 41, 42, 223, 213, 221, 211) further comprises: a cross-coupled pair of transistors (221, 211) coupled between the output power supply node (VPP) and a second pair of complementary nodes (12a, 11a), the cross-coupled pair of transistors (221, 211) having a first doping type (p-type); and a pair of isolation transistors (31, 32) coupled between the second pair of complementary nodes (12a, 11a) and the pair of complementary nodes (junction connection node of 21 and 31, junction connection node of 22 and 32), the pair of isolation transistors (31, 32) having a second doping type (n-type) and being selectively disabled by an isolation control signal (LAT).
For claim 18, Figure 16 of Ogawa teaches an input buffer circuit (14) comprising second low-voltage transistors (transistors in inverter 14) coupled between an input power supply node (VDD) and an input ground (ground) and configured to generate the complementary input signal (output of 14) based on the input signal (DIN) generated in the first voltage domain (VDD); and an output circuit (214) comprising second high-voltage transistors (transistors in inverter 214) coupled between the output power supply node (VPP) and an output ground (ground) and responsive to a signal on a node (11a) of the second pair of complementary nodes (12a, 11a) to generate an output signal (DOUT) in the second voltage domain (VPP).
For claim 19, Figure 16 of Ogawa teaches a pair of cascode transistors (223, 213) coupled between a third pair of complementary nodes (junction connection node of 221 and 223, junction connection node of 211 and 213) and the second pair of complementary nodes (12a, 11a), the pair of cascode transistors (223, 213) having the first doping type (p-type), wherein the first circuit (21, 22) comprises a second pair of cascode transistors (21, 22) coupled between the third pair of complementary nodes (junction connection node of 21 and 31, junction connection node of 22 and 32) and the first ground (ground), the second pair of cascode transistors (21, 31) having the second doping type (n-type).
For claim 20, Figure 16 of Ogawa teaches wherein the pair of isolation transistors (31, 32) is configured as a third pair of cascode transistors (31, 32) with respect to the second pair of cascode transistors (21, 22), thereby reducing stress on the second pair of cascode transistors (21, 22).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 7, 11, 13-15 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Wang et al. (US 2010/0026366) in view of Yu et al. (USP 7,710,182).
For claim 7, Figure 3 of Wang et al. teaches all the limitations of this claim as discussed above in the 102 rejections including wherein the receiving and generating uses low-voltage transistors (transistors 332, 336). Figure 2 of Yu et al. does not teach “buffering an intermediate signal on a first node of the pair of complementary nodes in the second voltage domain to generate an output signal, wherein the output signal has a second voltage swing between an output power supply voltage level and an output ground, and wherein the buffering uses high-voltage transistors”. However, Figure 2 of Yu et al. teaches buffering (output stage 260) an intermediate signal (V2X) on a first node (V2X) of the pair of complementary nodes (V1X, V2X) in the second voltage domain (0-V2 = VH) to generate an output signal (Vout), wherein the output signal (Vout) has a second voltage swing (0-V2 = VH) between an output power supply voltage level (VH) and an output ground (VSS), and wherein the buffering (260) uses high-voltage transistors (M11-M12). Therefore, it would have been obvious to one having ordinary skilled in the art at a time before the invention was effectively filed to modify the level shifter in Figure 3 of Wang et al. by incorporate an output stage (260), as taught in Figure 2 of Yu et al., into the level shifter for the purpose of providing a specific state of the output signal and improving the driving capability of the output signal. Thus, this combination/modification meets all the limitations of claim 7.
For claim 11, Figure 3 of Wang et al. teaches all the limitations of this claim as discussed above in the 102 rejections except for the level shifter further comprises “an output circuit coupled between the first power supply node and a fourth power supply node and configured to generate an output signal on an output node based on a signal on the first pair of nodes”. However, Figure 2 of Yu et al. teaches an output circuit (260) coupled between the first power supply node (VH) and a fourth power supply node (ground VSS) and configured to generate an output signal (Vout) on an output node (Vout) based on a signal (V2X) on the first pair of nodes (V1X, V2X). Therefore, it would have been obvious to one having ordinary skilled in the art at a time before the invention was effectively filed to modify the level shifter in Figure 3 of Wang et al. by incorporate an output circuit (260), as taught in Figure 2 of Yu et al., into the level shifter for the purpose of providing a specific state of the output signal and improving the driving capability of the output signal. Thus, this combination/modification meets all the limitations of claim 11.
For claim 13, the modification/combination as discussed in claim 11 above teaches wherein the input circuit (332, 336 in Figure 3 of Wang et al.) receives the input signal (IN), the input signal (IN) having a first voltage swing (VSS-VCCL) between an input power supply voltage level (VCCL) on the third power supply node (VCCL) and an input ground (VSS) on the second power supply node (VSS), wherein the output signal (VOUT, by incorporate the output circuit 260 in Figure 2 of Yu et al. into the level shifter) has a second voltage swing (ground-VH which is VCCH after the modification/combination) between an output power supply voltage level (VCCH) on the first power supply node (VCCH) and an output ground (VSS) on the fourth power supply node (VSS), and wherein the input power supply voltage level (VCCL) is less than the output power supply voltage level (VCCH).
For claim 14, the modification/combination as discussed in claim 11 above teaches wherein the pair of transistors (332, 336 in Figure 3 of Wang et al.) and the input circuit (130, Figure 2 of Wang et al.) comprise low-voltage transistors; and wherein the output circuit (the output circuit 260 in Figure 2 of Yu et al. that is incorporated into the level shifter), the cross-coupled pair of transistors (112, 116 in Figure 3 of Wang et al.), the pair of isolation transistors (212, 222 in Figure 3 of Wang et al.), and the pair of cascode transistors (312, 322 in Figure 3 of Wang et al.) comprise high-voltage transistors.
For claim 15, the modification/combination as discussed in claim 11 above teaches wherein the input circuit (130, Figure 2 of Wang et al.) and the pair of transistors (332, 336 in Figure 3 of Wang et al.) are in a first voltage domain (VCCL), and wherein the cross-coupled pair of transistors (112, 116 in Figure 3 of Wang et al.), the pair of isolation transistors (212, 222 in Figure 3 of Wang et al.), the pair of cascode transistors (312, 322 in Figure 3 of Wang et al.), and the output circuit (the output circuit 260 in Figure 2 of Yu et al. that is incorporated into the level shifter) are in a second voltage domain (VCCH).
For claim 18, the modification/combination as discussed in claim 11 above teaches: an input buffer circuit (inverter 130, Figure 3 of Wang et al.) comprising second low-voltage transistors (inside inverter 130) coupled between an input power supply node (VCCL) and an input ground (VSS) and configured to generate the complementary input signal (output of 130) based on the input signal (IN) generated in the first voltage domain (VSS-VCCL); and an output circuit (the output circuit 260 in Figure 2 of Yu et al. that is incorporated into the level shifter) comprising second high-voltage transistors (M11-M12) coupled between the output power supply node (VCCH after the modification ) and an output ground (VSS) and responsive to a signal on a node (OUT after the modification) of the pair of complementary nodes (OUT, junction connection node of 112 and 212 after the modification) to generate an output signal (Vout which is output of the output circuit 260) in the second voltage domain (VCCH after the modification).
Response to Arguments
Applicant’s arguments filed on 12/16/25 have been considered but are moot in view of the new ground of rejection(s).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directly to Examiner Long Nguyen whose telephone number is (571) 272-1753. The Examiner can normally be reached on Monday to Friday from 8:30am to 5:00pm.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lincoln Donovan, can be reached at (571) 272-1988. The fax number for this group is (571) 273-8300.
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/Long Nguyen/
Primary Examiner
Art Unit 2842