Prosecution Insights
Last updated: May 29, 2026
Application No. 18/442,791

CAPACITIVE SENSING SYSTEM

Non-Final OA §102§103§112
Filed
Feb 15, 2024
Examiner
BOLDUC, DAVID J
Art Unit
2852
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
1 (Non-Final)
84%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
91%
With Interview

Examiner Intelligence

Grants 84% — above average
84%
Career Allowance Rate
607 granted / 721 resolved
+16.2% vs TC avg
Moderate +7% lift
Without
With
+7.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
10 currently pending
Career history
734
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
84.8%
+44.8% vs TC avg
§102
8.8%
-31.2% vs TC avg
§112
5.0%
-35.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 721 resolved cases

Office Action

§102 §103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Objections Claim 1 is objected to because of the following informalities: The claim recites “a control circuit configured to control the first frequency of the first signal and the second frequency of the second frequency” which should read “a control circuit configured to control the first frequency of the first signal and the second frequency of the second signal”. Appropriate correction is required. Claim Rejections - 35 USC § 112 The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. Claim 7 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. The claim recites “a comparison circuit configured to provide an output signal based on between the output signal of the sampling circuit and a reference signal” which is unclear. It appears either that “between” is not meant to be included, or that additional terms are missing. Claim Rejections - 35 USC § 102/103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 1-3, 6-11, 13, 15-18 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over US 20060017449 to Takekawa. Regarding Claim 1, Takekawa discloses a device (Figs. 9-10, 14 and 29, detection circuit for relative capacitance difference acceleration sensor; ¶¶ [0010]-[0012], [0059]-[0075]), comprising: an excitation circuit having a first output terminal and a second output terminal, the first output terminal configured to provide a first signal of a first frequency to a capacitive sensor, the second output terminal configured to provide a second signal of a second frequency to the capacitive sensor (Figs. 9-10, 14 and 29, oscillator 50, 121, 122 outputs connected through buffers 51 and 52 to respective capacitors C1 and C2; ¶¶ [0059]-[0075], [0116]-[0121]); a monitoring circuit having an input terminal configured to receive a third signal from the capacitive sensor in response to the first and second signals (Figs. 9-10, 14 and 29, capacitors C1 and C2 output connected to phase comparator 53, charge pump 54, low-pass filter 55, counter 56, reference voltage generating circuit (Vref) 57, switch 58, and sample-and-hold circuit 59; ¶¶ [0059]-[0075], [0116]-[0121]); and a control circuit configured to control the first frequency of the first signal and the second frequency of the second signal to determine a value of the third signal (Figs. 9-10, 14 and 29, control circuit 94, 126 and/or PLL circuit used as frequency amplifier circuits 151 and 152 with phase comparison results to control output voltage of charge pump supplied to VCO through the low-pass filter; ¶¶ [0059]-[0075], [0116]-[0121]). Regarding Claim 2, Takekawa discloses the monitoring circuit comprises a sampling circuit having an input terminal and an output terminal, the output terminal configured to provide an output signal representing the third signal (Figs. 9-10, 14 and 29, sample-and-hold circuit 59 signal F; ¶¶ [0059]-[0075], [0116]-[0121]). Regarding Claim 3, Takekawa discloses the monitoring circuit comprises an amplification circuit having an input terminal and an output terminal, the output terminal coupled to the input terminal of the sampling circuit (Figs. 9-10, 14 and 29, control circuit 94, 126 and/or PLL circuit used as frequency amplifier circuits 151 and 152 connected to sample-and-hold circuit 59; ¶¶ [0059]-[0075], [0116]-[0121]). Regarding Claim 6, Takekawa discloses the monitoring circuit comprises a low pass filter (LPF) having a first terminal and a second terminal, the first terminal configured to receive the third signal of the capacitive sensor, the second terminal coupled to the input terminal of the amplification circuit (Figs. 9-10, 14, 29 and 32, low-pass filter 44/55/164 receiving signal DO with output E/VT to VCO/amplifier input; ¶¶ [0059]-[0075], [0116]-[0121], [0129]-[0130]).. Regarding Claim 7, Takekawa discloses a comparison circuit configured to provide an output signal based on the output signal of the sampling circuit and a reference signal (Figs. 9-10, 14 and 29, phase comparator 53 connected to sample-and-hold circuit 59 and Vref 57; ¶¶ [0059]-[0075], [0116]-[0121]). Regarding Claim 8, Takekawa discloses the comparison circuit comprises a comparator having a first input terminal, a second input terminal, and an output terminal, the first input terminal coupled to the output terminal of the sampling circuit, the second input terminal configured to receive the reference signal, and the output terminal configured to provide the output signal (Figs. 9-10, 14 and 29, phase comparator 53 connected to sample-and-hold circuit 59 and Vref 57 with output to charge pump 54 and low-pass filter 44/55/164; ¶¶ [0059]-[0075], [0116]-[0121]). Regarding Claim 9, Takekawa discloses the control circuit comprises a tracking circuit configured to determine the value of the third signal based on the reference signal and the output signal of the comparison circuit (Figs. 9-10, 14 and 29, control circuit 94, 126 and/or PLL circuit used as frequency amplifier circuits 151 and 152 with phase comparison results to control output voltage of charge pump supplied to VCO through the low-pass filter; ¶¶ [0059]-[0075], [0116]-[0121]). Regarding Claim 10, Takekawa discloses to determine the value of the third signal, the tracking circuit is configured to: adjust the first frequency of the first signal and the second frequency of the second signal; determine whether to conclude adjustment of the first frequency and the second frequency based on the output signal of the comparison circuit (Figs. 9-10, 14 and 29, control circuit 94, 126 and/or PLL circuit used as frequency amplifier circuits 151 and 152 with phase comparison results to control output voltage of charge pump supplied to VCO through the low-pass filter; ¶¶ [0059]-[0075], [0116]-[0121]); and based on determining to conclude the adjustment, determine the value of the third signal based on a value of the reference signal (Figs. 9-10, 14 and 29, control circuit 94, 126 and/or PLL circuit used as frequency amplifier circuits 151 and 152 with phase comparison results to control output voltage of charge pump supplied to VCO through the low-pass filter; ¶¶ [0059]-[0075], [0116]-[0121]). Regarding Claim 11, Takekawa discloses the control circuit is configured to determine a value of acceleration based on the value of the third signal, the first frequency, and the second frequency (Figs. 9-10, 14 and 29, control circuit 94, 126 and/or PLL circuit used as frequency amplifier circuits 151 and 152 with phase comparison results to control output voltage of charge pump supplied to VCO through the low-pass filter; ¶¶ [0059]-[0075], [0116]-[0121]). Regarding Claim 13, Takekawa discloses the first signal is a first pulse-shaped signal, and the second signal is a second pulse-shaped signal, wherein the first frequency is equal to the second frequency, and wherein the first pulse-shaped signal is out of phase relative to the second pulse-shaped signal (Figs. 9-10, 14 and 29, phase comparator 53 receiving equal frequency but out of phase signals B and C; ¶¶ [0059]-[0076], [0116]-[0121]). Regarding Claims 15-18 and 20, the method of the claims appear to be met by the operation of the device of claims 1, 7, 10-11 and 20. Claim(s) 4-5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takekawa in view of US 20160103174 to Aaltonen. Regarding Claim 4, Takekawa discloses the device of claim 3, but is silent regarding the amplification circuit comprises a first capacitor, a second capacitor, and an operational amplifier having a first input terminal, a second input terminal, and an output terminal, the first capacitor coupled between the input terminal of the amplification circuit and the first input terminal of the operational amplifier, the second capacitor coupled between the first input terminal of the operational amplifier and the output terminal of the operational amplifier, and the output terminal of the operational amplifier coupled to the output terminal of the amplification circuit. Aaltonen discloses the amplification circuit comprises a first capacitor (Fig. 1, either of variable capacitors 100, 102; ¶¶ [0030]-[0041]), a second capacitor (Fig. 1, either of switched-capacitor readout circuit parts 104/114; ¶¶ [0030]-[0041]), and an operational amplifier having a first input terminal, a second input terminal, and an output terminal (Fig. 1, operational amplifier; ¶¶ [0030]-[0041]), the first capacitor coupled between the input terminal of the amplification circuit and the first input terminal of the operational amplifier (Fig. 1, either of variable capacitors 100, 102 connected operational amplifier input; ¶¶ [0030]-[0041]), the second capacitor coupled between the first input terminal of the operational amplifier and the output terminal of the operational amplifier (Fig. 1, either of switched-capacitor readout circuit parts 104/114 connected operational amplifier input and output; ¶¶ [0030]-[0041]), and the output terminal of the operational amplifier coupled to the output terminal of the amplification circuit (Fig. 1, operational amplifier output; ¶¶ [0030]-[0041]). It would have been obvious to one of ordinary skill in the art before the effective filing of the application to modify the invention of Takekawa by providing the amplification circuit comprises a first capacitor, a second capacitor, and an operational amplifier having a first input terminal, a second input terminal, and an output terminal, the first capacitor coupled between the input terminal of the amplification circuit and the first input terminal of the operational amplifier, the second capacitor coupled between the first input terminal of the operational amplifier and the output terminal of the operational amplifier, and the output terminal of the operational amplifier coupled to the output terminal of the amplification circuit as in Aaltonen in order to provide for a well-known, simple alternative amplification circuit. See, e.g., "substitution of art-recognized equivalents" as discussed in MPEP 2144.06II "An express suggestion to substitute one equivalent component or process for another is not necessary to render such substitution obvious. In re Fout, 675 F.2d 297, 213 USPQ 532 (CCPA 1982)." Regarding Claim 5, Aaltonen discloses the second input terminal of the operational amplifier is configured to receive an input voltage (Fig. 1, either of variable capacitors 100, 102 connected to other operational amplifier input; ¶¶ [0030]-[0041]). Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takekawa in view of US 20190129042 to Yanagisawa. Regarding Claim 12, Takekawa discloses the device of claim 11, and further discloses the capacitive sensor is a capacitive accelerometer (Figs. 9-10, 14 and 29, detection circuit for relative capacitance difference acceleration sensor; ¶¶ [0010]-[0012], [0059]-[0075]). However, Takekawa does not disclose the device is associated with a tire pressure monitoring system (TPMS). Yanagisawa discloses the device is associated with a tire pressure monitoring system (TPMS) (Figs. 1-4 and 16, capacitance acceleration detection apparatuses (acceleration sensors) 2X, 2y, 2Z in a TPMS; ¶¶ [0056], [0216]). It would have been obvious to one of ordinary skill in the art before the effective filing of the application to modify the invention of Takekawa by providing the capacitive sensor is a capacitive accelerometer associated with a tire pressure monitoring system (TPMS) as in Yanagisawa in order to provide for a well-known, application for acceleration sensors. Regarding Claim 19, the method the claim appears to be met by the operation of the device of claim 12. Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Takekawa in view of US 20130152686 Venkatraman. Regarding Claim 14, Takekawa discloses the device of claim 1, and further discloses the capacitive sensor comprises a first capacitance between a first terminal and a terminal (Figs. 9-10, 14 and 29, capacitors C1 and C2; ¶¶ [0059]-[0075], [0116]-[0121]), and a second capacitance between a terminal and a second terminal (Figs. 9-10, 14 and 29, capacitors C1 and C2; ¶¶ [0059]-[0075], [0116]-[0121]), the first terminal coupled to the first output terminal of the excitation circuit, the second terminal coupled to the second output terminal of the excitation circuit (Figs. 9-10, 14 and 29, oscillator 50, 121, 122 outputs connected through buffers 51 and 52 to respective capacitors C1 and C2; ¶¶ [0059]-[0075], [0116]-[0121]). However, Takekawa does not explicitly disclose the first capacitance and second capacitance connected to a third terminal coupled to an input terminal of the monitoring circuit. Venkatraman discloses the first capacitance and second capacitance connected to a third terminal coupled to an input terminal of the monitoring circuit (Fig. 3, capacitor pair 34X; ¶¶ [0024]-[0031]). It would have been obvious to one of ordinary skill in the art before the effective filing of the application to modify the invention of Takekawa by providing the first capacitance and second capacitance connected to a third terminal coupled to an input terminal of the monitoring circuit as in Venkatraman in order to provide for a well-known, simple alternative capacitance circuit arrangement. See, e.g., "substitution of art-recognized equivalents" as discussed in MPEP 2144.06II "An express suggestion to substitute one equivalent component or process for another is not necessary to render such substitution obvious. In re Fout, 675 F.2d 297, 213 USPQ 532 (CCPA 1982)." Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to DAVID J BOLDUC whose telephone number is (571)270-1602. The examiner can normally be reached M-F, 10am-6pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Walter Lindsay, Jr. can be reached at (571) 272-1672. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DAVID J BOLDUC/Primary Examiner, Art Unit 2852
Read full office action

Prosecution Timeline

Feb 15, 2024
Application Filed
Apr 08, 2026
Non-Final Rejection mailed — §102, §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
84%
Grant Probability
91%
With Interview (+7.1%)
2y 2m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 721 resolved cases by this examiner. Grant probability derived from career allowance rate.

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