Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claims 1-20 are presented in the case.
Priority
Applicant's claim for the benefit of a prior-filed Provisional application 63/445,816 filed on 02/15/2023 is acknowledged.
Information Disclosure Statement
The information disclosure statement submitted on 07/22/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Allowable Subject Matter
Claims 7, 16 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim Objections
Claims 1-13 are objected to because of the following informalities:
Claim 1, line 2 recites the phrase “one fewer layers than a number of expected layers” which should be “one fewer circuit layer than a number of expected virtual layers”. Or physical/logic layer If supported by specification.
Claim 9, line 4 recites the phrase “an activation function” which should be an activation function circuitry”. See how claim 10 has a physical diode.
For the informalities above and wherever else they may occur appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-2 and 5-6 are rejected under 35 U.S.C. 103 as being unpatentable over Minixhofer et al. (US 20220058472 A1) hereinafter Minixhofer in view of Puchinger et al. (US 20220222516 A1) hereinafter Puchinger.
As to independent claim 1, Minixhofer teaches an analog neural network circuit comprising: [Analog neural network Fig. 1 110 ¶22]
at least one fewer layers than a number of expected layers of a neural network [single layer as multi-layer ¶22, ¶32 "a single layer of physical analog neurons, the techniques described herein allows the multi-layer analog neural network to be scaled up to ten, hundreds or thousands of layers "] such that at least two cycles of feeding back outputs and applying weights occur to complete all the expected layers of the neural network; [calculation cycles as feedback ¶47-48 "At each calculation cycle, each of the neuron outputs generated by the neurons X.sub.1, . . . , X.sub.n is fed as input to all analog neurons of the single layer 116 for using in the next calculation cycle"]
a control circuit for providing timing signals [controller with clocks (timing)¶58] including a feedback signal path to reuse circuitry of a layer for the at least two cycles; and [re-usable neurons output becomes input ¶37, ¶45]
an analog memory coupled to store outputs of the circuitry of the layer, [neuron output with memory and buffer ¶37, ¶52] the analog memory controllably coupled as part of the feedback signal path to the circuitry of the layer. [¶37, ¶47-48 " Each of the physical analog neurons includes a respective weight memory for storing weights that are used by the neuron to compute neuron outputs given neuron inputs"]
Minixhofer does not specifically teach control signal paths.
However, Puchinger teaches to control signal paths, [controller controls signal paths (switches)¶28 "digital controller 106 can control this circuitry by controlling the opening and closing of the switches in the circuitry"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the control circuitry disclosed by Minixhofer by incorporating the to control signal paths disclosed by Puchinger because both techniques address the same field of neural networks and by incorporating Puchinger into Minixhofer reduces components and resources need for a more efficient neural network [Puchinger ¶3]
As to dependent claim 2, the rejection of claim 1 is incorporated, Minixhofer and Puchinger further teach wherein the layers of the analog neural network circuit comprise at least two consecutive expected layers having a same number of neurons. [Puchinger same neurons can be reused (same number) ¶4, ¶27-30]
As to dependent claim 5, the rejection of claim 1 is incorporated, Minixhofer and Puchinger further teach wherein the layers of the analog neural network circuit comprise:
an input layer; [Puchinger input layer ¶27-28]
a folded layer providing hidden layers, [Minixhofer single layer becomes the layers (unfolds) ¶24-28 "use a single layer of physical analog neurons to create a multi-layer analog neural network"]
wherein the folded layer comprises the circuitry of the layer that is reused for the at least two cycles; and [Minixhofer layers used in cycles ¶5]
an output layer. [Puchinger output layer ¶27-28]
As to dependent claim 6, the rejection of claim 5 is incorporated, Minixhofer and Puchinger further teach wherein the control circuit generates a write control signal, a read control signal, an input control signal, an output control signal, and a weight-change control signal, [Puchinger wright ¶28, buffer reuses weights output (reads, input, weight) and clock control ¶12, ¶30, ¶41]
wherein the write control signal and the read control signal controllably couples the analog memory as part of the feedback signal path, [Puchinger controls switches (couples) for persisting (store in buffer) ¶12 "switch to act as another buffer to persist the output of the neuron when being reused as part of the second layer."]
wherein the input control signal couples output of the input layer to the folded layer, wherein the output control signal couples a final output of the folded layer to the output layer, and the weight-change control signal controls application of weights to the folded layer. [Puchinger switches control output of weights ¶12]
Claim 3 is rejected under 35 U.S.C. 103 as being unpatentable over Minixhofer and Puchinger as applied in the rejection of claim 1 above, and further in view of JANTSCHER et al. (US 20220309331 A1) hereinafter JANTSCHER.
As to dependent claim 3, Minixhofer and Puchinger teach the method of claim 1 above that is incorporated,
Minixhofer and Puchinger do not specifically teach wherein the analog neural network circuit provides a recurrent neural network.
However, JANTSCHER teaches wherein the analog neural network circuit provides a recurrent neural network. [RNN ¶53 "For layers following the first layer, it can be selected to use zero, one or more analog neurons as input neurons. This is required in order to implement recurrent neural network (RNN) architectures"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the network architecture disclosed by Minixhofer and Puchinger by incorporating the wherein the analog neural network circuit provides a recurrent neural network disclosed by JANTSCHER because all techniques address the same field of neural networks and by incorporating JANTSCHER into Minixhofer and Puchinger provides faster execution for calculation with efficient data processing [JANTSCHER ¶42].
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Minixhofer and Puchinger as applied in the rejection of claim 1 above, and further in view of Paramasivam et al. (US 20220222513 A1) hereinafter Paramasivam.
As to dependent claim 4, Minixhofer and Puchinger teach the method of claim 1 above that is incorporated,
Minixhofer and Puchinger do not specifically teach wherein the control circuit comprises an oscillator.
However, Paramasivam teaches wherein the control circuit comprises an oscillator. [oscillator for clocks (control) ¶123 "clock generator 1300 based on a ring oscillator 1302"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the network architecture disclosed by Minixhofer and Puchinger by incorporating the wherein the control circuit comprises an oscillator disclosed by Paramasivam because all techniques address the same field of neural networks and by incorporating Paramasivam into Minixhofer and Puchinger improves efficiency and effectiveness in performing neural network computation [Paramasivam ¶5].
Claims 8-10 are rejected under 35 U.S.C. 103 as being unpatentable over Minixhofer and Puchinger as applied in the rejection of claim 1 above, and further in view of Ambrogio et al. (US 20230306252 A1) hereinafter Ambrogio.
As to dependent claim 8, Minixhofer and Puchinger teach the method of claim 1 above that is incorporated,
Minixhofer and Puchinger do not specifically teach wherein the layers of the analog neural network circuit are each formed of a corresponding plurality of neurons, wherein each neuron is implemented by a neuron circuit comprising an array of resistive processing units (RPUs).
However, Ambrogio teaches wherein the layers of the analog neural network circuit are each formed of a corresponding plurality of neurons, wherein each neuron is implemented by a neuron circuit comprising an array of resistive processing units (RPUs). [neuron based RPUs wit arrays ¶31, ¶66 "RPU crossbar system 402, a first neuron layer 404, and a second neuron layer 406. The RPU crossbar system 402 comprises an RPU array"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the network architecture disclosed by Minixhofer and Puchinger by incorporating the wherein the layers of the analog neural network circuit are each formed of a corresponding plurality of neurons, wherein each neuron is implemented by a neuron circuit comprising an array of resistive processing units (RPUs) disclosed by Ambrogio because all techniques address the same field of neural networks and by incorporating Ambrogio into Minixhofer and Puchinger reduces errors in operations for improved results [Ambrogio ¶3].
As to dependent claim 9, the rejection of claim 8 is incorporated, Minixhofer, Puchinger and Ambrogio further teach wherein each neuron circuit further comprises:
a voltage adder coupled to receive outputs of the array of RPUs and a bias; and [Ambrogio summed weight input with voltage with RPU (Vout) ¶76 " generate a summed weighted input (e.g., analog voltages V.sub.OUT1, V.sub.OUT2, V.sub.OUTn) for each neuron"]
an activation function. [Ambrogio activation function circuitry ¶76]
As to dependent claim 10, the rejection of claim 9 is incorporated, Minixhofer, Puchinger and Ambrogio further teach wherein the activation function comprises a diode. [Puchinger diode ¶67]
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Minixhofer, Puchinger and Ambrogio as applied in the rejection of claim 8 above, and further in view of Kim et al. (US 20190318239 A1) hereinaftger Kim and LAM et al. (US 20220101107 A1) hereinafter LAM.
As to dependent claim 11, Minixhofer, Puchinger and Ambrogio teach the method of claim 8 above that is incorporated,
Minixhofer, Puchinger and Ambrogio do not specifically teach wherein each RPU comprises: a first PMOS transistor coupled to receive a weight at its gate; a first NMOS transistor coupled to receive the weight at its gate and coupled by its drain to a drain of the first PMOS transistor; a first capacitor coupled at a first end to the drains of the first NMOS transistor and the first PMOS transistor; a read PMOS transistor coupled at its gate to the first end of the first capacitor; a load at a drain of the read PMOS transistor;
However, Kim teaches wherein each RPU comprises:
a first PMOS transistor coupled to receive a weight at its gate; [Kim PMOS transistor Fig. 7 720 with weight ¶62-63]
a first NMOS transistor coupled to receive the weight at its gate and coupled by its drain to a drain of the first PMOS transistor; [Kim receives and stores weight using NMOS transistor with grate, drain ¶62-63]
a first capacitor coupled at a first end to the drains of the first NMOS transistor and the first PMOS transistor; [Kim storage capacitor 730 ¶62-63]
a read PMOS transistor coupled at its gate to the first end of the first capacitor; [Kim transistor 740 ¶62-63]
a load at a drain of the read PMOS transistor; and [Kim source drain terminals ¶62-63]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the network architecture disclosed by Minixhofer, Puchinger and Ambrogio by incorporating the wherein each RPU comprises: a first PMOS transistor coupled to receive a weight at its gate; a first NMOS transistor coupled to receive the weight at its gate and coupled by its drain to a drain of the first PMOS transistor; a first capacitor coupled at a first end to the drains of the first NMOS transistor and the first PMOS transistor; a read PMOS transistor coupled at its gate to the first end of the first capacitor; a load at a drain of the read PMOS transistor disclosed by Kim because all techniques address the same field of neural networks and by incorporating Kim into Minixhofer, Ambrogio and Puchinger uses less energy and provides acceleration of training [Kim ¶3].
Minixhofer, Puchinger, Ambrogio and Kim do not specifically teach a high pass filter at the drain of the read PMOS transistor.
However, LAM teaches a high pass filter at the drain of the read PMOS transistor. [transistor (has drain) with the filter ¶18-19 "filter comprises a high pass filter."]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the network architecture disclosed by Minixhofer, Puchinger, Ambrogio and Kim by incorporating the a high pass filter at the drain of the read PMOS transistor disclosed by LAM because all techniques address the same field of neural networks and by incorporating LAM into Minixhofer, Puchinger, Ambrogio and Kim enables models to better emulate a biological brain [LAM ¶5-6].
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Minixhofer, Puchinger and Ambrogio as applied in the rejection of claim 8 above, and further in view of SANDEROVICH et al. (US 20190380137 A1) hereinafter SANDEROVICH.
As to dependent claim 12, Minixhofer, Puchinger and Ambrogio teach the method of claim 8 above that is incorporated,
Minixhofer, Puchinger and Ambrogio do not specifically teach Analog Joint Source-Channel Coding (AJSCC), the RPUs coupled to receive an output of the AJSCC as an initial input for processing.
However, SANDEROVICH teaches Analog Joint Source-Channel Coding (AJSCC), the RPUs coupled to receive an output of the AJSCC as an initial input for processing. [joint source transmission (input/output) ¶51 "compression and transmission of video data using a joint source channel transmission"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the network architecture disclosed by Minixhofer, Puchinger and Ambrogio by incorporating Analog Joint Source-Channel Coding (AJSCC), the RPUs coupled to receive an output of the AJSCC as an initial input for processing disclosed by SANDEROVICH because all techniques address the same field of data manipulation and by incorporating SANDEROVICH into Minixhofer, Puchinger and Ambrogio provides high data throughputs for increasing bandwidths [SANDEROVICH ¶3-4]
Claims 13-15 are rejected under 35 U.S.C. 103 as being unpatentable over Kale (US 20210397929 A1) in view of Minixhofer and Puchinger.
As to independent claim 13, Kale teaches a wearable device comprising: [wearable ¶34]
one or more sensors for capturing physiological signals; and [sensor for temp, stress etc. (physiological) ¶118]
an analog neural network circuit [ANN ¶36, ¶58] coupled to receive output of the one or more sensors, wherein the analog neural network circuit comprises: [provides input to an ANN ¶36]
Kale does not specifically teach at least one fewer layers than a number of expected layers of a neural network; a control circuit for providing timing signals, an analog memory coupled to store outputs of the circuitry of the layer,
However, Minixhofer teaches at least one fewer layers than a number of expected layers of a neural network [single layer as multi-layer ¶22, ¶32 "a single layer of physical analog neurons, the techniques described herein allows the multi-layer analog neural network to be scaled up to ten, hundreds or thousands of layers "] such that at least two cycles of feeding back outputs and applying weights occur to complete all the expected layers of the neural network; [calculation cycles as feedback ¶47-48 "At each calculation cycle, each of the neuron outputs generated by the neurons X.sub.1, . . . , X.sub.n is fed as input to all analog neurons of the single layer 116 for using in the next calculation cycle"]
a control circuit for providing timing signals [controller with clocks (timing)¶58] including a feedback signal path to reuse circuitry of a layer for the at least two cycles; and [re-usable neurons output becomes input ¶37, ¶45]
an analog memory coupled to store outputs of the circuitry of the layer, [neuron output with memory and buffer ¶37, ¶52] the analog memory controllably coupled as part of the feedback signal path to the circuitry of the layer. [¶37, ¶47-48 " Each of the physical analog neurons includes a respective weight memory for storing weights that are used by the neuron to compute neuron outputs given neuron inputs"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the network circuitry disclosed by Kale by incorporating the at least one fewer layers than a number of expected layers of a neural network; a control circuit for providing timing signals, an analog memory coupled to store outputs of the circuitry of the layer disclosed by Minixhofer because both techniques address the same field of neural networks and by incorporating Minixhofer into Kale provides a computationally efficient neural network with leading performance [Minixhofer ¶24].
Kale and Minixhofer do not specifically teach control signal paths.
However, Puchinger teaches to control signal paths, [controller controls signal paths (switches)¶28 "digital controller 106 can control this circuitry by controlling the opening and closing of the switches in the circuitry"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the control circuitry disclosed by Kale and Minixhofer by incorporating the to control signal paths disclosed by Puchinger because all techniques address the same field of neural networks and by incorporating Puchinger into Kale and Minixhofer reduces components and resources need for a more efficient neural network [Puchinger ¶3]
As to dependent claim 14, the rejection of claim 13 is incorporated, Kale, Minixhofer and Puchinger further teach wherein the layers of the analog neural network circuit comprise:
an input layer; [Puchinger input layer ¶27-28]
a folded layer providing hidden layers, [Minixhofer single layer becomes the layers (unfolds) ¶24-28 "use a single layer of physical analog neurons to create a multi-layer analog neural network"]
wherein the folded layer comprises the circuitry of the layer that is reused for the at least two cycles; and [Minixhofer layers used in cycles ¶5]
an output layer. [Puchinger output layer ¶27-28]
As to dependent claim 15, the rejection of claim 14 is incorporated, Kale, Minixhofer and Puchinger further teach wherein the control circuit generates a write control signal, a read control signal, an input control signal, an output control signal, and a weight-change control signal, [Puchinger wright ¶28, buffer reuses weights output (reads, input, weight) and clock control ¶12, ¶30, ¶41]
wherein the write control signal and the read control signal controllably couples the analog memory as part of the feedback signal path, [Puchinger controls switches (couples) for persisting (store in buffer) ¶12 "switch to act as another buffer to persist the output of the neuron when being reused as part of the second layer."]
wherein the input control signal couples output of the input layer to the folded layer, wherein the output control signal couples a final output of the folded layer to the output layer, and the weight-change control signal controls application of weights to the folded layer. [Puchinger switches control output of weights ¶12]
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Kale, Minixhofer and Puchinger as applied in the rejection of claim 13 above, and further in view of Ambrogio.
As to dependent claim 17, Kale, Minixhofer and Puchinger teach the method of claim 13 above that is incorporated,
Kale, Minixhofer and Puchinger do not specifically teach wherein the layers of the analog neural network circuit are each formed of a corresponding plurality of neurons, wherein each neuron is implemented by a neuron circuit comprising an array of resistive processing units (RPUs).
However, Ambrogio teaches wherein the layers of the analog neural network circuit are each formed of a corresponding plurality of neurons, wherein each neuron is implemented by a neuron circuit comprising an array of resistive processing units (RPUs). [neuron based RPUs wit arrays ¶31, ¶66 "RPU crossbar system 402, a first neuron layer 404, and a second neuron layer 406. The RPU crossbar system 402 comprises an RPU array"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the network architecture disclosed by Kale, Minixhofer and Puchinger by incorporating the wherein the layers of the analog neural network circuit are each formed of a corresponding plurality of neurons, wherein each neuron is implemented by a neuron circuit comprising an array of resistive processing units (RPUs) disclosed by Ambrogio because all techniques address the same field of neural networks and by incorporating Ambrogio into Kale, Minixhofer and Puchinger reduces errors in operations for improved results [Ambrogio ¶3].
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Kale, Minixhofer, Puchinger and Ambrogio as applied in the rejection of claim 17 above, and further in view of SANDEROVICH.
As to dependent claim 18, Kale, Minixhofer, Puchinger and Ambrogio teach the method of claim 17 above that is incorporated,
Kale, Minixhofer, Puchinger and Ambrogio do not specifically teach Analog Joint Source-Channel Coding (AJSCC), the RPUs coupled to receive an output of the AJSCC as an initial input for processing.
However, SANDEROVICH teaches Analog Joint Source-Channel Coding (AJSCC), the RPUs coupled to receive an output of the AJSCC as an initial input for processing. [joint source transmission (input/output) ¶51 "compression and transmission of video data using a joint source channel transmission"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the network architecture disclosed by Kale, Minixhofer, Puchinger and Ambrogio by incorporating Analog Joint Source-Channel Coding (AJSCC), the RPUs coupled to receive an output of the AJSCC as an initial input for processing disclosed by SANDEROVICH because all techniques address the same field of data manipulation and by incorporating SANDEROVICH into Kale, Minixhofer, Puchinger and Ambrogio provides high data throughputs for increasing bandwidths [SANDEROVICH ¶3-4]
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Puchinger in view of Minixhofer.
As to independent claim 19, Puchinger teaches a method of operating an analog neural network comprising an input layer, [Analog neural network ¶4]
generating, by the control circuit of the analog neural network, a write control signal, a read control signal, an input control signal, an output control signal, and a weight-change control signal, [wright ¶28, buffer reuses weights output (reads, input, weight) and clock control ¶12, ¶30, ¶41]
wherein the write control signal and the read control signal controllably couples the analog memory of the analog neural network as part of a feedback signal path to reuse circuitry of the folded layer, [controls switches (couples) for persisting (store in buffer) ¶12 "switch to act as another buffer to persist the output of the neuron when being reused as part of the second layer."]
wherein the input control signal couples output of the input layer to the folded layer, wherein the output control signal couples a final output of the folded layer to the output layer, and the weight-change control signal controls application of weights to the folded layer. [Puchinger switches control output of weights ¶12]
Puchinger does not specifically teach a folded layer providing hidden layers such that at least two cycles of feeding back outputs and applying weights occur to complete all expected layers of the neural network, an output layer, a control circuit, and an analog memory.
However, Minixhofer teaches a folded layer providing hidden layers such that at least two cycles of feeding back outputs and applying weights occur to complete all expected layers of the neural network, an output layer, a control circuit, and an analog memory, [single layer becomes the layers (unfolds) ¶24-28 "use a single layer of physical analog neurons to create a multi-layer analog neural network"]
Accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filling date of the claimed invention to modify the network circuitry disclosed by Puchinger by incorporating the a folded layer providing hidden layers such that at least two cycles of feeding back outputs and applying weights occur to complete all expected layers of the neural network, an output layer, a control circuit, and an analog memory disclosed by Minixhofer because both techniques address the same field of neural networks and by incorporating Minixhofer into Puchinger provides a computationally efficient neural network with leading performance [Minixhofer ¶24].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Applicant is required under 37 C.F.R. § 1.111(c) to consider these references fully when responding to this action.
Tran et al. (US 20210174185 A1) teaches an adaptable neuron circuit is coupled to a neuron in a neuromorphic memory array, and the adaptable neuron circuit comprises a sample-and-hold circuit for sampling (see ¶11).
It is noted that any citation to specific pages, columns, lines, or figures in the prior art references and any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck, 699 F.2d 1331, 1332-33, 216 U.S.P.Q. 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 U.S.P.Q. 275, 277 (C.C.P.A. 1968)).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Beau Spratt whose telephone number is 571 272 9919. The examiner can normally be reached 8:30am to 5:00pm (PST).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jennifer Welch can be reached at 571 272 7212. The fax phone number for the organization where this application or proceeding is assigned is 571 483 7388.
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/BEAU D SPRATT/ Primary Examiner, Art Unit 2143
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