DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s Remarks/Arguments filed on January 20th, 2026, have been carefully considered.
Claims 1, 7, 12, 18, and 20 are currently amended.
No claims have been added or canceled.
Claims 1-20 are currently pending in the instant application.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over OH et al. [US2014/0075102] in view of Jeong et al. [US2021/0318957]. OH teaches controller of a nonvolatile memory device and a command scheduling method thereof. Jeong teaches memory controller, storage device including the memory controller, and method of operating the memory controller and the storage device.
Regarding claims 1, 12 and 20, OH teaches an apparatus [OH abstract, “…a controller…”], comprising:
a memory system [OH paragraph 0117, first lines “…a memory card system…”] comprising an input command queue [OH paragraph 0064, first lines “…The command scheduler 124 may queue commands input from the host 101. The command scheduler 124 may schedule the queued commands to control an execution priority of the commands…”]; and
a controller associated with the memory system [OH paragraph 0091, last lines “…The input commands may be queued at a controller 120 (refer to FIG. 1) before execution of the input commands…”], wherein the controller is configured to cause the apparatus to:
OH teaches the whole logical block address space maybe divided into three zones [OH paragraph 0085, middle lines “… A whole logical block address space may be divided into three zones. In FIG. 5, symbols "A", "B", "C", "D", "E1", and "E2" may indicate command input from the host. A symbol "ST" may indicate a table switching time. However, logical block addresses of the command B and C may exist at different zones. Thus, after the command B is performed, a table switching operation may be performed before the command C is performed….”]
OH fails to explicitly teach receive a first command comprising a first range of logical block addresses, the first range of logical block addresses comprising a first plurality of logical block addresses, a second command comprising a second range of logical block addresses, the second range of logical block addresses comprising a second plurality of logical block addresses, and a third command comprising a third range of logical block addresses, the third range of logical block addresses comprising a third plurality of logical block addresses.
However, Jeong does teach receive a first command comprising a first range of logical block addresses, the first range of logical block addresses comprising a first plurality of logical block addresses [Jeong paragraph 0065, most lines “…a range of a first logical address segment corresponding to the first read command segment may range from LBA1 to LBA25…”], a second command comprising a second range of logical block addresses, the second range of logical block addresses comprising a second plurality of logical block addresses [Jeong paragraph 0065, most lines “…A range of a second logical address segment corresponding to the second read command segment may range from LBA26 to LBA50…”], and a third command comprising a third range of logical block addresses, the third range of logical block addresses comprising a third plurality of logical block addresses [Jeong paragraph 0065, most lines “…A range of a third logical address segment corresponding to the third read command segment may range from LBA51 to LBA75…”].
OH and Jeong are analogous arts in that they both deal with zoned based data storage.
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of both OH’s command reordering with Jeong’s teachings of each command having a plurality of logical block addresses for the benefit of increasing the operational speed of the storage device by effectively using a cache memory mapping to improve the hit rate [Jeong paragraph 0032 and 0033, most lines “…a memory controller capable of improving map caching performance and increasing an operation speed of a storage device by effectively using a cache memory and a buffer memory. In an embodiment, a memory controller may effectively use a cache memory to improve a cache hit by caching mapping information from a buffer memory in the cache memory when a target command in a first queue is transferred to a second queue to be processed by a memory device…”]
wherein the first command is received prior to the second command and the second command is received prior to the third command [OH paragraph 0085, last lines “…symbols "A", "B", "C", "D", "E1", and "E2" may indicate command input from the host…”(They are in order of reception.)];
determine that a first logical block address of the third range of logical block addresses is contiguous with a last logical block address of the first range of logical block addresses based at least in part on receiving the first command, the second command, and the third command [OH figure 6, feature “C” and “D” and paragraph 0106, most lines “…commands having the same zone ID may be internally reordered. Commands may be reordered such that commands having adjacent logical block addresses are successively executed…” (The art teaches the same reordering of commands even though the command is the 3rd and 4th vs 2nd and 3rd the same teachings apply and read on the claims.)]; and
order the first command, the second command, and the third command in the input command queue, wherein the third command is ordered in the input command queue directly following the first command based at least in part on determining that the first logical block address of the third range of logical block addresses is contiguous with the last logical block address of the first range of logical block addresses [OH paragraph 0019, last lines “…the commands in the same zone are reordered such that commands having adjacent logical block addresses are successively executed…” and figure 6, feature “D” before “C”].
The examiner would also point out that the OH teaches an additional feature of a zone area that can divided the commands in the queue into zones, however this does not preclude it from also reading on the fact it shows it was known in the art to reorder the commands within the same zone which reads on the applicant’s claims.
Regarding claims 2 and 13, as per claim 1, OH teaches the controller is further configured to cause the apparatus to:
determine that a last logical block address of the first range of logical block addresses is non-contiguous with a first logical block address of the second range of logical block addresses based at least in part on receiving the first command, the second command, and the third command [OH figure 6, feature “C” and “D” and paragraph 0106, most lines “…commands having the same zone ID may be internally reordered. Commands may be reordered such that commands having adjacent logical block addresses are successively executed…” (The art teaches the same reordering of commands even though the command is the 2nd and 3rd vs 1st and 2nd the same teachings apply and read on the claims. This implies if commands are reordered then then those commands that are pushed out of position would have to be non-contiguous.)].
Regarding claims 3 and 14, as per claim 1, OH teaches receive a fourth command comprising a fourth range of logical block addresses prior to receiving the first command, the second command, and the third command [OH paragraph 0108, last lines “…First, whether a new command belongs to a specific zone may be determined. The new command may be inserted between a series of commands which are determined to exist at the same zone and are previously reordered…”(Where new command is the fourth command]; and
receive an indication that one or more operations associated with the fourth command are being performed based at least in part on receiving the first command, the second command, and the third command wherein determining that the first logical block address of the third range of logical block addresses is contiguous with the last logical block address of the first range of logical block addresses is based at least in part on determining that the one or more operations associated with the fourth command are being performed [OH paragraph 0112, all lines “…whether the new command is a read command may be determined. Since a user wants a read command to be executed instantly prior to a write command, the read command may have an execution priority prior to the write command…”(Where the priority would be determining the one or more operations associated with the fourth command…”].
Regarding claims 4 and 15, as per claim 1, OH teaches determine that the one or more operations associated with the fourth command are being performed, the controller is configured to cause the apparatus to:
receive an indication of a location of a pointer associated with the input command queue [OH paragraph 0055, all lines “…The SATA interface may support a native command queuing (NCQ) function in which a plurality of, for example, 32 commands are successively executed. Tagged command queuing (TCQ) may also be supported…”(where tags can act as pointers.)].
Regarding claim 5 and 16, as per claim 1, OH teaches the controller is further configured to cause the apparatus to:
receive a fifth command comprising a fifth range of logical block addresses and a sixth command comprising a sixth range of logical block addresses, wherein the fifth command is received prior to the fourth command and the sixth command is received after the fourth command [OH figure 5-6, feature E1 and E2 and paragraph 0106, all lines “…commands having the same zone ID may be internally reordered. Commands may be reordered such that commands having adjacent logical block addresses are successively executed. Alternatively, commands may be reordered such that a read command is executed prior to execution of a write command…”]; and
refrain from re-ordering the sixth command to directly follow the fifth command based at least in part on determining that the one or more operations associated with the fourth command are being performed [OH paragraph 0112, last lines “…Since a user wants a read command to be executed instantly prior to a write command, the read command may have an execution priority prior to the write command…”(The priority of the write command means it is refrained from re-ordering so as to give reads preference.) and paragraph 0114, all lines “… In operation S440, if the new command is not a read command, it may be inserted at the end of previously reordered commands. If the new command is inserted, the method may be ended…”].
Regarding claims 6 and 17, as per claim 1, OH teaches the first command, the second command, and the third command each comprise a first type of command [OH paragraph 0115, last lines “…the inventive concept in which a reordering operation based on an adjacent logical block address and a reordering operation based on a read command are sequentially performed at a reordering operation on commands having the same zone ID…”], and the controller is further configured to cause the apparatus to:
receive a seventh command comprising a seventh range of logical block addresses based at least in part on receiving the first command, the second command, and the third command [OH paragraph 0114, last lines “…if the new command is not a read command, it may be inserted at the end of previously reordered commands. If the new command is inserted, the method may be ended…”]; and
refrain from re-ordering the seventh command in the input command queue based at least in part on determining that the seventh command comprises a second type of command different than the first type of command [OH paragraph 0114, all lines “… In operation S440, if the new command is not a read command, it may be inserted at the end of previously reordered commands. If the new command is inserted, the method may be ended…”].
Regarding claims 7 and 18, as per claim 1, OH teaches a memory system controller associated with the memory system, wherein the memory system controller is configured to cause the apparatus to:
write first data associated with the first command to a first range of physical block addresses, second data associated with the third command to a second range of physical block addresses, and third data associated with the second command to a third range of physical block addresses based at least in part on ordering the first command, the second command, and the third command in the input command queue, wherein the first range of physical block addresses, the second range of physical block addresses, and the third range of physical block addresses are [OH paragraph 0106, all lines “…commands having the same zone ID may be internally reordered. Commands may be reordered such that commands having adjacent logical block addresses are successively executed. Alternatively, commands may be reordered such that a read command is executed prior to execution of a write command…”],
OH and Jeong teach ordered [OH paragraph 106, most lines “…commands having the same zone ID may be internally reordered. Commands may be reordered such that commands having adjacent logical block addresses are successively executed. Alternatively, commands may be reordered such that a read command is executed prior to execution of a write command…”] based on the first plurality of logical block addresses [Jeong paragraph 0065, most lines “…a range of a first logical address segment corresponding to the first read command segment may range from LBA1 to LBA25…”], the second plurality of logical block addresses [Jeong paragraph 0065, most lines “…A range of a second logical address segment corresponding to the second read command segment may range from LBA26 to LBA50…”], and the third plurality of logical block addresses [Jeong paragraph 0065, most lines “…A range of a third logical address segment corresponding to the third read command segment may range from LBA51 to LBA75…”], wherein the order comprises a first physical block address of the third range of physical block addresses that is contiguous with a last physical block address of the first range of physical block addresses [OH paragraph 0106, last lines “…Commands may be reordered such that commands having adjacent logical block addresses are successively executed. Alternatively, commands may be reordered such that a read command is executed prior to execution of a write command…” and paragraph 0124, middle lines “…The device controller 2220 may reorder and execute commands input from the UFS host 2100 at a data processing operation on the flash memory 2230. As described above, commands may be reordered to correspond to logical block addresses…”]. The examiner has determined that reordering a third read command before a second write command would place the start of the third range to be contiguous to the last address of the first command since it has been reordered.
Regarding claims 8 and 19, as per claim 1, OH teaches the controller is further configured to cause the apparatus to:
receive a plurality of commands that each comprise a respective range of logical block addresses, wherein each of the plurality of commands are received in a sequential order [OH paragraph 0085, last lines “…symbols "A", "B", "C", "D", "E1", and "E2" may indicate command input from the host…”];
determine that a first logical block address of a range of logical block addresses of one or more entries in the input command queue is contiguous with a last logical block address of a range of logical block addresses of a prior entry in the input command queue based at least in part on receiving the plurality of commands [OH paragraph 0019, last lines “…the commands in the same zone are reordered such that commands having adjacent logical block addresses are successively executed…”]; and
order each of the plurality of commands in the input command queue based at least in part on determining that the first logical block address of the range of logical block addresses of one or more entries in the input command queue is contiguous with the last logical block address of the range of logical block addresses of a previous entry in the input command queue [OH paragraph 0111, all lines “…If a command having a logical block address near to that of the new command exists, in operation S425, the new command may be inserted at a next order of the adjacent logical block address command…”].
Regarding claim 9, as per claim 1, the controller is further configured to cause the apparatus to:
receive an eighth command comprising an eighth range of logical block addresses and a ninth command comprising a ninth range of logical block addresses, wherein the eighth command is received prior to the ninth command OH figure 6, feature “C” and “D” and paragraph 0106, most lines “…commands having the same zone ID may be internally reordered. Commands may be reordered such that commands having adjacent logical block addresses are successively executed…” (This repeats the same as the above with just different numbers such as 8 and 9, but rejected under the same rational as the 2nd and 3rd above.)];
determine that a last logical block address of the ninth range of logical block addresses is contiguous with a first logical block address of the eighth range of logical block addresses based at least in part on receiving the eighth command and the ninth command [OH paragraph 0106, most lines “…commands having the same zone ID may be internally reordered. Commands may be reordered such that commands having adjacent logical block addresses are successively executed…”]; and
order the eighth command and the ninth command in the input command queue, wherein the eighth command is ordered in the input command queue directly following the ninth command based at least in part on determining that the last logical block address of the ninth range of logical block addresses is contiguous with the first logical block address of the eighth range of logical block addresses addresses [OH paragraph 0019, last lines “…the commands in the same zone are reordered such that commands having adjacent logical block addresses are successively executed…” and figure 6, feature “D” before “C” (This repeats the same as the above with just different numbers such as 8 and 9, but rejected under the same rational as the 2nd and 3rd above.)].
Regarding claim 10, as per claim 1, OH teaches a memory system controller comprising a processor for processing commands in the input command queue [OH paragraph 0060, all lines “…a controller 120 may include a processing unit 121…”], wherein the memory system controller maintains a table of a mapping between logical addresses and physical addresses [OH paragraph 0069, all lines “…The mapping table may store mapping information between logical block addresses and physical block addresses. The mapping table may store logical block addresses and physical block addresses corresponding to the logical block addresses…”].
Regarding claim 11, as per claim 1, OH teaches when ordered in the input command queue, entries associated with each of the first command, the second command, and the third command indicate a location in a buffer of the memory system that associated data is located [OH paragraph 0066, most lines “…The working memory 125 may be formed of a cache memory, a dynamic RAM (DRAM), a static RAM (SRAM), a PRAM, or a combination thereof…”].
Response to Arguments
Applicant’s arguments with respect to claims 1, 7, 12, 18, and 20 have been considered but are moot in view of new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC CARDWELL whose telephone number is (571)270-1379. The examiner can normally be reached on Monday - Friday 10-6pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Reginald Bragdon can be reached on (571) 272-4204. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC CARDWELL/Primary Examiner, Art Unit 2139
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