Prosecution Insights
Last updated: July 17, 2026
Application No. 18/443,002

SIGNAL TRANSMITTING DEVICE AND INSULATING CHIP

Non-Final OA §103
Filed
Feb 15, 2024
Priority
Aug 30, 2021 — JP 2021-140075 +1 more
Examiner
MCCALL SHEPARD, SONYA D
Art Unit
2898
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Rohm Co., Ltd.
OA Round
1 (Non-Final)
93%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 93% — above average
93%
Career Allowance Rate
1097 granted / 1181 resolved
+24.9% vs TC avg
Minimal +4% lift
Without
With
+3.8%
Interview Lift
resolved cases with interview
Fast prosecutor
2y 0m
Avg Prosecution
42 currently pending
Career history
1205
Total Applications
across all art units

Statute-Specific Performance

§101
0.6%
-39.4% vs TC avg
§103
73.5%
+33.5% vs TC avg
§102
16.8%
-23.2% vs TC avg
§112
6.4%
-33.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1181 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of Species A, claims 1-18 and 20 in the reply filed on 26 May 2026 is acknowledged. Specification The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-2, 11-18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chen US 9,380,705 in view of O’Sullivan et al. US 2020/0076512, and further in view of Kuwajima US 2017/0148732. PNG media_image1.png 189 504 media_image1.png Greyscale Chen US 9,380,705 Regarding claim 1, Chen in Figs. 1 and 2 col. 1, line 60 – col. 4, line 9 discloses a signal transmitting device col. 1, line 60 – col. 2, line 23, comprising: a first chip 210 including a first circuit 212 col. 2, lines 24-34; a first die pad 216 (e.g. support col. 3, lines 66-67) on which the first chip 210 is mounted; an insulating chip 230 col. 2, lines 41-43; a second chip 220 col. 2, lines 35-38 including a second circuit 222 configured to perform at least one of reception of a signal and transmission of a signal with the first circuit through the insulating chip col. 1, line 60 – col. 2, line 23; and a second die pad 226 on which the second chip 220 is mounted, wherein the insulating chip 230 includes a substrate 234 col. 2, lines 41-42. Chen does not expressly disclose an element insulation layer including a front surface and a back surface opposite to the front surface, the back surface being located closer to the substrate than the front surface is, and a first isolation element and a second isolation element arranged in the element insulation layer and configured to transmit the signal, the first isolation element includes a first frontward conductor arranged in the element insulation layer at a position closer to the front surface than to the back surface, and a first backward conductor arranged in the element insulation layer at a position closer to the back surface than to the front surface, the first backward conductor being opposed to the first frontward conductor in a thickness-wise direction of the element insulation layer, the second isolation element includes a second frontward conductor arranged in the element insulation layer at a position closer to the front surface than to the back surface, and a second backward conductor arranged in the element insulation layer at a position closer to the back surface than to the front surface, the second backward conductor being opposed to the second frontward conductor in the thickness-wise direction of the element insulation layer, the first backward conductor is electrically connected to the second backward conductor, and the insulating chip includes a back surface insulation layer arranged on a back surface of the substrate. However, in analogous art, O’Sullivan et al. in Fig. 10 and [0063] teach an integrated isolator device having a back-to-back configuration for providing electrical isolation between two circuits, in which multiple isolators formed on a single, monolithic substrate are connected in series to achieve a higher amount of electrical isolation for a single substrate than for isolators formed on separate substrates connected in series. O’Sullivan et al. further teach element insulation layer 1016, 1036, 1022 including a front surface and a back surface opposite to the front surface, the back surface being located closer to a substrate 206 than the front surface is, and a first isolation element 302 [0044] and a second isolation element 304 [0044] arranged in the element insulation layer and configured to transmit the signal, the first isolation element 302 includes a first frontward conductor 308 arranged in the element insulation layer at a position closer to the front surface than to the back surface, and a first backward conductor 310 arranged in the element insulation layer at a position closer to the back surface than to the front surface, the first backward conductor 310 being opposed to the first frontward conductor 308 in a thickness-wise direction of the element insulation layer, the second isolation element includes a second frontward conductor 312 arranged in the element insulation layer at a position closer to the front surface than to the back surface, and a second backward conductor 314 arranged in the element insulation layer at a position closer to the back surface than to the front surface, the second backward conductor 314 being opposed to the second frontward conductor 314 in the thickness-wise direction of the element insulation layer, the first backward conductor 310 is electrically connected to the second backward conductor 314. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of O’Sullivan et al. in the device of Chen for the purpose of providing electrical isolation between two circuits, in which multiple isolators formed on a single, monolithic substrate are connected in series to achieve a higher amount of electrical isolation for a single substrate than for isolators formed on separate substrates connected in series. Although Chen in Fig. 2 discloses the third chip 230 is bonded to support 226, Chen in view of O’Sullivan et al. do not expressly teach the insulating chip includes a back surface insulation layer arranged on a back surface of the substrate. However, in analogous art, Kuwajima teaches in Fig. 36 and [0234] a semiconductor chip CP is mounted over the upper surface of a die pad DP as a chip mounting portion such that the top surface of the semiconductor chip CP faces upward. The back surface of the semiconductor chip CP is bonded and fixed to the upper surface of the die pad DP via a die bonding material (adhesive) DB. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Kuwajima in the device of Chen and O’Sullivan et al. for the purpose of mounting the top surface of the semiconductor chip facing upward. Regarding claim 2, Chen in view of O’Sullivan et al. and further in view of Kuwajima teach the signal transmitting device according to claim 1. Kuwajima teaches wherein the back surface insulation layer DB includes an adhesive includes a resin [0234]. Regarding claim 11, Chen in view of O’Sullivan et al. and further in view of Kuwajima teach the signal transmitting device according to claim 1 but do not expressly teach wherein a thickness of the back surface insulation layer is greater than a distance between the first backward conductor and the front surface of the substrate in the thickness-wise direction of the element insulation layer. Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B). Regarding claim 12, Chen in view of O’Sullivan et al. and further in view of Kuwajima teach the signal transmitting device according to claim 1 but do not expressly teach wherein a thickness of the back surface insulation layer is smaller than a thickness of the substrate. Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B). Regarding claim 13, Chen in view of O’Sullivan et al. and further in view of Kuwajima teach the signal transmitting device according to claim 1 but do not expressly teach wherein a distance between the first frontward conductor and the first backward conductor in the thickness-wise direction of the element insulation layer is greater than a distance between the first backward conductor and the front surface of the substrate in the thickness-wise direction of the element insulation layer. Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B). Regarding claim 14, Chen in view of O’Sullivan et al. and further in view of Kuwajima teach the signal transmitting device according to claim 1 but do not expressly teach wherein a thickness of the back surface insulation layer is greater than a distance between the first backward conductor and the front surface of the substrate in the thickness-wise direction of the element insulation layer. Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B). Regarding claim 15, Chen in view of O’Sullivan et al. and further in view of Kuwajima teach the signal transmitting device according to claim 1 but do not expressly teach wherein a thickness of the back surface insulation layer is smaller than a distance between the first frontward conductor and the first backward conductor in the thickness-wise direction of the element insulation layer. Notwithstanding, one of ordinary skill in the art would have been led to the recited dimensions through routine experimentation and optimization. Applicant has not disclosed that the relative dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, Jn re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966). See also MPEP 2144.04(1V)(B). Regarding claim 16, Chen in view of O’Sullivan et al. and further in view of Kuwajima teach the signal transmitting device according to claim 1. O’Sullivan et al. in Fig. 3A and [0045] teach wherein a first pad 326 and a second pad 330 are formed on the front surface of the element insulation layer, the first frontward conductor 308 is electrically connected to the first pad, the second frontward conductor 312 is electrically connected to the second pad, the first frontward conductor 308 and the first circuit 110 are electrically connected by the first pad 326, and the second frontward conductor 312 and the second circuit 130 are electrically connected by the second pad 330. Regarding claim 17, Chen in view of O’Sullivan et al. and further in view of Kuwajima teach the signal transmitting device according to claim 1. O’Sullivan et al. in Figs. 3B-3D teaches wherein the first frontward conductor 310 includes a first frontward coil 310 having a spiral or annular shape, the first backward conductor includes a first backward coil 310 having a spiral or annular shape, the second frontward conductor 314 includes a second frontward coil 314 having a spiral or annular shape, and the second backward conductor 314 includes a second backward coil 314 having a spiral or annular shape. Regarding claim 18, Chen in view of O’Sullivan et al. and further in view of Kuwajima teach the signal transmitting device according to claim 17. O’Sullivan et al. in [0046]-[0048] teach wherein the signal transmitting device is configured to transmit a signal from the first circuit toward the second circuit through a transformer including the first isolation element and the second isolation element, the transformer includes a first signal transformer and a second signal transformer, the signal transmitted through the transformer includes a first signal and a second signal, the first signal is transmitted from the first circuit toward the second circuit through the first signal transformer, and the second signal is transmitted from the first circuit toward the second circuit through the second signal transformer. Regarding claim 20, Chen in Figs. 1 and 2 col. 1, line 60 – col. 4, line 9 discloses an insulating chip 230 configured to be bonded to a die pad by a bonding material, the insulating chip, comprising: a substrate 234. Chen does not expressly disclose an element insulation layer including a front surface and a back surface opposite to the front surface, the back surface being located closer to the substrate than the front surface is, and a first isolation element and a second isolation element arranged in the element insulation layer and configured to transmit the signal, the first isolation element includes a first frontward conductor arranged in the element insulation layer at a position closer to the front surface than to the back surface, and a first backward conductor arranged in the element insulation layer at a position closer to the back surface than to the front surface, the first backward conductor being opposed to the first frontward conductor in a thickness-wise direction of the element insulation layer, the second isolation element includes a second frontward conductor arranged in the element insulation layer at a position closer to the front surface than to the back surface, and a second backward conductor arranged in the element insulation layer at a position closer to the back surface than to the front surface, the second backward conductor being opposed to the second frontward conductor in the thickness-wise direction of the element insulation layer, the first backward conductor is electrically connected to the second backward conductor, and the insulating chip includes a back surface insulation layer arranged on a back surface of the substrate. However, in analogous art, O’Sullivan et al. in Fig. 10 and [0063] teach an integrated isolator device having a back-to-back configuration for providing electrical isolation between two circuits, in which multiple isolators formed on a single, monolithic substrate are connected in series to achieve a higher amount of electrical isolation for a single substrate than for isolators formed on separate substrates connected in series. O’Sullivan et al. further teach element insulation layer 1016, 1036, 1022 including a front surface and a back surface opposite to the front surface, the back surface being located closer to a substrate 206 than the front surface is, and a first isolation element 302 [0044] and a second isolation element 304 [0044] arranged in the element insulation layer and configured to transmit the signal, the first isolation element 302 includes a first frontward conductor 308 arranged in the element insulation layer at a position closer to the front surface than to the back surface, and a first backward conductor 310 arranged in the element insulation layer at a position closer to the back surface than to the front surface, the first backward conductor 310 being opposed to the first frontward conductor 308 in a thickness-wise direction of the element insulation layer, the second isolation element includes a second frontward conductor 312 arranged in the element insulation layer at a position closer to the front surface than to the back surface, and a second backward conductor 314 arranged in the element insulation layer at a position closer to the back surface than to the front surface, the second backward conductor 314 being opposed to the second frontward conductor 314 in the thickness-wise direction of the element insulation layer, the first backward conductor 310 is electrically connected to the second backward conductor 314. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of O’Sullivan et al. in the device of Chen for the purpose of providing electrical isolation between two circuits, in which multiple isolators formed on a single, monolithic substrate are connected in series to achieve a higher amount of electrical isolation for a single substrate than for isolators formed on separate substrates connected in series. Although Chen in Fig. 2 discloses the third chip 230 is bonded to support 226, Chen in view of O’Sullivan et al. do not expressly teach the insulating chip includes a back surface insulation layer arranged on a back surface of the substrate. However, in analogous art, Kuwajima teaches in Fig. 36 and [0234] a semiconductor chip CP is mounted over the upper surface of a die pad DP as a chip mounting portion such that the top surface of the semiconductor chip CP faces upward. The back surface of the semiconductor chip CP is bonded and fixed to the upper surface of the die pad DP via a die bonding material (adhesive) DB. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teachings of Kuwajima in the device of Chen and O’Sullivan et al. for the purpose of mounting the top surface of the semiconductor chip facing upward. Allowable Subject Matter Claims 3-10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: the prior art of record neither anticipates nor renders obvious in the context of the claims: 3. The signal transmitting device according to claim 2, wherein the insulating chip is bonded to the first die pad or the second die pad by a bonding material, and a thickness of the back surface insulation layer is greater than a thickness of the bonding material. 4. The signal transmitting device according to claim 3, wherein the bonding material is electrically insulative. 5. The signal transmitting device according to claim 1, wherein the back surface insulation layer includes an oxide film arranged on the back surface of the substrate, and an insulation layer arranged on a side of the oxide film opposite from the substrate. 6. The signal transmitting device according to claim 5, wherein a thickness of the insulation layer is greater than a thickness of the oxide film. 7. The signal transmitting device according to claim 5, wherein the insulating chip is bonded to the first die pad or the second die pad by a bonding material, and a thickness of the oxide film is smaller than a thickness of the bonding material. 8. The signal transmitting device according to claim 1, wherein the first chip is bonded to the first die pad by a first conductive bonding material, the second chip is bonded to the second die pad by a second conductive bonding material, and the insulating chip is bonded to the first die pad or the second die pad by an insulative bonding material. 9. The signal transmitting device according to claim 8, wherein a thickness of the back surface insulation layer is greater than a thickness of the first conductive bonding material. 10. The signal transmitting device according to claim 8, wherein a thickness of the back surface insulation layer is greater than a thickness of the second conductive bonding material. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SONYA D MCCALL-SHEPARD whose telephone number is (571)272-9801. The examiner can normally be reached M-F: 8:30 AM-5:00 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Julio J. Maldonado can be reached at (571)272-1864. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Sonya McCall-Shepard/Primary Examiner, Art Unit 2898
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Prosecution Timeline

Feb 15, 2024
Application Filed
Jun 11, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
93%
Grant Probability
97%
With Interview (+3.8%)
2y 0m (~0m remaining)
Median Time to Grant
Low
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