DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 5/29/2026 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 3, 5-6, 13-16, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Kachare et al. (US PGPUB 2022/0365707) in view of Mohan et al. (US PGPUB 2017/0147499).
With regard to Claim 1, Kachare teaches an apparatus, comprising:
one or more memory devices (Fig. 3: Flash Chips 325-1 through 325-8); and
a controller coupled with the one or more memory devices and configured to cause the apparatus to (Fig. 3: Controller 315):
receive a command to write data associated with a validity duration characteristic of the data ([0051] “As the descriptors imply, host write request handler 505 may handle write requests, such as write request 515, received from host 105 of FIG. 1.” [0053] “The retention period for a particular write request may be determined using retention period determiner 530. Retention period determiner may determine the retention period for a particular data in a number of different ways. In some embodiments of the disclosure, write request 515 may specify the data retention period to be applied for the data in that write request. For example, an application whose data is retained for no more than 24 hours may specify a retention period of 1 day as part of write request 515,” wherein the “retention period” is the “validity duration”, i.e. [0072] “once the retention period has expired the data may be automatically invalidated by storage device 120 of FIG. 1”.);
write the data to one or more first memory cells of a block of memory cells of the one or more memory devices ([0042] “SSD controller 315 may manage sending read requests and write requests to flash memory chips 325-1 through 325-8 along channels 320-1 through 320-4.” [0066] “Flash memory chips 325-1 through 325-8 may support two or more different programming step voltages. In programming data into flash memory chips 325-1 through 325-8, flash controller 335 may increment the voltage in a cell by a step voltage (which may be represented as ΔV) until the voltage in the cell meets or exceeds the target voltage (which may represent the value being stored in the cell).”); and
write an indication of the validity duration characteristic of the data in a second field of an [address table] (See Figure 8, [0084] “FTL 330 may include logical-to-physical mapping table 565. Logical-to-physical mapping table 565 may store... other pertinent information about data 605... for example, retention period 615 of FIG. 6. When FTL 330 of FIG. 3 receives write request 515 from host 105 of FIG. 1 and programs data 605 of FIG. 6 into flash memory chips 325-1 through 325-8 of FIG. 3, FTL 330 may update logical-to-physical mapping table 565 to store this information,” wherein the address table being a “physical-to-logical address table” is further taught below by Mohan.),
wherein each row of the [address table] includes:
a respective second field that indicates a respective validity duration characteristic corresponding to the respective physical address, wherein the respective second fields comprise the second field ([0034] “an application specifying a data retention period for data to be written to the storage device... The storage device may then automatically invalidate the data when the retention period expires.” See Fig. 8 showing that each row of the address tables includes a “Retention Period” characteristic specified in Column 615 which corresponds to a “Physical Address” specified in Column 805.).
With further regard to claim 1, Kachare does not teach the physical-to-logical address table configuration as described in claim 1. Mohan teaches
wherein the [address table] is a physical-to-logical address table associated with the block of memory cells (See Fig. 3B, wherein [0091] “Tables 324 and 338 are examples of second address translation tables 190, in which physical addresses are mapped to logical addresses.” [0053] “each NVM module has a single second address translation table 190 for handling the mapping... for all non-volatile memory in the NVM module.” [0047] “NVM devices 140, 142 are flash memory chips or die... Each NVM device includes a number of addressable and individually selectable blocks... each block contains the minimum number of memory cells.”),
wherein each row of the physical-to-logical address table corresponds to a respective physical address and each row of the physical-to-logical address table includes (See Fig. 3B showing two physical-to-logical address tables, wherein each row corresponds to a respective physical address, i.e. Table 324 having Row 330 corresponding to Physical Address “PA 2”.):
a respective first field that indicates a respective logical address corresponding to the respective physical address (See Fig. 3B showing, for example, Table 324 having Row 330 including a “Logical Address” field corresponding to the respective physical address, i.e. Table 324 having Row 330 including Logical Address “4181” corresponding to Physical Address “PA 2”), and
a respective second field that indicates a respective [validity characteristic] (See Fig. 3B showing, for example, Table 324 having Row 330 including a “Valid” field, i.e. ‘validity characteristic’, corresponding to the respective physical addresses. The “Valid” field instead storing the “validity duration characteristic” as taught above in Kachare.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the apparatus as disclosed by Kachare with the physical-to-logical address table configuration as taught by Mohan since this configuration “reduces the work needed to be done by a storage controller... Thus... the storage controller can provide higher performance for other operations in the storage device, and can therefore manage a greater amount of non-volatile memory than if the storage controller were handling all address mapping and other non-volatile memory management tasks for the storage device” (Kachare [0015]).
With regard to Claim 3, Kachare in view of Mohan teaches all the limitations of Claim 1 as described above. Kachare further teaches wherein the block of memory cells comprises the physical-to-logical address table ([0043] “Within each flash memory chip, the space may be organized into blocks, which may be further subdivided into pages, and which may be grouped into superblocks.” [0085] “logical-to-physical mapping table 565 of FIG. 5 may be stored in storage 575. Storage 575 may be a non-volatile storage, such as another flash memory... storage 575 may be an area on flash memory chips 325-1 through 325-8 of FIG. 3, rather than a separate storage.”).
With regard to Claim 5, Kachare in view of Mohan teaches all the limitations of Claim 1 as described above. Kachare further teaches wherein the controller is further configured to cause the apparatus to:
receive a second command to write second data associated with a second validity duration characteristic of the second data, the second validity duration characteristic being different than the validity duration characteristic ([0051] “As the descriptors imply, host write request handler 505 may handle write requests, such as write request 515, received from host 105 of FIG. 1.” [0052] “Host write request handler 505 may include submission queues 525-1, 525-2, and 525-3. Each submission queue 525-1 through 525-3 may be used for write requests with different associated retention periods. So, for example... submission queue 525-2 may be used for write requests with a data retention period of 1 week, submission queue 525-3 may be used for write requests with a data retention period of 1 month, and so on.” [0053] “write request 515 may specify the data retention period to be applied for the data in that write request.”);
write the second data to one or more third memory cells of the block of memory cells ([0042] “SSD controller 315 may manage sending read requests and write requests to flash memory chips 325-1 through 325-8 along channels 320-1 through 320-4.” [0066] “Flash memory chips 325-1 through 325-8 may support two or more different programming step voltages. In programming data into flash memory chips 325-1 through 325-8, flash controller 335 may increment the voltage in a cell by a step voltage (which may be represented as ΔV) until the voltage in the cell meets or exceeds the target voltage (which may represent the value being stored in the cell).”); and
write a second indication of the second validity duration characteristic of the second data in another second field, of the respective second fields, of the physical-to- logical address table associated with the block of memory cells (See Fig. 8 showing “Logical Address” 1005 having a “Retention Period” of “1W”, i.e. 1 week. [0084] “FTL 330 may include logical-to-physical mapping table 565. Logical-to-physical mapping table 565 may store... other pertinent information about data 605... for example, retention period 615 of FIG. 6. When FTL 330 of FIG. 3 receives write request 515 from host 105 of FIG. 1 and programs data 605 of FIG. 6 into flash memory chips 325-1 through 325-8 of FIG. 3, FTL 330 may update logical-to-physical mapping table 565 to store this information.” [0085] “logical-to-physical mapping table 565 of FIG. 5 may be stored in storage 575. Storage 575 may be a non-volatile storage, such as another flash memory... storage 575 may be an area on flash memory chips 325-1 through 325-8 of FIG. 3, rather than a separate storage.”).
With regard to Claim 6, Kachare in view of Mohan teaches all the limitations of Claim 1 as described above. Kachare further teaches wherein the controller is further configured to cause the apparatus to:
write the data, based at least in part on reading the data from the one or more first memory cells, to one or more fifth memory cells of a second block of memory cells of the one or more memory devices ([0047] “To avoid such data being lost, the garbage collection logic may program the valid data from such blocks into other blocks. Once the data has been programmed into a new block (and the table mapping logical block addresses (LBAs) to physical block addresses (PBAs) updated to reflect the new location of the data), the block may then be erased, returning the state of the pages in the block to a free state.”); and
write a third indication of the validity duration characteristic, based at least in part on reading the second field of the physical-to-logical address table associated with the block of memory cells, in a third field of a physical-to-logical address table associated with the second block of memory cells ([0084] “FTL 330 may include logical-to-physical mapping table 565. Logical-to-physical mapping table 565 may store... other pertinent information about data 605... for example, retention period 615 of FIG. 6,” wherein the “retention period”, i.e. “validity duration characteristic,” is written when the valid data is written into the new block, as described above in relation to the garbage collection operation.).
With regard to Claim 14, Kachare in view of Mohan teaches all the limitations of Claim 1 as described above. Kachare further teaches wherein the validity duration characteristic is associated with a rate of invalidation of the data ([0033] “Many applications know the retention time (exact or approximate) for the data when writing to a storage device, which may be measured in hours or days (among other possibilities). For example, some application messages may be erased automatically after 24 hours, or junk email may be deleted after 1 month.” [0034] “Embodiments of the disclosure support an application specifying a data retention period for data to be written to the storage device.”).
With regard to Claim 15, Kachare in view of Mohan teaches all the limitations of Claim 1 as described above. Kachare further teaches wherein the indication of the validity duration characteristic comprises a stream identifier associated with the data ([0052] “each submission queue 525-1 through 525-3 may be associated with a combination of a data retention period and a device stream ID, thus permitting stream IDs and data retention periods to be combined.” [0053] “property of write request 515 may be identified, which may in turn be used to determine the retention period for the data. Examples of such properties may include ... a stream identifier.”).
With regard to Claims 16 and 18, these claims are equivalent in scope to Claims 1 and 3 rejected above, merely having a different independent claim type, and as such Claims 16 and 18 are respectively rejected under the same grounds and for the same reasons as discussed above with regard to Claims 1 and 3.
With regard to Claim 16, this claim is equivalent in scope to Claim 1 rejected above, merely having a different independent claim type, and as such Claim 16 is rejected under the same grounds and for the same reasons as discussed above with regard to Claim 1.
With further regard to Claim 16, the claim recites additional elements not specifically addressed in the rejection of Claim 1. The Kachare reference also anticipates these additional elements of Claim 16, for example, Kachare teaches:
A non-transitory computer-readable medium storing code comprising instructions which, when executed by a processor of an electronic device, cause the electronic device to [perform operations] ([0150] “Embodiments of the disclosure may include a tangible, non-transitory machine-readable medium comprising instructions executable by one or more processors, the instructions comprising instructions to perform the elements of the disclosures as described herein.”).
With regard to Claim 20, this claim is equivalent in scope to Claim 1 rejected above, merely having a different independent claim type, and as such Claim 20 is rejected under the same grounds and for the same reasons as discussed above with regard to Claim 1.
Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Kachare in view of Mohan as applied to Claim 3 above, and further in view of Briggs (US PGPUB 2019/0138459).
With regard to claim 4, Kachare in view of Mohan teaches all the limitations of claim 3 as described above. Kachare in view of Mohan does not teach the validity duration being stored in the same block as the write data as described in claim 4. Briggs teaches wherein the controller is further configured to cause the apparatus to:
write metadata associated with the data to the block of memory cells, wherein the metadata associated with the data comprises the indication of the validity duration characteristic of the data ([0045] “Each occupied block 310o... may include block metadata 312... When the cache manager 200 allocates client data 124 to a free cache block 310F within the leaf 304, the cache manager 200 may map client metadata 124m associated with the client data 124 to the block metadata 312. Some examples of block metadata 312 include ... a time to live (TTL).” [0058] “TTL corresponding to when the client data 124 expires,” wherein the “TTL” is equivalent to the “retention period” disclosed above in Kachare, i.e. the “validity duration” characteristic.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the apparatus as disclosed by Kachare in view of Mohan with the metadata writing as taught by Briggs as this configuration is advantageous since it “has an advantage that it may permit the related block metadata 312 to be dynamic and/or potentially prevent the cache manager 200 from deleting or removing client data 124 that increases in value” (Briggs [0046]).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kachare in view of Mohan as applied to Claim 6 above, and further in view of Goldberg et al. (US PGPUB 2018/0267720).
With regard to Claim 7, Kachare in view of Mohan teaches all the limitations of Claim 6 as described above. Kachare in view of Mohan does not teach the writing based on a quantity of data as described in claim 7. Goldberg teaches
write the data to the one or more fifth memory cells based at least in part on a quantity of data, stored at the one or more memory devices and associated with the validity duration characteristic, satisfying a threshold ([0031] “when available space on a flash module is below a desired threshold, a garbage collector attempts to locate data blocks that host only a few active/valid/current pages of data for garbage collection. The garbage collector first moves the valid pages of data in a selected block to a new location,” wherein the garbage collection operation, i.e. as recited above in Kachare, is executed in response to the quantity of data being at a level which results in the available space being below a threshold.).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the apparatus as disclosed by Kachare in view of Mohan with the writing based on a quantity of data as taught by Goldberg as this “reduces write wear on flash storage cells and improves the lifetime of a flash storage system” (Goldberg [0032]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Kachare in view of Mohan as applied to Claim 6 above, and further in view of Mohan et al. (US PGPUB 2016/0019160).
With regard to claim 8, Kachare in view of Mohan teaches all the limitations of claim 6 as described above. Kachare in view of Mohan does not teach the storage density configuration as described in claim 8. Mohan teaches
wherein memory cells of the block of memory cells are configured in accordance with a first storage density configuration and memory cells of the second block of memory cells are configured in accordance with a second storage density configuration that is different than the first storage density configuration ([0084] “In some embodiments, health information table 222, memory operation parameters 224 and/or the second address translation table 226 are stored in a portion of NVM memory using a single-layer-cell (SLC) mode of operation”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the apparatus as disclosed by Kachare in view of Mohan with the storage density configuration as taught by Mohan in order “to allow for faster and more reliable retrieval and updating” (Mohan [0084]).
Claims 9-10 are rejected under 35 U.S.C. 103 as being unpatentable over Kachare in view of Mohan as applied to Claim 6 above, and further in view of In et al. (US PGPUB 2024/0069773).
With regard to claim 9, Kachare in view of Mohan teaches all the limitations of claim 6 as described above. Kachare in view of Mohan does not teach the opening of a block as described in claim 9. In teaches wherein the controller is further configured to cause the apparatus to:
open the second block of memory cells based at least in part on the validity duration characteristic, wherein writing the data to the one or more fifth memory cells of the second block of memory cells is based at least in part on opening the second block of memory cells ([0011] “Certain aspects are directed to a method for open block data relocation in a memory. In some examples, the method includes closing a first block based on a satisfies a threshold data-error condition of the first block, wherein the first block comprises invalid data and valid data. In some examples, the method includes opening a second block in response to closing the first block. In some examples, the method includes relocating the valid data from the first block to the second block,” wherein the “invalid data” is responsive to data exceeding the time specified in the “retention period”, i.e. “validity duration characteristic”, taught above in Kachare).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the apparatus as disclosed by Kachare in view of Mohan with the opening of a block as taught by In since “software may limit the amount of memory resources that are open, and thus, may not allow for multiple open blocks” (In [0023]).
With regard to Claim 10, Kachare in view of Mohan and In teaches all the limitations of Claim 9 as described above. Kachare further teaches wherein the controller is further configured to cause the apparatus to:
read the data from the one or more first memory cells based at least in part on reading the indication of the validity duration characteristic of the data ([0088] “Returning to FIG. 5, host read request handler 510 may receive read request 520 from host 105 of FIG. 1. Using logical address 610, host read request handler 510 may determine the physical address where the data is stored from logical-to-physical mapping table 565... Host read request handler 510 may then provide this information to flash controller 335, which may then read the data from flash memory chips 325-1 through 325-8 of FIG. 3, decode the data (as appropriate), and return the data back to host read request handler 510, which may then return the data to host 105 of FIG. 1. As discussed above, in some situations read request 520 may request data that has already been invalidated. In that case, host read request handler 510 may return an error directly.”).
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Kachare in view of Mohan as applied to Claim 6 above, and further in view of Alcantara et al. (US PGPUB 2015/0261797).
With regard to claim 11, Kachare in view of Mohan teaches all the limitations of claim 6 as described above. Kachare in view of Mohan does not teach the codeword writing as described in claim 11. Alcantara teaches
wherein the one or more first memory cells and the indication of the validity duration characteristic are associated with a codeword stored in the block of memory cells, and wherein the controller is further configured to cause the apparatus to ([0051] “the FRB organizes host data into codewords during write operations, and receives the codewords from the non-volatile memory (e.g., Flash memory).”):
write the data to the one or more fifth memory cells based at least in part on reading the data and the indication of the validity duration characteristic from the codeword stored in the block of memory cells ([0013] “reading the plurality of CWs from the first block stripe of the non-volatile memory one codeword at a time.” [0011] “a command to perform garbage collection in a first block stripe of the non-volatile memory from the CPU, the command including a second block stripe to write to and a plurality of valid logical block numbers (LBNs) corresponding to a first plurality of codewords (CWs) stored in the first block stripe; allocating space, by the FRB, in a buffer memory of the FRB for storage of the first plurality of CWs; storing, by the FRB, the first plurality of CWs into the allocated space in the buffer memory; transferring, by the FRB, a second plurality of CWs to a plurality of physical addresses in the second block stripe of the non-volatile memory; and sending, by the FRB, the plurality of valid LBNs and the plurality of physical addresses to the CPU to update a logical-to-physical table”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the apparatus as disclosed by Kachare in view of Mohan with the codeword writing as taught by Alcantara for purposes of “streamlining the write, read, and garbage collection processes of the controller 130, thus improving the performance of the SSD” (Alcantara [0058]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kachare in view of Mohan and Alcantara as applied to Claim 11 above, and further in view of In.
With regard to claim 12, Kachare in view of Mohan and Alcantara teaches all the limitations of claim 11 as described above. Kachare in view of Mohan and Alcantara does not teach the opening of a block as described in claim 12. In teaches wherein the controller is further configured to cause the apparatus to:
open a plurality of blocks of memory cells including the second block of memory cells; and write the data to the one or more fifth memory cells of the second block of memory cells based at least in part on opening the plurality of blocks of memory cells ([0011] “Certain aspects are directed to a method for open block data relocation in a memory. In some examples, the method includes closing a first block based on a satisfies a threshold data-error condition of the first block, wherein the first block comprises invalid data and valid data. In some examples, the method includes opening a second block in response to closing the first block. In some examples, the method includes relocating the valid data from the first block to the second block.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the apparatus as disclosed by Kachare in view of Mohan and Alcantara with the opening of a block as taught by In since “software may limit the amount of memory resources that are open, and thus, may not allow for multiple open blocks” (In [0023]).
With further regard to Claim 12, Kachare further teaches:
each block of memory cells of the plurality of blocks of memory cells associated with a different validity duration characteristic (See Figure 8 show a plurality of blocks being associated with different “retention period”, i.e. “validity duration”, characteristics.).
Claim 21 is rejected under 35 U.S.C. 103 as being unpatentable over Kachare in view of Mohan as applied to Claim 1 above, and further in view of Fujii et al. (US PGPUB 2023/0393948).
With regard to claim 21, Kachare in view of Mohan teaches all the limitations of claim 1 as described above. Kachare in view of Mohan does not teach the bitmap as described in claim 21. Fujii teaches wherein the controller is further configured to cause the apparatus to:
extract, from the physical-to-logical address table, a bitmap associated with a type of data based at least in part on scanning the physical-to-logical address table using a bit mask, an exclusive-or (XOR) operation, or a zero check ([0113] “The bitmap (T1511) is an exclusive-OR between the mapping tables generated at the time of extracting the backup target data, indicating whether the data is included (1) or not included (0) in order of block numbers.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the apparatus as disclosed by Kachare in view of Mohan with the bitmap as taught by Fujii for purposes of “reducing the restore time and the cost of using the cloud service” (Fujii [0186]).
Claim 22 is rejected under 35 U.S.C. 103 as being unpatentable over Kachare in view of Mohan as applied to Claim 1 above, and further in view of Murugesan et al. (US Patent 9,489,306).
With regard to claim 22, Kachare in view of Mohan teaches all the limitations of claim 1 as described above. Kachare in view of Mohan does not teach the data remaining in memory based on the validity duration characteristic as described in claim 22. Murugesan teaches wherein the controller is further configured to cause the apparatus to:
cause, based at least in part on the validity duration characteristic of the data, the data to remain in the block of memory cells until the data is invalidated (Col. 5 ll. 39-52: “a caching policy determines which type of data... is to be cached and the time period in which to retain such data in a cache storage. The retention period associated with cached data is also sometimes represented by a ‘time to live’ (TTL) period, which indicates a length of time from the creation timestamp that the cached data will remain in the cache storage. In some embodiments, a TTL period is stored with each of the one or more cache entries of cache storage 208. In some embodiments, after the TTL period associated with a cache entry expires, the cache entry is immediately removed from cache storage 208 or can be selectively filtered based on TTL depending upon which kind of cache storage is used.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the apparatus as disclosed by Kachare in view of Mohan with the data remaining in memory based on the validity duration characteristic as taught by Murugesan for purposes “of performing efficient cache invalidation” (Murugesan Col. 8 ln. 59).
Claims 23-24 are rejected under 35 U.S.C. 103 as being unpatentable over Kachare in view of Mohan as applied to Claim 1 above, and further in view of Kim et al. (US PGPUB 2023/0126807).
With regard to claim 23, Kachare in view of Mohan teaches all the limitations of claim 1 as described above. Kachare in view of Mohan does not teach the data transferring based on criteria as described in claim 23. Kim teaches wherein the controller is further configured to cause the apparatus to:
transfer the data from the block of memory cells based at least in part on a first set of criteria corresponding to the validity duration characteristic of the data; and transfer second data from the block of memory cells based at least in part on a second set of criteria corresponding to a second validity duration characteristic of the second data ([0006] “The controller... is configured to store the hot data in the first memory region, is configured to store the warm data in the second memory region, is configured to store the cold data in the third memory region, is configured to select a source block of first memory blocks included in the first memory region, is configured to select destination blocks in each of the second and third memory regions, and is configured to migrate each piece of unit data stored in the source block to the destination blocks of the second or third memory regions according to a degree of hotness of each piece of the unit data,” wherein the “hot” and “warm” data are the claimed “data” and “second data” respectively. [0069] “a method of migrating data to a destination block in the same memory region or a destination block in another memory region based on a time elapsing since data has been written in the source block.”).
Therefore, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to have modified the apparatus as disclosed by Kachare in view of Mohan with the data transferring based on criteria as taught by Kim “in order to utilize a space of the non-volatile memory more efficiently” (Kim [0069]).
With regard to Claim 24, Kachare in view of Mohan and Kim teaches all the limitations of Claim 23 as described above. Kim teaches wherein the controller is further configured to cause the apparatus to:
transfer third data from the block of memory cells based at least in part on a third set of criteria corresponding to a third validity duration characteristic of the third data ([0006] “The controller... is configured to store the hot data in the first memory region, is configured to store the warm data in the second memory region, is configured to store the cold data in the third memory region, is configured to select a source block of first memory blocks included in the first memory region, is configured to select destination blocks in each of the second and third memory regions, and is configured to migrate each piece of unit data stored in the source block to the destination blocks of the second or third memory regions according to a degree of hotness of each piece of the unit data,” wherein the “cold” data is the claimed “third data”. [0069] “a method of migrating data to a destination block in the same memory region or a destination block in another memory region based on a time elapsing since data has been written in the source block.”).
Response to Arguments
Applicant's arguments, see Pages 9-11 of the Remarks filed 5/29/2026, with respect to the rejections under 35 U.S.C. 102 of Claims 1, 16 and 20 have been fully considered but they are not persuasive. With respect to the Applicant’s argument that the newly amended language of Claims 1, 16 and 20 is not taught by the previously cited prior art, this argument has been fully considered but is moot in view of the newly cited Mohan et al. (US PGPUB 2017/0147499) reference as discussed above in the respective rejections.
With respect to the Applicant’s further arguments, Pages 8-9 of the Remarks, that the features of the remaining claims are not taught by the cited prior art, the Office respectfully disagrees. These arguments rely upon the arguments as presented in relation to Claim 1, and as such the Office directs the Applicant to the response above regarding these arguments.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure is as follows:
Battaje et al. (US PGPUB 2018/0004652) discloses a method and system implementing efficient garbage collection, including the marking of a translation table entry with an expiration timeout.
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/NICHOLAS J SIMONETTI/ Primary Examiner, Art Unit 2137 July 11, 2026
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