Prosecution Insights
Last updated: April 19, 2026
Application No. 18/443,116

DIFFERENTIAL SWITCH WITH HIGH OFF ISOLATION AND BANDWIDTH

Final Rejection §103
Filed
Feb 15, 2024
Examiner
CHEN, SIBIN
Art Unit
2896
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Texas Instruments Incorporated
OA Round
2 (Final)
87%
Grant Probability
Favorable
3-4
OA Rounds
2y 4m
To Grant
92%
With Interview

Examiner Intelligence

Grants 87% — above average
87%
Career Allow Rate
886 granted / 1023 resolved
+18.6% vs TC avg
Moderate +5% lift
Without
With
+5.1%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
16 currently pending
Career history
1039
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
42.2%
+2.2% vs TC avg
§102
40.9%
+0.9% vs TC avg
§112
14.2%
-25.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1023 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1-4 and 8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US 2018/0131360) in view of Lee (US 2016/0349906). Regarding claim 1, Wu discloses a circuit, comprising: a first switch [231] having a control terminal and first and second terminals, the first terminal of the first transistor coupled to a first input terminal, and the second terminal of the first transistor coupled to a first output terminal; a second switch [234] having a control terminal and first and second terminals, the first terminal of the second switch coupled to a second input terminal, and the second terminal of the second switch coupled to a second output terminal; a third switch [233] having a control terminal and first and second terminals, the first terminal of the third switch coupled to the first input terminal; a first capacitor [222] having first and second terminals, the first terminal of the first capacitor coupled to the second terminal of the third switch, and the second terminal of the first capacitor coupled to the second output terminal; a second capacitor [221] having first and second terminals, the first terminal of the second capacitor coupled to the second input terminal; and a fourth switch [232] having a control terminal and first and second terminals, the first terminal of the fourth switch coupled to the second terminal of the second capacitor, and the second terminal of the fourth switch coupled to the first output terminal. Wu does not disclose where the switches are implemented as transistors. However, Lee discloses implementing switches as transistors such as FETs and BJTs (par. 91). In view of such teaching, it would have been obvious to the ordinary artisan before the effective filing date of the claimed invention to modify the invention as indicated above by incorporating the switch design as taught in Lee for the purpose of utilizing a suitable and well-known type of switch implementation. Regarding claim 2, the combination as indicated above discloses wherein the control terminals of the first and second transistors are coupled together (the input IN21 and IN22 pass through in the straight path or the cross coupled path). Regarding claim 3, the combination as indicated above discloses wherein the control terminals of the third and fourth transistors are coupled together (the input IN21 and IN22 pass through in the straight path or the cross coupled path). Regarding claim 4, the combination as indicated above discloses wherein the first and second input terminals form a differential input and the first and second output terminals form a differential output. Regarding claim 8, the combination as indicated above discloses wherein the first and second transistors are controllable to be conductive in a forward direction in a first operational state and non-conductive in the forward direction in a second operational state, and wherein the third and fourth transistors are controllable to be non-conductive in the forward direction in the first operational state and conductive in the forward direction in the second operational state (since IN21 and IN22, as differential signals, would not propagate to the same output terminal simultaneously). Allowable Subject Matter Claims 11-16 and 19-24 are allowed. Claims 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Response to Arguments Applicant's arguments filed 1/16/26 have been fully considered but they are not persuasive. Regarding claim 1, applicant argues that Wu does not disclose "the first terminal of the first capacitor coupled to the second terminal of the third transistor," or "the second terminal of the first capacitor coupled to the second output terminal." The first capacitor is 222. The third transistor is 233. The first terminal (on the left) of the first capacitor 222 is coupled to the second terminal (on the right) of the third transistor 233. Furthermore, the second terminal (on the right) of the first capacitor 222 is coupled to the second output terminal (at OUT22). Applicant argues that Wu does not disclose "the first terminal of the second capacitor coupled to the second input terminal" or "the first terminal of the fourth transistor coupled to the second terminal of the second capacitor." The second capacitor is 221. The fourth transistor is 234. The first terminal (on the left) of the second capacitor 221 is coupled to the second input terminal IN22 (through 232). Furthermore, the first terminal (on the left) of the fourth transistor 234 is coupled to the second terminal (on the right) of the second capacitor 221 (electrically through 232 and 221). Since it is not claimed that these elements must be directly coupled, they are electrically coupled, meeting the claim limitations. Conclusion THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to SIBIN CHEN whose telephone number is (571)270-5768. The examiner can normally be reached 9:00am - 5:00pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jessica Han can be reached at (571) 272-2078. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SIBIN CHEN/ Primary Examiner, Art Unit 2896
Read full office action

Prosecution Timeline

Feb 15, 2024
Application Filed
Jul 16, 2025
Non-Final Rejection — §103
Jan 16, 2026
Response Filed
Jan 30, 2026
Final Rejection — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12603645
DISCHARGE CONTROL CIRCUIT
2y 5m to grant Granted Apr 14, 2026
Patent 12592685
FLIP-FLOPS AND INTEGRATED CIRCUITS INCLUDING THE SAME
2y 5m to grant Granted Mar 31, 2026
Patent 12587181
CLOCK SIGNAL CIRCUITS
2y 5m to grant Granted Mar 24, 2026
Patent 12587175
REDUCED POWER CONSUMPTION COMPUTE-IN-MEMORY SYSTEM, METHOD OF OPERATING SAME
2y 5m to grant Granted Mar 24, 2026
Patent 12580555
PHASE INTERPOLATOR AND NON-OVERLAPPING CLOCK GENERATOR
2y 5m to grant Granted Mar 17, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

AI Strategy Recommendation

Get an AI-powered prosecution strategy using examiner precedents, rejection analysis, and claim mapping.
Powered by AI — typically takes 5-10 seconds

Prosecution Projections

3-4
Expected OA Rounds
87%
Grant Probability
92%
With Interview (+5.1%)
2y 4m
Median Time to Grant
Moderate
PTA Risk
Based on 1023 resolved cases by this examiner. Grant probability derived from career allow rate.

Sign in with your work email

Enter your email to receive a magic link. No password needed.

Personal email addresses (Gmail, Yahoo, etc.) are not accepted.

Free tier: 3 strategy analyses per month