Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election of Group I, species V, figs. 15-17, claims 11-14, in the reply filed on 12/24/2025 and 02/10/2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
Claim Objections
Claim 11 is objected to because of the following informalities:
In claim 11 line 13, “a side” ---, should be corrected to ---, “the side” ---.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 11 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Morita et al (US Publication No. 20060221539) in view of Shamouilian et al (US Patent No. 6639783).
Regarding claim 11, Morita discloses an electrostatic chuck (i.e., such as ESC 101; see for example, fig. 6, para. [0095]- [0099]) comprising: a dielectric substrate (i.e., such as dielectric substrate 105; see for example, fig. 6, para. [0095]- [0099]) on which a plurality of first gas holes is formed (i.e., such as plurality of first gas holes 121s; see for example, fig. 6, para. [0095]- [0099]); a base plate (i.e., such as base plate 123; see for example, fig. 6, para. [0095]- [0099]) on which a second gas hole is formed (i.e., such as second gas hole 139s; see for example fig. 7, para. [0100]); and a joining layer (i.e., such as joining layer 11; see for example, fig. 6, para. [0095]- [0099]) which is provided between the dielectric substrate (i.e., such as dielectric substrate 105; see for example, fig. 6, para. [0095]- [0099]) and the base plate (i.e., such as base plate 123; see for example, fig. 6, para. [0095]- [0099]) and which is formed of an insulating material (i.e., such as insulating material alumina; see for example, fig. 6, para. [0095]- [0099]), wherein a first opening (i.e., such as first opening 109s; see for example, fig. 6, para. [0095]- [0099]) being an end (i.e., such as end of each 109 at the top face 111 of 105; see for example, fig. 6, para. [0095]- [0099]) of each of the first gas holes (i.e., such as plurality of first gas holes 121s; see for example, fig. 6, para. [0095]- [0099]) is formed in plurality (i.e., such as plurality of first gas holes 121s; see for example, fig. 6, para. [0095]- [0099]) on a surface (i.e., such as surface 111; see for example, fig. 6, para. [0095]- [0099]) of the dielectric substrate (i.e., such as dielectric substrate 105; see for example, fig. 6, para. [0095]- [0099]) on a side (i.e., such as side of center region bottom face of 105, top face of 123, and bonding face 11; see for example, fig. 6, para. [0095]- [0099]) of the joining layer (i.e., such as joining layer 11; see for example, fig. 6, para. [0095]- [0099]), a second opening (i.e., such as second opening 125s; see for example, fig. 6, para. [0095]- [0099]) being an end (i.e., such as end of each 125 at the bottom face of 123; see for example, fig. 6, para. [0095]- [0099]) of the second gas hole (i.e., such as second gas hole 139s; see for example fig. 7, para. [0100]) is formed on a surface (i.e., such as surface top face of base 123; see for example fig. 7, para. [0100]) of the base plate (i.e., such as base plate 123; see for example, fig. 6, para. [0095]- [0099]) on a side (i.e., such as side of center region bottom face of 105, top face of 123, and bonding face 11; see for example, fig. 6, para. [0095]- [0099]) of the joining layer (i.e., such as joining layer 11; see for example, fig. 6, para. [0095]- [0099]).
Morita does not explicitly disclose and the second opening is communicated with the plurality of first openings via a communication path formed on the joining layer.
Shamouilian discloses an ESC with integrated channel (i.e., such as ESC 100; see for example fig. 2A, Col. 3 lines 61+); wherein the second opening (i.e., such as second opening 132; see for example fig. 2A, Col. 3 lines 61+) is communicated (i.e., such as 114s communicate with 132 via 118; see for example fig. 2A, Col. 3 lines 61+) with the plurality of first openings (i.e., such as plurality of first openings 114; see for example fig. 2A, Col. 3 lines 61+) via a communication path (i.e., such as communication path 118; see for example fig. 2A, Col. 3 lines 61+) formed on the joining layer (i.e., such as joining layer 116; see for example fig. 2A, Col. 3 lines 61+).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the communication path in Morita, as taught by Shamouilian, as it provides the advantage of optimizing the circuit design towards ensuring a uniform wafer cooling.
Regarding claim 14, Morita in view of Shamouilian and the teachings of Morita as modified by Shamouilian have been discussed above.
Shamouilian further discloses the ESC with integrated channel (i.e., such as ESC 100; see for example fig. 2A, Col. 3 lines 61+); wherein the joining layer (i.e., such as joining layer 116; see for example fig. 2A, Col. 3 lines 61+) is a layer (i.e., such as layer 116; see for example fig. 2A, Col. 3 lines 61+) created by curing (i.e., such as curing; for instance, the layers are cured to form a ceramic body by co-firing or hot pressing; see for example fig. 2A, Col. 3 lines 61+) a solid adhesive sheet (i.e., such as solid adhesive sheet 126; see for example fig. 2A, Col. 3 lines 61+) on which the communication path (i.e., such as communication path 118; see for example fig. 2A, Col. 3 lines 61+) is formed in advance (i.e., such as formed in advance; for instance, the details of the plenum 118 in the second layer 116 are best understood by simultaneously referring to FIGS. 2A and 2B. The plenum 118 is formed by sculpting an upper surface 126 of the second layer 116 to produce a pattern of channels and/or grooves; see for example fig. 2A, Col. 3 lines 61+).
Claims 12-13 are rejected under 35 U.S.C. 103 as being unpatentable over Morita et al (US Publication No. 20060221539) in view of Shamouilian et al (US Patent No. 6639783) and further in view of Hayahara (US Publication No. 20200395235).
Regarding claim 12, Morita in view of Shamouilian and the teachings of Morita as modified by Shamouilian have been discussed above.
Morita further discloses the electrostatic chuck (i.e., such as ESC 101; see for example, fig. 6, para. [0095]- [0099]).
Shamouilian furthermore discloses the ESC with integrated channel (i.e., such as ESC 100; see for example fig. 2A, Col. 3 lines 61+).
Neither Morita nor Shamouilian explicitly discloses wherein an insulator film is provided on the surface of the base plate on the side of the joining layer.
Hayahara discloses an ESC device (i.e., such as ESC 1; see for example fig. 1, para. [0033]- [0056]); wherein an insulator film (i.e., such as insulator film 6; see for example fig. 1, para. [0033]- [0056]) is provided on the surface (i.e., such as surface of 3; see for example fig. 1, para. [0033]- [0056]) of the base plate (i.e., such as base plate 3; see for example fig. 1, para. [0033]- [0056]) on the side (i.e., such as bottom face side of 7; see for example fig. 1, para. [0033]- [0056]) of the joining layer (i.e., such as joining layer 7; see for example fig. 1, para. [0033]- [0056]).
Thus, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the insulative film in Morita, as taught by Hayahara, as it provides the advantage of optimizing the circuit design towards further protection against moisture, debris, and corrosion.
Regarding claim 13, Morita in view of Shamouilian and further in view of Hayahara and the teachings of Morita as modified by Shamouilian have been discussed above. Also, the teachings of Morita as modified by Hayahara have been discussed above as well.
Hayahara further discloses the ESC device (i.e., such as ESC 1; see for example fig. 1, para. [0033]- [0056]); wherein the insulator film (i.e., such as insulator film 6; see for example fig. 1, para. [0033]- [0056]) is a film (i.e., such as film 6; for instance, the adhesion layer 6 is any selectable adhesion layer, it is preferable that the adhesion layer 6 is made of a heat-resistant, insulating, and sheet-shaped or film-shaped adhesive resin such as a polyimide resin, a silicone resin, and an epoxy resin; see for example fig. 1, para. [0033]- [0056]) formed by spraying (i.e., such as spraying; for instance, both insulating plates 6 and 7 are any selectable adhesion layer, or insulating ceramic plate instead of a resin sheet or may be a sprayed film having insulating properties such as alumina; see for example fig. 1, para. [0033]- [0056]).
Claims 1-10 and 15 are not elected.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUAAMAR Q AL-TAWEEL whose telephone number is (571)270-0339. The examiner can normally be reached 0730-1700.
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/MUAAMAR QAHTAN AL-TAWEEL/Examiner, Art Unit 2838
/THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838