Prosecution Insights
Last updated: July 17, 2026
Application No. 18/443,461

ELECTROSTATIC CHUCK AND METHOD OF MANUFACTURING THE SAME

Non-Final OA §103
Filed
Feb 16, 2024
Priority
Feb 22, 2023 — JP 2023-025987
Examiner
AL-TAWEEL, MUAAMAR QAHTAN
Art Unit
2838
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Toto Ltd.
OA Round
3 (Non-Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
51 granted / 62 resolved
+14.3% vs TC avg
Strong +25% interview lift
Without
With
+24.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
56 currently pending
Career history
111
Total Applications
across all art units

Statute-Specific Performance

§103
78.6%
+38.6% vs TC avg
§102
21.4%
-18.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 62 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claims 1-11 are rejected under 35 U.S.C. 103 as being unpatentable over Nakamura et al (US Publication No. 20060209490) in view of Nagatomo (US Publication No. 20180201545) and further in view of Kuno et al (US Publication No. 20230317432). Regarding claim 1, Nakamura discloses (i.e., see for example fig. 5 as shown below, para. [0072]- [0115]); an electrostatic chuck (1), comprising: a dielectric substrate (2) which includes a placement surface (PS) on which an attracted object (W) is to be placed and in which through holes (7) that penetrate the placement surface (PS) are formed; an electrode terminal (8) which is provided on a surface (OSPS) of the dielectric substrate (2) on an opposite side (OSPS) to the placement surface (PS); a base plate (24) to be joined to the surface (OSPS) of the dielectric substrate (2) on the opposite side (OSPS) to the placement surface (PS); and a joining layer (26, 28) which is provided between the dielectric substrate (2) and the base plate (24) and which is formed of an insulating material (i.e., such as alumina; see for example para. [0033]), wherein when viewed from a direction (Y) perpendicular to the placement surface (PS), at least one space (i.e., 5; such as and through holes 5 communicated with the circular projected part 3a. And the electrostatic chuck 1 may comprise a plurality of convexities for supporting a wafer Won the gas packing face 3b if needed, see for example para. [0059]) is formed at a position (PSN) within the joining layer (26, 28) that does not overlap with any of the through holes (7) and the electrode terminal (8). PNG media_image1.png 367 563 media_image1.png Greyscale Nakamura does not explicitly disclose that is an upper-side surface including a surface. Nagatomo discloses an electrostatic chuck device (i.e., 1; see for example fig. 1, para. [0024]- [0055]); wherein that is an upper-side surface (i.e., 11a; such as a loading plate 11 having a loading upper surface side 11a on which a plate-shaped sample W such as a semiconductor wafer is loaded on the upper surface. On the loading surface 11a of the loading plate 11, a plurality of protrusion portions 11b having a diameter that is smaller than the thickness of the plate-shaped sample is formed at predetermined intervals, and these protrusion portions 11b support the plate-shaped sample W; see for example fig. 1, para. [0024]- [0055]) including a surface (i.e., bottom face surface of 19; such as the cooling gas is supplied to grooves 19 formed among a plurality of protrusion portions 11b on the upper surface of the loading plate 11 through the gas hole and cools the plate-shaped sample W; see for example fig. 1, para. [0024]- [0055]). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the surface-scheme in Nakamura, as taught by Nagatomo, as it provides the advantage of optimizing the circuit design towards efficient cooling to the processed wafer. Nakamura nor Nagatomo explicitly discloses at least one enclosed space defined by the dielectric substrate and the base plate. Kuno discloses a wafer placement table (i.e., such as ESC 10; see for example fig. 2, para. [0027]- [0033]); at least one enclosed space (i.e., such as at least one enclosed space 50; see for example fig. 2, para. [0027]- [0033]) defined (i.e., such as defined; for instance, when through-holes like lift pin holes are present, the temperature tends to increase around such the through-holes, so it is applicable that each of the gas intermediate passages 50 does not overlap the refrigerant flow channel 32; see for example fig. 8, para. [0059]) by the dielectric substrate (i.e., such as dielectric substrate/ceramic plate 20; see for example fig. 2, para. [0027]- [0033]) and the base plate (i.e., such as base plate/cooling plate 30; see for example fig. 2, para. [0027]- [0033]). Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to have optionally included the enclosed spaces in the bonding layer of the ESC in Nakamura, as taught by Kuno, as it provides the advantage of optimizing the circuit design towards reliable and effective cooling to the ESC during wafer processing. Regarding claim 2, Nakamura in view of Nagatomo and further in view of Kuno and the teachings of Nakamura as modified by Nagatomo have been discussed above. Also, the teachings of Nakamura as modified by Kuno have been discussed above as well. Nakamura further discloses (i.e., see for example fig. 5 as shown above, para. [0072]- [0115]); the electrostatic chuck (1), wherein when viewed from a direction (Y) perpendicular to the placement surface (PS), when a proportion (i.e., PRN; see for example fig. 2 as shown below, para. [0072]- [0115]) occupied by an area (A) of the at least one space (i.e., 5/3c; such as and through holes 5 communicated with the circular projected part 3a. And the electrostatic chuck 1 may comprise a plurality of convexities for supporting a wafer W on the gas packing face 3b if needed, see for example para. [0059]) per unit area (DL1, DL2) of the joining layer (26, 28) is assumed to be a space proportion (3c), the space proportion (3c) in a central part (DL1) of the joining layer (26, 28) is larger than the space proportion (3c) in an outer circumferential part (DL2) of the joining layer (26,28). PNG media_image2.png 391 385 media_image2.png Greyscale Regarding claim 3, Nakamura in view of Nagatomo and further in view of Kuno and the teachings of Nakamura as modified by Nagatomo have been discussed above. Also, the teachings of Nakamura as modified by Kuno have been discussed above as well. Nakamura further discloses (i.e., see for example fig. 5 as shown above, para. [0072]- [0115]) (i.e., Also, see for example fig. 2 as shown above, para. [0072]- [0115]); the electrostatic chuck (1), wherein the at least one space (i.e., 5/3c; such as and through holes 5 communicated with the circular projected part 3a. And the electrostatic chuck 1 may comprise a plurality of convexities for supporting a wafer Won the gas packing face 3b if needed, see for example para. [0059]) (i.e., see for example fig. 2 as shown above, para. [0072]- [0115]) comprises spaces (3cs) formed in plurality (i.e., 5s/3cs; such as and through holes 5 communicated with the circular projected part 3a. And the electrostatic chuck 1 may comprise a plurality of convexities for supporting a wafer Won the gas packing face 3b if needed, see for example para. [0059]), and a density (DNS1) of the spaces (3cs) in a central part (DL1) of the joining layer (26, 28) is higher than a density (DNS2) of the spaces (3cs) in an outer circumferential part (DL2) of the joining layer (26, 28). Regarding claim 4, Nakamura in view of Nagatomo and further in view of Kuno and the teachings of Nakamura as modified by Nagatomo have been discussed above. Also, the teachings of Nakamura as modified by Kuno have been discussed above as well. Nakamura further discloses (i.e., see for example fig. 5 as shown above, para. [0072]- [0115]) (i.e., Also, see for example fig. 2 as shown above, para. [0072]- [0115]); the electrostatic chuck (1), wherein the at least one space (i.e., 5/3c; such as and through holes 5 communicated with the circular projected part 3a. And the electrostatic chuck 1 may comprise a plurality of convexities for supporting a wafer Won the gas packing face 3b if needed, see for example para. [0059]) comprises spaces formed in plurality (i.e., 5s/3cs; such as and through holes 5 communicated with the circular projected part 3a. And the electrostatic chuck 1 may comprise a plurality of convexities for supporting a wafer Won the gas packing face 3b if needed, see for example para. [0059]), and each of the spaces (3cs) arranged in a central part (DL1) of the joining layer (26, 28) is larger than each of the spaces (3cs) arranged in an outer circumferential part (DL2) of the joining layer (26, 28). Regarding claim 5, Nakamura in view of Nagatomo and further in view of Kuno and the teachings of Nakamura as modified by Nagatomo have been discussed above. Also, the teachings of Nakamura as modified by Kuno have been discussed above as well. Nakamura further discloses (i.e., see for example fig. 5 as shown above, para. [0072]- [0115]) (i.e., Also, see for example fig. 2 as shown above, para. [0072]- [0115]); the electrostatic chuck (1), wherein the at least one space (i.e., 5/3c; such as and through holes 5 communicated with the circular projected part 3a. And the electrostatic chuck 1 may comprise a plurality of convexities for supporting a wafer Won the gas packing face 3b if needed, see for example para. [0059]) is formed so as to penetrate the joining layer (26, 28) in a direction (Y) perpendicular to the placement surface (PS). Regarding claim 6, Nakamura in view of Nagatomo and further in view of Kuno and the teachings of Nakamura as modified by Nagatomo have been discussed above. Also, the teachings of Nakamura as modified by Kuno have been discussed above as well. Nakamura further discloses (i.e., see for example fig. 5 as shown above, para. [0072]- [0115]) (i.e., Also, see for example fig. 2 as shown above, para. [0072]- [0115]); the electrostatic chuck (1), wherein an insulator film (i.e., 21; such as the heat radiating sheet 21 is produced by covering a resistor heating element 22 with an insulating sheet, see for example para. [0072]) is provided on a surface (i.e., top face of 24) of the base plate (24) on the joining layer-side (i.e., sheet 21 is between bottom layer 28 and top layer 26). Regarding claim 7, Nakamura in view of Nagatomo and further in view of Kuno and the teachings of Nakamura as modified by Nagatomo have been discussed above. Also, the teachings of Nakamura as modified by Kuno have been discussed above as well. Nakamura further discloses (i.e., see for example fig. 5 as shown above, para. [0072]- [0115]) (i.e., Also, see for example fig. 2 as shown above, para. [0072]- [0115]); the electrostatic chuck (1), wherein the insulator film (i.e., 21; such as the heat radiating sheet 21 is produced by covering a resistor heating element 22 with an insulating sheet, see for example para. [0072]) is a film formed by spraying (i.e., such as by a method for spray drying to obtain a composite material as a starting material, see for example para. [0087]). Regarding claim 8, Nakamura in view of Nagatomo and further in view of Kuno and the teachings of Nakamura as modified by Nagatomo have been discussed above. Also, the teachings of Nakamura as modified by Kuno have been discussed above as well. Nakamura further discloses (i.e., see for example fig. 5 as shown above, para. [0072]- [0115]) (i.e., Also, see for example fig. 2 as shown above, para. [0072]- [0115]); the electrostatic chuck (1), wherein the joining layer (26, 28) is a layer (i.e., such as the organic adhesive layers 26 and 28 have a function of moderating the difference of the thermal expansion between the electrostatic chuck 1 and the heat radiating sheet, see for example para. [0074]) created by curing (i.e., sintering/spraying) a solid adhesive sheet (i.e., such as a heat radiating sheet is stuck to the face in which the above-mentioned electrode 6 for electrostatic attraction is formed through the adhesive layer 26, see for example para. [0109]) on which a space part (i.e., such as the heat radiating sheet 21 is obtained by covering a resistor heating element 22 with an insulator. And as the insulator, similarly to the abovementioned adhesive layer 26, an imide resin, an epoxy resin, a silicone resin, and a phenol resin may be used, see for example para. [0109]) which is a depression (i.e., such as holes, setting face, and grooves are formed by drilling and grinding machining, see for example para. [0107]) or a through hole (i.e., 23; such as holes, setting face, and grooves are formed by drilling and grinding machining, see for example para. [0107]) is formed in advance (i.e., such as a method for forming the setting face using the plate-shaped ceramic of alumina and aluminum nitride, see for example para. [0107]). Regarding claim 9, Nakamura in view of Nagatomo and further in view of Kuno and the teachings of Nakamura as modified by Nagatomo have been discussed above. Also, the teachings of Nakamura as modified by Kuno have been discussed above as well. Nakamura further discloses (i.e., see for example fig. 5 as shown above, para. [0072]- [0115]) (i.e., Also, see for example fig. 2 as shown above, para. [0072]- [0115]); the electrostatic chuck (1), wherein a refrigerant flow path (29) for supplying a refrigerant (i.e., cooling medium; such as a flow channel 29 for passing a cooling medium is formed in the cooling member 24 sand heat from the heat radiating sheet 21 and setting face 3 is removed and discharged out of the system, see for example para. [0073]) is formed in the base plate (24), and when viewed from a direction (Y) perpendicular to the placement surface (PS), when a proportion (i.e., PRN; see for example fig. 2, para. [0072]- [0115]) occupied by an area (A) of the at least one space (i.e., 5/3c; such as and through holes 5 communicated with the circular projected part 3a. And the electrostatic chuck 1 may comprise a plurality of convexities for supporting a wafer Won the gas packing face 3b if needed, see for example para. [0059]) per unit area (DL1, DL2) of the joining layer (26, 28) is assumed to be a space proportion (3c), the space proportion (3c) in a first portion (i.e., Pl; see for example fig. 4 as shown below, para. [0065]- [0071]) of the joining layer (26, 28) which overlaps with an upstream side (USS) of the refrigerant flow path (29) is larger than the space proportion (3c) in a second portion (P2) of the joining layer (26, 28) which overlaps with a downstream side (DSS) of the refrigerant flow path (29). PNG media_image3.png 336 382 media_image3.png Greyscale Regarding claim 10, Nakamura in view of Nagatomo and further in view of Kuno and the teachings of Nakamura as modified by Nagatomo have been discussed above. Also, the teachings of Nakamura as modified by Kuno have been discussed above as well. Nakamura further discloses (i.e., see for example fig. 5 as shown above, para. [0072]- [0115]) (i.e., Also, see for example fig. 2 as shown above, para. [0072]- [0115]) (i.e., Also, see for example fig. 4 as shown above, para. [0065]- [0071]); the electrostatic chuck (1), wherein when viewed from a direction (Y) perpendicular to the placement surface (PS), the first portion (Pl) is at a position (PCC) closer to center than the second portion (P2). Regarding claim 11, Nakamura in view of Nagatomo and further in view of Kuno and the teachings of Nakamura as modified by Nagatomo have been discussed above. Also, the teachings of Nakamura as modified by Kuno have been discussed above as well. Nakamura further discloses (i.e., see for example fig. 5 as shown above, para. [0072]- [0115]) (i.e., Also, see for example fig. 2 as shown above, para. [0072]- [0115]) (i.e., Also, see for example fig. 4 as shown above, para. [0065]- [0071]); a method of manufacturing an electrostatic chuck (1), and curing (i.e., sintering/spraying) the adhesive sheet (21). And, for the rest of the limitations/features in claim 11 is rejected for the same reasons that have already been stated/discussed above in rejected claim 1. {See rejection of claim 1} Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to MUAAMAR Q AL-TAWEEL whose telephone number is (571)270-0339. The examiner can normally be reached 0730-1700. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Thienvu V Tran can be reached at (571) 270- 1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MUAAMAR QAHTAN AL-TAWEEL/ Examiner, Art Unit 2838 /THIENVU V TRAN/ Supervisory Patent Examiner, Art Unit 2838
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Prosecution Timeline

Feb 16, 2024
Application Filed
Oct 08, 2025
Non-Final Rejection mailed — §103
Jan 05, 2026
Response Filed
Jan 28, 2026
Final Rejection mailed — §103
Mar 09, 2026
Interview Requested
Apr 14, 2026
Request for Continued Examination
Apr 22, 2026
Response after Non-Final Action
May 11, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
99%
With Interview (+24.6%)
2y 5m (~0m remaining)
Median Time to Grant
High
PTA Risk
Based on 62 resolved cases by this examiner. Grant probability derived from career allowance rate.

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