Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the application filed on 02/16/2024.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/16/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 2, and 17 are objected to because of the following informalities: Regarding claim 2, in line 4, “to provide contribute” appears that it should read as “to contribute”. Regarding claim 17, in line 11, “power converter provide” appears that it should read as “power converter to provide”. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 7, 8, 11, and 17 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Shaikh et al. (US Patent Application Publication US 2023/0095471 A1, hereinafter “Shaikh”). Regarding claim 1, Shaikh discloses (see Fig. 1B, Fig. 2, Fig. 3, and Fig. 4) an apparatus comprising: a plurality of power converters (see Fig. 2), wherein ones of the plurality of power converters are multi-phase power converters configured to generate a corresponding one of a plurality of regulated supply voltages (V_reg1, V_reg2), the plurality of power converters comprising (see Fig. 2): a first power converter having a first plurality of phase circuits (converter comprising PPC102-1, SPC104-1), wherein the first power converter is configured to provide a first output current (output current to V_reg1); and a second power converter having a second plurality of phase circuits (converter comprising PPC102-2, SPC104-2, SPC104-3, SPC104-4), wherein the second power converter is configured to provide a second output current (output current to V_reg2); and a phase reassignment circuit (comprising Mux 103, Mux 113) configured to cause one or more selected ones of the first plurality of phase circuits to be reassigned to provide a portion of the second output current from the second power converter (see Fig. 4, where SPC104-1 is reassigned to provide current to output V_reg2) and further configured to cause one or more selected ones of the second plurality of phase circuits to provide a portion of the first output current from the first power converter (see Fig. 3, where SPC104-2 is reassigned to provide current to output V_reg1).
Regarding claim 7, Shaikh discloses (see Fig. 1B, Fig. 2, Fig. 3, and Fig. 4) wherein a given one of the plurality of regulated supply voltages is different from other ones of the plurality of regulated supply voltages (see [0028] “The respective regulated supply voltages provided by PPC 102-1 and PPC 102-2 may be different from one another in various embodiments.”).
Regarding claim 8, Shaikh discloses (see Fig. 1B, Fig. 2, Fig. 3, and Fig. 4) wherein, when a given one of the plurality of power converters is receiving a contribution to its output current from another one of the plurality of power converters, the given one of the plurality of power converters determines a one of the plurality of regulated supply voltages provided therefrom (see [0028] “It is further noted that during operation, the regulated supply voltages generated and provided by the various ones of the PPCs 102 may be varied during operation. For example, in an implementation of an IC that utilizes dynamic voltage and frequency scaling (DVFS) as part of a power management scheme, the regulated supply voltage provided by a given one of the PPCs 102 may change in accordance with the power needs of the system at any given time. The changes to a regulated supply voltage in such an embodiment may be put into effect by, e.g., a corresponding control circuit 101 that changes various operating parameters such as switching frequency. The control circuits 101 may in turn be coupled to power management circuitry from which it may receive commands to raise or lower the regulated supply voltage in accordance with needs of the loads to which power is being supplied.”).
Regarding claim 11, Shaikh discloses (see Fig. 1B, Fig. 2, Fig. 3, and Fig. 4) a method comprising: generating, using a plurality of multi-phase power converters (converter comprising PPC102-1, SPC104-1, and converter comprising PPC102-2, SPC104-2, SPC104-3, SPC104-4), a corresponding plurality of regulated supply voltages (V_reg1, V_reg2); and assigning, using a phase reassignment circuit (comprising Mux 103, Mux 113), at least one phase circuit of a first one of the plurality of multi-phase power converters to a second one of the plurality of multi-phase power converters (see Fig. 4, where SPC104-1 of converter comprising PPC102-1 and SPC104-1 is reassigned to converter comprising PPC102-2, SPC104-2, SPC104-3, SPC104-4), wherein the at least one phase circuit of the first one of the plurality of multi-phase power converters is configured to, when assigned to the second one of the plurality of multi-phase power converters, contribute a portion of an output current provided by the second one of the plurality of multi-phase power converters (see Fig. 4, where SPC104-1 is reassigned to provide a portion of current to output V_reg2).
Regarding claim 17, Shaikh discloses (see Fig. 1B, Fig. 2, Fig. 3, and Fig. 4) an apparatus comprising: a plurality of power converters (see Fig. 2), wherein a given one of the plurality of power converters is configured to provide a corresponding regulated supply voltage and includes a corresponding plurality of phase circuits configured to provide a portion of an output current provided by the given one of the plurality of power converters (converter comprising PPC102-1 and SPC104-1 provides current to output V_reg1; converter comprising PPC102-2, SPC104-2, SPC104-3, SPC104-4 provides current to output V_reg2); a plurality of switching circuits coupled between corresponding ones of the plurality of phase circuits of the plurality of power converters (Mux 103, Mux 113); and a phase reassignment circuit (comprising Mux 103, Mux 113, and signal “Config”) configured to, using ones of the plurality of switching circuits, cause one or more phase circuits of the given one of the plurality of power converters provide a portion of an output current generated by another one of the plurality of power converters (see Fig. 4, where SPC104-1 of converter comprising PPC102-1 and SPC104-1 is reassigned via Mux 103 and Mux 113 to converter comprising PPC102-2, SPC104-2, SPC104-3, SPC104-4, to provide a portion of output current to V_reg2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 9, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Shaikh in view of Ng et al. (US Patent Application Publication US 2021/0320590 A1, hereinafter “Ng”). Regarding claim 9, Shaikh discloses (see Fig. 2) wherein ones of the plurality of power converters include a corresponding one of a plurality of control circuits (Control Ckt 101-1, Control Ckt 101-2). Shaikh does not disclose wherein ones of the plurality of control circuits include a corresponding one of a plurality of error amplifiers. However, Ng teaches (see Fig. 1, Fig. 2, Fig. 3) wherein ones of the plurality of control circuits (122, 124, 126, 128) include a corresponding one of a plurality of error amplifiers (see Fig. 3, amplifier 32). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Shaikh wherein ones of the plurality of control circuits include a corresponding one of a plurality of error amplifiers, as taught by Ng, because it can help implement a PWM controller for each power converter to regulate the output voltage and current.
Regarding claim 10, Shaikh discloses (see Fig. 2) wherein a given one of the plurality of control circuits is configured to control a switching mode, a switching frequency, and a duty cycle for all phase circuits assigned to a corresponding one of the plurality of power converters (see [0026] “the control circuits 101 may operate their respective PPCs 102 in different modes of operations, such as pulse frequency modulation (PFM), pulse width modulation (PWM), and so on.”).
Claims 13, 14, 19, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Shaikh in view of Salus et al. (US Patent Application Publication US 2023/0031911 A1, hereinafter “Salus”). Regarding claim 13, Shaikh does not disclose further comprising conveying, via a demand current bus, a demand current value from the second one of the multi-phase power converters to the first one of the multi-phase power converters. However, Salus teaches (see Fig. 3) further comprising conveying, via a demand current bus (304), a demand current value from the second one of the multi-phase power converters (104(2)) to the first one of the multi-phase power converters (104(1)). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Shaikh to further comprise conveying, via a demand current bus, a demand current value from the second one of the multi-phase power converters to the first one of the multi-phase power converters, as taught by Salus, because it can help achieve load balancing between the outputs of the power converters. Regarding claim 14, Shaikh does not disclose further comprising providing, via a sense current bus, a sense current value from a phase circuit of the first one of the plurality of multi-phase power converters to a sense current receiver in the second one of the plurality of multi-phase power converters. However, Salus teaches (see Fig. 3, Fig. 4, and Fig. 6) further comprising providing, via a sense current bus (see bus connecting each PTR PHASE and PER PHASE: OUTPUT: CURRENT INFO), a sense current value from a phase circuit of the first one of the plurality of multi-phase power converters (corresponding phase PTR PHASE of 104(1)) to a sense current receiver (CSX 414) in the second one of the plurality of multi-phase power converters (corresponding phase PTR PHASE of 104(2)). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Shaikh to further comprise providing, via a sense current bus, a sense current value from a phase circuit of the first one of the plurality of multi-phase power converters to a sense current receiver in the second one of the plurality of multi-phase power converters, as taught by Salus, because it can help achieve load balancing between the outputs of the power converters.
Regarding claim 19, Shaikh does not disclose further comprising a sense current bus coupled between ones of the plurality of power converters, wherein the given one of the plurality of power converters includes a control circuit coupled to receive a sense current value via the sense current bus, wherein the control circuit is configured to, based on the sense current value, determine a number of phase circuits needed to enable regulation of a correspondingly generated output voltage. However, Salus teaches (see Fig. 3, Fig. 4, Fig. 5, and Fig. 6) further comprising a sense current bus (see bus connecting each PTR PHASE and PER PHASE: OUTPUT: CURRENT INFO) coupled between ones of the plurality of power converters (see respective PTR PHASES of 104(1) and 104(2)), wherein the given one of the plurality of power converters includes a control circuit (XCU of 104(1)) coupled to receive a sense current value via the sense current bus (OUTPUT: CURRENT INFO is sent to XCU of 104(1) via the sense current bus), wherein the control circuit is configured to, based on the sense current value, determine a number of phase circuits needed to enable regulation of a correspondingly generated output voltage (see 502 and 512, where the current information is used to map the required number of PTR PHASES according to 502). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Shaikh to further comprise a sense current bus coupled between ones of the plurality of power converters, wherein the given one of the plurality of power converters includes a control circuit coupled to receive a sense current value via the sense current bus, wherein the control circuit is configured to, based on the sense current value, determine a number of phase circuits needed to enable regulation of a correspondingly generated output voltage, as taught by Salus, because it can help achieve load balancing between the outputs of the power converters. Regarding claim 20, Shaikh does not disclose further comprising a demand current bus, wherein a control circuit of the given one of the plurality of power converters is configured to provide a demand current value, via the demand current bus, to the phase reassignment circuit. However, Salus teaches (see Fig. 3 and Fig. 5) further comprising a demand current bus (304), wherein a control circuit of the given one of the plurality of power converters (DCU and XCU of 104(1)) is configured to provide a demand current value (GANGING CURRENT INFO), via the demand current bus, to the phase reassignment circuit (502) (see [0063] “For example, one load domain in ganged load domain 302 acts as a master and all other load domains in ganged load domain 302 are slaves that follow the voltage programmed to the master.” And “By using ganging, PTR phases 208 from multiple dies 104(1) and 104(2) may be configured to serve the same ganged load domain 302.”). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Shaikh to further comprise a demand current bus, wherein a control circuit of the given one of the plurality of power converters is configured to provide a demand current value, via the demand current bus, to the phase reassignment circuit, as taught by Salus, because it can help achieve load balancing between the outputs of the power converters.
Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Shaikh in view of Salus, and further in view of Ng. Regarding claim 15, Shaikh does not disclose further comprising generating, using a sense current amplifier in the phase circuit of the first one of the plurality of multi-phase power converters, the sense current value. However, Ng teaches (see Fig. 2, and Fig. 3) further comprising generating, using a sense current amplifier (30) in the phase circuit of the first one of the plurality of multi-phase power converters (phase comprising 102 of converter comprising 102, 104), the sense current value (VCS). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Shaikh to further comprise generating, using a sense current amplifier in the phase circuit of the first one of the plurality of multi-phase power converters, the sense current value, as taught by Ng, because it can help implement a current sensing circuit to help achieve load balancing between the outputs of the power converters.
Allowable Subject Matter
Claims 2-6, 12, 16, and 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 2, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the plurality of power converters includes a third power converter having a third plurality of phase circuits, wherein the phase reassignment circuit is configured to reassign one or more selected ones of the third plurality of phase circuits to provide contribute output current to one of the first or second output currents.”. Claims 3-6 are objected due to their dependency on claim 2. Regarding Claim 12, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “further comprising assigning, using the phase reassignment circuit, at least one phase circuit of a third one of the plurality of multi-phase power converters to the second one of the plurality of multi-phase power converters.”. Regarding Claim 16, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “further comprising disabling, using the phase reassignment circuit, a control circuit corresponding to one of the plurality of multi-phase power converters in response to determining that all phase circuits of the one of the multi-phase power converters are assigned to provide respective output currents to other ones of the plurality of multi-phase power converters.”. Regarding Claim 18, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “wherein the phase reassignment circuit is configured to disable a control circuit of the given one of the plurality of power converters in response to determining that all phase circuits of the given one of the plurality of power converters are assigned to provide output current to other ones of the plurality of power converters.”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US Patent Application Publication US 2021/0257909 A1 discloses a reconfigurable power converter. US Patent Application Publication US 2021/0036596 A1 discloses a plurality of voltage regulators provided for multiple outputs in a power converter. US Patent Application Publication US 2018/0302077 A1 discloses a multi-phase voltage regulator power phase duty cycle control method. US Patent US 10,126,791 B2 discloses a programmable power management integrated circuit.
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/MONICA LEWIS/ Supervisory Patent Examiner, Art Unit 2838
/JYE-JUNE LEE/Examiner, Art Unit 2838