DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claim 1-3, 5-7, and 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Coolbaugh et al. (US publication 2006/0145296 A1), hereinafter referred to as Coolbaugh.
Regarding claim 1, Coolbaugh teaches a semiconductor device (fig. 5i and related text) comprising: a substrate (405, [0065]); an element insulating layer (425/485/540/505, [0065 and 0077]) provided on the substrate; and a semiconductor resistance layer (450/560, [0086]) provided on the element insulating layer (fig. 5i), wherein the semiconductor resistance layer includes: a front surface side resistance layer (560) extending in a first direction (horizontal) perpendicular to a thickness direction of the substrate (fig. 5i); a substrate side resistance layer (450) arranged closer to the substrate than the front surface side resistance layer in the thickness direction (fig. 5i); and an internal connector (connector (475a/525a/570a/530) and another two connector shown in fig. 5i, [0091]) that electrically connects the front surface side resistance layer and the substrate side resistance layer in series ([0091]).
Regarding claim 2, Coolbaugh teaches wherein the substrate side resistance layer includes an overlap region that overlaps with the front surface side resistance layer when viewed from the thickness direction (fig. 5i).
Regarding claim 3, Coolbaugh teaches wherein the overlap region is formed over an entirety of the substrate side resistance layer in the first direction (fig. 5i).
Regarding claim 5, Coolbaugh teaches wherein the internal connector includes: a first internal via connected to the front surface side resistance layer; a second internal via provided at a different position from the first internal via in the first direction and connected to the substrate side resistance layer; and an internal wiring layer arranged at a different position from both the front surface side resistance layer and the substrate side resistance layer in the thickness direction and connected to both the first internal via and the second internal via (fig. 5i).
Regarding claim 6, Coolbaugh teaches wherein the internal connector includes an internal via connected to both the front surface side resistance layer and the overlap region of the substrate side resistance layer (fig. 5i).
Regarding claim 7, Coolbaugh teaches wherein both the front surface side resistance layer and the substrate side resistance layer have a first end portion and a second end portion, which are both end portions in the first direction, and wherein the internal via connects the second end portions of the front surface side resistance layer and the substrate side resistance layer in the first direction (fig. 5i).
Regarding claim 18, Coolbaugh teaches wherein when viewed from the thickness direction, a width dimension of the front surface side resistance layer and a width dimension of the substrate side resistance layer are equal to each other (fig. 5i).
Regarding claim 19, Coolbaugh teaches wherein a thickness of the front surface side resistance layer and a thickness of the substrate side resistance layer are equal to each other (fig. 5i).
Regarding claim 20, Coolbaugh teaches wherein the element insulating layer includes: a substrate side insulating layer provided on the substrate; and a front surface side insulating layer stacked on the substrate side insulating layer, wherein the substrate side insulating layer has a structure in which a plurality of first insulating films and a plurality of second insulating films that relieves a stress of the first insulating films are alternately stacked one by one, and wherein the semiconductor resistance layer is embedded in the front surface side insulating layer (fig. 5i).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 4 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Coolbaugh, as applied to claim 1 above.
Regarding claim 4, Coolbaugh discloses all the limitations of claim 1 as discussed above on which this claim depends.
Coolbaugh does not explicitly teach wherein in the first direction, the front surface side resistance layer is longer than the substrate side resistance layer. However, Coolbaugh teaches different variation of length of the front surface side resistance layer compared to the substrate side resistance layer (the front surface side resistance layer length is equal to the substrate side resistance layer (fig. 1f), the front surface side resistance layer length is a little shorter than the substrate side resistance layer (fig. 2e), the front surface side resistance layer length is about half of the substrate side resistance layer (fig. 5i)) and thus makes it obvious that the front surface side resistance layer and the substrate side resistance layer length is a parameter that one must consider and decide upon and is something that can be optimized through routine experimentation.
Furthermore, it has been held where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. (MPEP §2144.05 II/III).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Coolbaugh so that wherein in the first direction, the front surface side resistance layer is longer than the substrate side resistance layer for the purpose of optimizing device performance and overall size of the device.
Regarding claim 17, Coolbaugh discloses all the limitations of claim 1 as discussed above on which this claim depends.
In another embodiment Coolbaugh teaches wherein in the first direction, a length of the front surface side resistance layer and a length of the substrate side resistance layer are equal to each other (fig. 1f). Also, Coolbaugh teaches different variation of length of the front surface side resistance layer compared to the substrate side resistance layer (the front surface side resistance layer length is equal to the substrate side resistance layer (fig. 1f), the front surface side resistance layer length is a little shorter than the substrate side resistance layer (fig. 2e), the front surface side resistance layer length is about half of the substrate side resistance layer (fig. 5i)) and thus makes it obvious that the front surface side resistance layer and the substrate side resistance layer length is a parameter that one must consider and decide upon and is something that can be optimized through routine experimentation.
Furthermore, it has been held where the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation. (MPEP §2144.05 II/III).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Coolbaugh so that wherein in the first direction, a length of the front surface side resistance layer and a length of the substrate side resistance layer are equal to each other for the purpose of optimizing device performance and overall size of the device.
Allowable Subject Matter
Claims 8-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The claims contain limitations that none of the prior art of record discloses, teaches or fairly suggests, alone or in combinations when taken in combination with all other limitations of the base claim and any intervening claims.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mohammed R Alam whose telephone number is 469-295-9205 and can normally be reached between 8:00am-6:00pm (M-F) or by e-mail via Mohammed.Alam1@uspto.gov.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached on 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/MOHAMMED R ALAM/Primary Examiner, Art Unit 2897
Prosecution Insights