DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-4, 7-8, 12-14, 16-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Muramatsu et al. (US PG. Pub. 2006/0272853) in view of Tanaka et al. (US PG. Pub. 215/0181703).
Regarding claim 1 – Muramatsu teaches a printed circuit board (fig. 1, 1A [paragraph 0117] Muramatsu states, “wiring board 1A”) comprising: a glass layer (33 [paragraph 0124] Muramatsu states, “the ceramic layers 33 are alumina, silicon nitride, aluminum nitride, and glass ceramics produced by adding an inorganic filler such as borosilicate glass or borosilicate lead glass”) having a first surface (lower surface of component 3), and a second surface (top surface of component 3) opposing the first surface; a through-via (32 [paragraph 0122] Muramatsu states, “penetration conductors 32”) penetrating the glass layer (33); a first insulating layer (B21 [0129] Muramatsu states, “B21-B24 are basically made of a resin material such as an epoxy resin and contain an appropriate amount of inorganic filler such as a silica powder for adjustment of the dielectric constant or the dielectric breakdown voltage”) disposed on the first surface (claimed structure shown in figure 1); a second insulating layer (B0 & 4 [paragraph 0128] Muramatsu states, “The groove-filling portion 4 and the lowest resin insulating layer B0 may be made of a resin produced by adding acid anhydride to an epoxy resin”) disposed on the second surface (top surface of component 3) of the glass layer (33) and covering a side surface of the glass layer (33) connecting the first surface and the second surface of the glass layer (claimed structure shown in figure 1); a second wiring layer (wirings 53 shown on surface of B11 [paragraph 0135] Muramatsu states, “CU-plating-formed interconnections 51 and 53”) disposed on the second insulating layer (B0 & 4); and a connection via (65 [paragraph 0136] Muramatsu states, “via conductors 65”) penetrating the second insulating layer (B0 & 4) to connect the second wiring layer (53) and the through-via (32) to each other, the connection via (65) being in contact (electrical contact) with the through-via (32; see fig. 1), wherein the first insulating layer (B21; first insulating layer made of epoxy resin and inorganic filler discussed in above) includes an insulating material different from an insulating material of the second insulating layer (B0 & 4 made of epoxy resin with acid anhydride as discussed above).
Muramatsu fails to teach the connection via being in physical contact with the through-via.
Tanaka teaches a printed circuit board (figs. 1A-1B, 10 [paragraph 0018] Tanaka states, “wiring substrate 10”) wherein a connection via (57 [paragraph 0047] Tanaka states, “a via wire 57”) being in physical contact ([paragraph 0104] Tanaka states, “the via wire 57 is directly stacked on the upper end surface 42A of the via wire 42”) with a through-via (42 [paragraph 0057] Tanaka states, “via wire 42”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the printed circuit board having a connection via being in electrical contact with the through via as taught by Muramatsu with the connection via being in physical contact with the through-via without a pad/land therebetween as taught by Tanaka because Tanaka states, “ there is no wiring layer formed integrally with the via wire 42 on the upper surface 41A of the insulation layer 41. When a wiring layer covers the glass cloth 41G exposed on the upper surface 41A of the insulation layer 41, the wiring may short-circuit. To avoid such short-circuiting of the wiring, no wiring layer is formed on the upper surface 41A of the insulation layer 41” [paragraph 0104].
Regarding claim 3 – Muramatsu in view of Tanaka teach the printed circuit board of claim 1, further comprising: one or more third insulating layers (Muramatsu; fig. 1, B12-B14) disposed on the second insulating layer (B0 & 4), the one or more third insulating layers (B12-B14) covering at least a portion of the second wiring layer (layer 53 shown on layer B11); and one or more third wiring layers (layer 53 on the third insulating layer B12) respectively disposed on or within the third insulating layers (B12-B14; see fig. 1).
Regarding claim 4 – Muramatsu in view of Tanaka teach the printed circuit board of claim 3, further comprising: one or more fourth insulating layers (Muramatsu; fig. 1, B22-B23) disposed on the first insulating layer (B21); and one or more fourth wiring layers (wiring 53 shown in fourth wiring layer B22/B23) respectively disposed on or within the fourth insulating layers (B22/B23; claimed structure shown in figure 1).
Regarding claim 7 – Muramatsu in view of Tanaka teach the printed circuit board of claim 4, wherein the number of the third insulating layers (Muramatsu; fig. 1, B12, B13, B14) is different (three layers vs two layers) from the number of the fourth insulating layers (B22, B23).
Regarding claim 8 – Muramatsu in view of Tanaka teach the printed circuit board of claim 7, wherein the number of the third insulating layers (Muramatsu; fig. 1, B12, B13, B14) is greater (three layers vs two layers) than the number of the fourth insulating layers (B22, B23).
Regarding claim 12 – Muramatsu in view of Tanaka teach the printed circuit board of claim 1, further comprising: a core (Muramatsu; fig. 1, 2 [paragraph 0120] Muramatsu states, “core body 1”) having a through-hole (25 [paragraph 0120] Muramatsu states, “a sub-core accommodation space (through-hole) 25”), wherein the glass layer (33) is disposed in the through-hole (25 [paragraph 0120] Muramatsu states, “A plate-like ceramic sub-core 3 is accommodated in the sub-core accommodation space 25”).
Regarding claim 13 – Muramatsu in view of Tanaka teach the printed circuit board of claim 1, further comprising: a first wiring layer (Muramatsu; fig. 1, lower wiring layer 31 [paragraph 0123] Muramatsu states, “metallization pads 31”) disposed on and in contact with the first surface of the glass layer (33, claimed structure shown in figure 1), wherein the first insulating layer (B21) covers the first wiring layer (31), the first wiring layer (fig. 1, lower wiring layer on the component 3 including layers 31 and 39) includes a first metal layer (31 [paragraph 0124] Muramatsu states, “the dam metallization layers 39 are Ni or Ag-based metals. The surfaces of the metallization pads 31 and the dam metallization layers 39 are plated with Cu”) and a second metal layer (39) disposed on the first metal layer (31), and at least a portion of the first metal layer (31) covers a lower surface of the through-via (32).
Regarding claim 14 – Muramatsu in view of Tanaka teach a printed circuit board (Muramatsu; fig. 1, 1A [paragraph 0117] Muramatsu states, “wiring board 1A”) comprising: a glass layer (33 [paragraph 0124] Muramatsu states, “the ceramic layers 33 are alumina, silicon nitride, aluminum nitride, and glass ceramics produced by adding an inorganic filler such as borosilicate glass or borosilicate lead glass”) having a first surface (lower surface of component 3), and a second surface (top surface of component 3) opposing the first surface; a through-via (32 [paragraph 0122] Muramatsu states, “penetration conductors 32”) penetrating the glass layer (33); a first wiring layer (lower wiring layers 31 & 39 [paragraph 0123] Muramatsu states, “metallization pads 31”) disposed on the first surface of the glass layer (33; claimed structure shown in figure 1), the first wiring layer (31 & 39) having an interface with the through-via (32), the first wiring layer (31 & 39 [paragraph 0124] Muramatsu states, “the dam metallization layers 39 are Ni or Ag-based metals. The surfaces of the metallization pads 31 and the dam metallization layers 39 are plated with Cu”) including a first metal layer (31) and a second metal layer (39) disposed on the first metal layer (31); a first insulating layer (B21 [0129] Muramatsu states, “B21-B24 are basically made of a resin material such as an epoxy resin and contain an appropriate amount of inorganic filler such as a silica powder for adjustment of the dielectric constant or the dielectric breakdown voltage”) disposed on the first surface and covering the first wiring layer (lower wiring layer 31/39; claimed structure shown in figure 1); a second insulating layer (B0 & 4 [paragraph 0128] Muramatsu states, “The groove-filling portion 4 and the lowest resin insulating layer B0 may be made of a resin produced by adding acid anhydride to an epoxy resin”) disposed on the second surface (top surface of element 3) of the glass layer (33) and covering a side surface of the glass layer (33) connecting the first surface and the second surface of the glass layer (claimed structure shown in figure 1), the second insulating layer (B0 & 4) being in contact with a portion of the first insulating layer (B21); a second wiring layer (wirings 53 shown on surface of B11 [paragraph 0135] Muramatsu states, “CU-plating-formed interconnections 51 and 53”) disposed on the second insulating layer (B0 & 4); and a connection via (65 [paragraph 0136] Muramatsu states, “via conductors 65”) penetrating the second insulating layer (B0 & 4) to connect the second wiring layer (53) and the through-via (32) to each other (see fig. 1), wherein at least a portion of the first metal layer (31) is in contact with the through-via (32) and extends onto the first surface (claimed structure shown in figure 1).
Muramatsu fails to teach wherein the connection via being in physical contact with the through-via.
Tanaka teaches a printed circuit board (figs. 1A-1B, 10 [paragraph 0018] Tanaka states, “wiring substrate 10”) wherein a connection via (57 [paragraph 0047] Tanaka states, “a via wire 57”) being in physical contact ([paragraph 0104] Tanaka states, “the via wire 57 is directly stacked on the upper end surface 42A of the via wire 42”) with a through-via (42 [paragraph 0057] Tanaka states, “via wire 42”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the printed circuit board having a connection via being in electrical contact with the through via as taught by Muramatsu with the connection via being in physical contact with the through-via without a pad/land therebetween as taught by Tanaka because Tanaka states, “ there is no wiring layer formed integrally with the via wire 42 on the upper surface 41A of the insulation layer 41. When a wiring layer covers the glass cloth 41G exposed on the upper surface 41A of the insulation layer 41, the wiring may short-circuit. To avoid such short-circuiting of the wiring, no wiring layer is formed on the upper surface 41A of the insulation layer 41” [paragraph 0104].
Regarding claim 16 – Muramatsu in view of Tanaka teach the printed circuit board of claim 14, wherein the first insulating layer (Muramatsu; fig. 1, B21) includes an insulating material (epoxy resin as discussed in the rejection to claim 14 above) different from an insulating material (epoxy resin with acid anhydride as discussed in the rejection to claim 14 above) of the second insulating layer (B0 & 4).
Regarding claim 17 – Muramatsu in view of Tanaka teach the printed circuit board of claim 14, wherein the first metal layer (Muramatsu; fig. 1, 31) and the second metal layer (39) include the same metal ([paragraph 0124] Muramatsu states, “Examples of the metal material of the metallization pads 31, the penetration conductors 32, the electrode conductor layers 36 and 37, and the dam metallization layers 39 are Ni or Ag-based metals”).
Regarding claim 18 – Muramatsu in view of Tanaka teach the printed circuit board of claim 14, wherein the first metal layer (Muramatsu; fig. 1, 31) includes a layer, and the second metal layer (39) includes layer formed using the first metal layer (31) as a seed (claimed structure shown in figure 1).
Muramatsu in view of Tanaka does not explicitly teach electroless plating or electrolytic plating.
In accordance to MPEP 2113, the method of forming the device is not germane to the issue of patentability of the device itself. Therefore, this limitation has not been given patentable weight. Please note that even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product, i.e. “first and second metal layers”, does not depend on its method of production, i.e. “electroless plating” and “electrolytic plating”. In re Thorpe, 227 USPQ 964, 966 (Federal Circuit 1985).
Regarding claim 19 – Muramatsu in view of Tanaka teach the printed circuit board of claim 14, wherein the first metal layer (Muramatsu; fig. 1, 31) includes a metal foil (metal layer 31 is considered “a metal foil”) or a copper foil.
Regarding claim 20 – Muramatsu in view of Tanaka teach the printed circuit board of claim 1, wherein the through-via (Muramatsu; fig. 1, 32) is in direct contact with the first wiring layer (lower wiring layer 31).
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Muramatsu et al. in view of Tanaka et al. as applied to claim 1 above, and further in view of Kim (US PG. Pub. 2022/0078907).
Regarding claim 2 – Muramatsu in view of Tanaka teach the printed circuit board of claim 1, wherein the first insulating layer (Muramatsu; fig. 1, B21) and the second insulating layer (B0 & 4) respectively include a filler ([paragraph 0130] Muramatsu states, “the groove-filling portion 4 and the lowest resin insulating layer B0 are basically made of the same epoxy resin as the resin insulating layers B11-B14 and B21-B24, their linear expansion coefficients are adjusted by changing the contents of the inorganic filler. That is, the groove-filling portion 4 and the lowest resin insulating layer B0 are higher in filler content and hence have a smaller linear expansion coefficient than the resin insulating layers B11-B14 and B21-B24”).
Muramatsu in view of Tanaka fail to explicitly teach wherein the second insulating layer includes the filler finer than the filter included in the first insulating layer.
Kim teaches wherein the second insulating layer (fig. 1, 12 [paragraph 0023] Kim states, “first to third resin layers 10, 12, and 14”) includes the filler (22 [paragraph 0020] Kim states, “A diameter of each of the first fillers 20 may be greater than a diameter of each of the second fillers 22”) finer than the filler (20) included in the first insulating layer (10).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the printed circuit board having a filler in each of the first and second insulating layer as taught by Muramatsu in view of Tanaka with the filler in the second insulating layer being finer than that of the filler in the first insulating layer as taught by Kim because Kim states, “the insulation structure may include fillers of different sizes, thereby having a low coefficient of thermal expansion (CTE), a high glass transition temperature (Tg), a high elastic modulus, low dielectric loss, and a high copper foil adhesion strength.” [paragraph 0113].
Claim(s) 5-6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Muramatsu et al. in view of Tanaka et al. as applied to claim 4 above, and further in view of Lee et al. (US PG. Pub. 2014/0182895).
Regarding claim 5 – Muramatsu in view of Tanaka teach the printed circuit board of claim 4, but fails to explicitly teach wherein the number of the third wiring layers is different from the number of the fourth wiring layers.
Lee teaches wherein the number of the third wiring layers (fig. 4, see wirings P2, P4 [paragraph 0071] Lee states, “circuit pattern layer P2…circuit pattern layer P4” ) is different from the number of the fourth wiring layers (P1 [paragraph 0072] Lee states, “circuit pattern layer P1”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the printed circuit board having third and fourth wiring layers on the third and fourth insulating layers as taught by Muramatsu in view of Tanaka with the third wiring layers being different from the number of fourth wiring layers as taught by Lee because wiring density/layering can be implemented in required/desired areas of the PCB and allows for an asymmetric layer layout.
Regarding claim 6 – Muramatsu in view of Tanaka and Lee teach the printed circuit board of claim 5, wherein the number of the third wiring layers (Lee; fig. 4, P2 & P4) is greater than the number of the fourth wiring layers (P1).
Claim(s) 9-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Muramatsu et al. in view of Tanaka et al. as applied to claim 3 above, and further in view of Inagaki et al. (US PG. Pub. 2016/0064318).
Regarding claim 9 – Muramatsu in view of Tanaka teach the printed circuit board of claim 3, further comprising: a first wiring layer (Muramatsu; fig. 1, lower wiring layer 31 [paragraph 0123] Muramatsu states, “metallization pads 31”) disposed on and in contact with the first surface (bottom surface) of the glass layer (33), wherein the first insulating layer (B21) covers the first wiring layer (lower wiring layer 31; claimed structure shown in figure 1).
Muramatsu in view of Tanaka fail to teach wherein an average pitch of an interconnection included in the same third wiring layer among the one or more third insulating layers is shorter than an average pitch of an interconnection included in the first wiring layer.
Inagaki teaches a printed circuit board (fig. 1, 10) wherein an average pitch of an interconnection included in the same third wiring layer (158Fa) among the one or more third insulating layers (150Fa) is shorter ([paragraph 0038] Inagaki states, “first conductive layer (158Fa [paragraph 0047] Inagaki states, “insulating resin interlayer (150Fa)”) is set at a finer pitch than other conductive layers to increase its wiring density. Thus, the wiring width is narrow (for example, approximately 2˜11 μm, most preferably 5 μm) and wiring lines are made thin (for example, approximately 3˜11 μm, most preferably 5 μm)”) than an average pitch of an interconnection included in the first wiring layer (58S).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the printed circuit board having a third wiring layer on a third insulating layer and a first wiring layer as taught by Muramatsu in view of Tanaka with the pitch of the third wiring layer being shorter than that of the first wiring layer as taught by Inagaki because Inagaki states this will, “increase its wiring density” [paragraph 0038]. This increased density will create a space savings and reduce the size of the overall PCB.
Regarding claim 10 – Muramatsu in view of Tanaka and Inagaki teach the printed circuit board of claim 9, further comprising: one or more fourth insulating layers (Muramatsu; fig. 1, B22 & B23) disposed on the first insulating layer (B21); and one or more fourth wiring layers (wirings 53 shown on fourth insulating layers B22 and B23) respectively disposed on or within the fourth insulating layers (claimed structure shown in figure 1).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Muramatsu et al. in view of Tanaka et al. as applied to claim 1 above, and further in view of Yuri et al. (US PG. Pub. 2006/0175083).
Regarding claim 11 – Muramatsu in view of Tanaka teach the printed circuit board of claim 1, further comprising: one or more third insulating layers (Muramatsu; fig. 1, B12-B14) disposed on the second insulating layer (B0 & 4), the one or more third insulating layers (B12-B14) covering at least a portion of the second wiring layer (wiring 53 on B11); one or more third wiring layers (see wirings 53 on surface of B12-B13) respectively disposed on or within the third insulating layers (see fig. 1); one or more fourth insulating layers (B22-B23) disposed on the first insulating layer (B21); and one or more fourth wiring layers (wirings 53 on B22-B23) respectively disposed on or within the fourth insulating layers (B22-B23), wherein the third insulating layers (B12-B14) include a material substantially the same as an insulating material of the first insulating layer (B21).
Muramatsu fails to teach wherein the fourth insulating layers include a material substantially the same as an insulating material of the second insulating layer.
Yuri teaches a printed circuit board (fig. 4, 200) wherein the fourth insulating layers (lowermost layer 102 [paragraph 0110] Yuri states, “the dielectric layer 102 is made of an epoxy resin”) include a material substantially the same as an insulating material of the second insulating layer (layer 102 on upper surface of layer 100 and element 55 [paragraph 0125] Yuri states, “the gap therebetween was filled with epoxy resin so as to form the filling coupled portion 55”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the printed circuit board having a fourth insulating layer and second insulating layer as taught by Muramatsu with the fourth and second insulating layer being made of substantially the same insulating material as taught by Yuri because Yuri states, “The filling coupled portion 55 affixes the sub-core portion 1 to the main core body 100m, and absorbs any difference in the linear coefficient of expansion in the in-plane direction (i.e., the horizontal direction as viewed in FIG. 4) and the thickness (vertical) direction between the sub-core portion 1 and the main core body 100m, by means of the elastic deformation of portion 55” [paragraph 0106]. This similar material can prevent warpage of the printed circuit board.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Muramatsu et al. in view of Tanaka et al. as applied to claim 14 above, and further in view of Fushie et al. (US PG. Pub. 2006/0201818).
Regarding claim 15 – Muramatsu in view of Tanaka teach the printed circuit board of claim 14, but fails to teach wherein the connection via includes a third metal layer and a fourth metal layer disposed on the third metal layer, and the third metal layer covers at least a portion of the through-via.
Fushie teaches wherein the connection via (fig. 1, 5 [paragraph 0040] Fushie states, “copper film layer 5”) includes a third metal layer (5a [paragraph 0066] Fushie states, “electroless plating copper layer 5a”) and a fourth metal layer (5b [paragraph 0068] Fushie states, “electrolytic plating copper layer 5b”) disposed on the third metal layer (5a), and the third metal layer (5a) covers at least a portion of the through-via (3 [paragraph 0040] Fushie states, “through-hole 3”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to modify the connection via as taught by Muramatsu in view of Tanaka with the connection via including a third and fourth metal layer as taught by Fushie because electroless plating (the third metal layer) will improve adhesion between the glass substrate and the fourth metal layer.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lin et al. (US PG. Pub. 2017/0018505) discloses a wiring board with embedded components.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN T SAWYER whose telephone number is (571)270-5469. The examiner can normally be reached M-F 8:30 am - 5pm.
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/STEVEN T SAWYER/Primary Examiner, Art Unit 2847