DETAILED ACTION
This action is in response to the application filed 02/16/2024. Claims 1-20 are pending and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The disclosure is objected to because of the following informalities:
In order to keep consistency, “a quantum computing device with a high queueing delay” in paragraph 0062 should read “a quantum computer device with a high queuing delay”.
Appropriate correction is required.
Claim Objections
Claims 2, 4, 6, 11, and 18 are objected to because of the following informalities:
Regarding claim 2, the Examiner respectfully notes that claim 2 is a method claim and the limitation of “in response to determining to utilize parallelization, identifying a parallelization type based on the quantum circuit and the one or more quantum hardware units” is a contingent limitation and therefore under the broadest reasonable interpretation these limitation may not be performed (“The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” MPEP 2111.04(II)). Accordingly the Examiner recommends the Applicant positively recite determining to utilize parallelization to avoid a contingent interpretation of these limitations.
In order to keep consistency, “queueing delay” in claims 4, 11, and 18 should read “queuing delay”
Regarding claim 6, the Examiner respectfully notes that claim 6 is a method claim and the limitation of “wherein the parallelization type comprises intra-device parallelization and inter-device parallelization” is a contingent limitation and therefore under the broadest reasonable interpretation these limitation may not be performed (“The broadest reasonable interpretation of a method (or process) claim having contingent limitations requires only those steps that must be performed and does not include steps that are not required to be performed because the condition(s) precedent are not met.” MPEP 2111.04(II)). Accordingly the Examiner recommends the Applicant positively recite determining to utilize parallelization to avoid a contingent interpretation of these limitations.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 6, 13, and 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 6, claim 6 recites “wherein the parallelization type comprises intra-device parallelization and inter-device parallelization.” Examiner notes that according to paragraphs 60-61, the selection module process determines using either intra-device or inter-device parallelization. Thus, it is unclear as to how the parallelization type comprises both intra-device parallelization and inter-device parallelization. For purposes of examination, Examiner has interpreted “wherein the parallelization type comprises intra-device parallelization and inter-device parallelization” to be “wherein the parallelization type comprises intra-device parallelization or inter-device parallelization.”
Regarding claim 13, claim 13 recites “wherein the parallelization type comprises intra-device parallelization and inter-device parallelization.” Examiner notes that according to paragraphs 60-61, the selection module process determines using either intra-device or inter-device parallelization. Thus, it is unclear as to how the parallelization type comprises both intra-device parallelization and inter-device parallelization. For purposes of examination, Examiner has interpreted “wherein the parallelization type comprises intra-device parallelization and inter-device parallelization” to be “wherein the parallelization type comprises intra-device parallelization or inter-device parallelization.”
Regarding claim 20, claim 20 recites “wherein the parallelization type comprises intra-device parallelization and inter-device parallelization.” Examiner notes that according to paragraphs 60-61, the selection module process determines using either intra-device or inter-device parallelization. Thus, it is unclear as to how the parallelization type comprises both intra-device parallelization and inter-device parallelization. For purposes of examination, Examiner has interpreted “wherein the parallelization type comprises intra-device parallelization and inter-device parallelization” to be “wherein the parallelization type comprises intra-device parallelization or inter-device parallelization.”
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 15-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because claim 15 is directed to a computer readable tangible storage medium (e.g. see claim 15, line 2), which includes a signal based on the broadest reasonable interpretation (i.e. The ordinary and customary meaning of a computer readable medium that includes signals per se). While the Specification discloses a computer readable tangible storage medium (see paragraph 0023), the Specification is not limiting the computer readable tangible storage medium to only a non-transitory embodiment. Instead, paragraph 0023 is limiting a computer readable storage medium as non-transitory, in which case a computer readable storage medium and a computer readable tangible storage medium are not the same. A computer readable tangible storage medium, or the like, that covers both transitory and non-transitory embodiments may be amended to narrow the claim to cover only statutory embodiments to avoid a rejection under 35 U.S.C 101 by either adding the limitation “non-transitory” to the claim and positively reciting that the computer readable medium is a non-transitory computer readable medium or amending the claim language to be consistent with the language in the specification. See also In re Nuijten, 500 F.3d 1346, 1356-57 (Fed. Cir. 2007) (transitory embodiments are not directed to statutory subject matter). Examiner notes that if Applicant amends to overcome the signals per se rejection, claim 15 will still be rejected under 35 U.S.C. 101.
Regarding claims 16-20, claims 16-20 are rejected for at least the same reasons as claim 15 since claims 16-20 depend on claim 15.
Claims 1-20 are rejected under 35 U.S.C. 101 because the claims are directed towards an abstract idea without significantly more.
Regarding Claim 1:
Subject Matter Eligibility Analysis Step 1:
Claim 1 recites a method and is thus a process, one of the four statutory categories of patentable subject matter.
Subject Matter Eligibility Analysis Step 2A Prong 1:
Claim 1 recites
identifying one or more quantum hardware units available to a user based on the user credentials and the quantum circuit; (This limitation is a mental process as it encompasses a human mentally determining units that are available to a user and is thus an observation.)
generating a score for an orientation of the one or more quantum hardware units and the quantum circuit using noise information and a queuing delay for the one or more quantum hardware units and a pretrained machine learning model; (This limitation is a mental process as it encompasses a human mentally creating a score for hardware units based on other information and is thus an evaluation.)
generating outputs for the orientation based on the generated scores. (This limitation is a mental process as it encompasses a human mentally creating outputs based on the mentally created scores and is thus an evaluation.)
Therefore, claim 1 recites an abstract idea.
Subject Matter Eligibility Analysis Step 2A Prong 2:
Claim 1 further recites additional elements of
a processor-implemented method (This element does not integrate the abstract idea into a practical application because it amounts to mere “apply it on a computer” (see MPEP 2106.05(f)).)
receiving a quantum circuit and one or more user credentials (This element does not integrate the abstract idea into a practical application because it recites insignificant extra-solution activity of data gathering (see MPEP 2106.05(g)).)
Therefore, claim 1 is not integrated into a practical application.
Subject Matter Eligibility Analysis Step 2B:
The additional elements of claim 1 do not provide significantly more than the abstract idea itself, taken alone and in combination because
a processor-implemented method uses a computer as a tool to perform the abstract idea and cannot provide significantly more (see MPEP 2106.05(f)).
receiving a quantum circuit and one or more user credentials is the well understood, routine, and conventional activity of “transmitting or receiving data over a network” (see MPEP 2106.05(d)(II); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network)).
Therefore, claim 1 is subject-matter ineligible.
Regarding Claim 2:
Subject Matter Eligibility Analysis Step 2A Prong 1:
Claim 2 recites
determining whether to utilize parallelization based on the quantum circuit and the one or more quantum hardware units; (This limitation is a mental process as it encompasses a human mentally determining using parallelization and is thus a judgement.)
in response to determining to utilize parallelization, identifying a parallelization type based on the quantum circuit and the one or more quantum hardware units. (This limitation is a mental process as it encompasses a human mentally determining the type of parallelization and is thus an observation.)
Therefore, claim 2 recites an abstract idea.
Subject Matter Eligibility Analysis Step 2A Prong 2:
Claim 2 does not further recite any additional elements. Therefore, claim 2 is not integrated into a practical application.
Subject Matter Eligibility Analysis Step 2B:
Since there are no additional elements, claim 2 does not provide significantly more than the abstract idea itself, taken alone and in combination. Therefore, claim 2 is subject-matter ineligible.
Regarding Claim 3:
Subject Matter Eligibility Analysis Step 2A Prong 1:
Claim 3 recites
suggests a set of quantum hardware suitable to process the quantum circuit to satisfy a threshold. (This limitation is a mental process as it encompasses a human mentally suggesting hardware that satisfies a threshold and is thus a judgment.)
Therefore, claim 3 recites an abstract idea.
Subject Matter Eligibility Analysis Step 2A Prong 2:
Claim 3 further recites additional elements of
wherein the pretrained machine learning model is trained from a previous execution history for circuits with a preconfigured number of similarities as a quantum circuit (This element does not integrate the abstract idea into a practical application because it amounts to mere “apply it on a computer” (see MPEP 2106.05(f)).)
Therefore, claim 3 is not integrated into a practical application.
Subject Matter Eligibility Analysis Step 2B:
The additional elements of claim 3 do not provide significantly more than the abstract idea itself, taken alone and in combination because
wherein the pretrained machine learning model is trained from a previous execution history for circuits with a preconfigured number of similarities as a quantum circuit uses a computer as a tool to perform the abstract idea and cannot provide significantly more (see MPEP 2106.05(f)).
Therefore, claim 3 is subject-matter ineligible.
Regarding Claim 4:
Subject Matter Eligibility Analysis Step 2A Prong 1:
Claim 4 recites
predict a quality degradation, queueing delay, running time, and classical computing overhead for each quantum hardware unit and an error mitigation technique for a particular orientation of the one or more quantum hardware units (This limitation is a mental process as it encompasses a human mentally predicting various outcomes and techniques and is thus an evaluation.)
Therefore, claim 4 recites an abstract idea.
Subject Matter Eligibility Analysis Step 2A Prong 2:
Claim 4 further recites additional elements of
wherein the pretrained machine learning model utilizes a training module (This element does not integrate the abstract idea into a practical application because it amounts to mere “apply it on a computer” (see MPEP 2106.05(f)).)
Therefore, claim 4 is not integrated into a practical application.
Subject Matter Eligibility Analysis Step 2B:
The additional elements of claim 4 do not provide significantly more than the abstract idea itself, taken alone and in combination because
wherein the pretrained machine learning model utilizes a training module uses a computer as a tool to perform the abstract idea and cannot provide significantly more (see MPEP 2106.05(f)).
Therefore, claim 4 is subject-matter ineligible.
Regarding Claim 5:
Subject Matter Eligibility Analysis Step 2A Prong 1:
Claim 5 recites
wherein the one or more outputs are selected from a group consisting of a queue time for a quantum hardware unit, a quality degradation for the quantum hardware unit, a mitigation method utilized, a run time, and classical computer overhead; (This limitation is a mental process as it encompasses a human mentally selecting an output from a group and is thus a judgement.)
Therefore, claim 5 recites an abstract idea.
Subject Matter Eligibility Analysis Step 2A Prong 2:
Claim 5 does not further recite any additional elements. Therefore, claim 5 is not integrated into a practical application.
Subject Matter Eligibility Analysis Step 2B:
Since there are no additional elements, claim 5 does not provide significantly more than the abstract idea itself, taken alone and in combination. Therefore, claim 5 is subject-matter ineligible.
Regarding Claim 6:
Subject Matter Eligibility Analysis Step 2A Prong 1:
Claim 6 recites
wherein the parallelization type comprises intra-device parallelization and inter-device parallelization. (This limitation is a mental process as it further defines the mental process of identifying a parallelization type from claim 2.)
Therefore, claim 6 recites an abstract idea.
Subject Matter Eligibility Analysis Step 2A Prong 2:
Claim 6 does not further recite any additional elements. Therefore, claim 6 is not integrated into a practical application.
Subject Matter Eligibility Analysis Step 2B:
Since there are no additional elements, claim 6 does not provide significantly more than the abstract idea itself, taken alone and in combination. Therefore, claim 6 is subject-matter ineligible.
Regarding Claim 7:
Subject Matter Eligibility Analysis Step 2A Prong 1:
Claim 7 recites the same abstract ideas as claim 1. Therefore, claim 7 recites an abstract idea.
Subject Matter Eligibility Analysis Step 2A Prong 2:
Claim 7 further recites additional elements of
executing the circuit on the orientation with the score satisfying a preconfigured threshold. (This element does not integrate the abstract idea into a practical application because it amounts to mere “apply it on a computer” (see MPEP 2106.05(f)).)
Therefore, claim 7 is not integrated into a practical application.
Subject Matter Eligibility Analysis Step 2B:
The additional elements of claim 7 do not provide significantly more than the abstract idea itself, taken alone and in combination because
executing the circuit on the orientation with the score satisfying a preconfigured threshold uses a computer as a tool to perform the abstract idea and cannot provide significantly more (see MPEP 2106.05(f)).
Therefore, claim 7 is subject-matter ineligible.
Regarding Claim 8:
Subject Matter Eligibility Analysis Step 1:
Claim 8 recites a computer system comprising one or more processors and is thus an apparatus, one of the four statutory categories of patentable subject matter.
Subject Matter Eligibility Analysis Step 2A Prong 1:
Claim 8 recites
identifying one or more quantum hardware units available to a user based on the user credentials and the quantum circuit; (This limitation is a mental process as it encompasses a human mentally determining units that are available to a user and is thus an observation.)
generating a score for an orientation of the one or more quantum hardware units and the quantum circuit using noise information and a queuing delay for the one or more quantum hardware units and a pretrained machine learning model; (This limitation is a mental process as it encompasses a human mentally creating a score for hardware units based on other information and is thus an evaluation.)
generating outputs for the orientation based on the generated scores. (This limitation is a mental process as it encompasses a human mentally creating outputs based on the mentally created scores and is thus an evaluation.)
Therefore, claim 8 recites an abstract idea.
Subject Matter Eligibility Analysis Step 2A Prong 2:
Claim 8 further recites additional elements of
A computer system, the computer system comprising: one or more processors, one or more computer-readable memories, one or more computer-readable tangible storage media, and program instructions stored on at least one of the one or more tangible storage media for execution by at least one of the one or more processors via at least one of the one or more memories, wherein the computer system is capable of performing a method comprising: (This element does not integrate the abstract idea into a practical application because it amounts to mere “apply it on a computer” (see MPEP 2106.05(f)).)
receiving a quantum circuit and one or more user credentials (This element does not integrate the abstract idea into a practical application because it recites insignificant extra-solution activity of data gathering (see MPEP 2106.05(g)).)
Therefore, claim 8 is not integrated into a practical application.
Subject Matter Eligibility Analysis Step 2B:
The additional elements of claim 8 do not provide significantly more than the abstract idea itself, taken alone and in combination because
A computer system, the computer system comprising: one or more processors, one or more computer-readable memories, one or more computer-readable tangible storage media, and program instructions stored on at least one of the one or more tangible storage media for execution by at least one of the one or more processors via at least one of the one or more memories, wherein the computer system is capable of performing a method comprising: uses a computer as a tool to perform the abstract idea and cannot provide significantly more (see MPEP 2106.05(f)).
receiving a quantum circuit and one or more user credentials is the well understood, routine, and conventional activity of “transmitting or receiving data over a network” (see MPEP 2106.05(d)(II); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network)).
Therefore, claim 8 is subject-matter ineligible.
Regarding claim 9, claim 9 recites substantially similar limitations to claim 2, and is therefore rejected under the same analysis.
Regarding claim 10, claim 10 recites substantially similar limitations to claim 3, and is therefore rejected under the same analysis.
Regarding claim 11, claim 11 recites substantially similar limitations to claim 4, and is therefore rejected under the same analysis.
Regarding claim 12, claim 12 recites substantially similar limitations to claim 5, and is therefore rejected under the same analysis.
Regarding claim 13, claim 13 recites substantially similar limitations to claim 6, and is therefore rejected under the same analysis.
Regarding claim 14, claim 14 recites substantially similar limitations to claim 7, and is therefore rejected under the same analysis.
Regarding Claim 15:
Subject Matter Eligibility Analysis Step 1:
Claim 15 recites a computer program product comprising one or more computer-readable tangible storage media and as discussed above is non-statutory subject matter. For purposes of compact prosecution, Examiner has analyzed claim 15 and its dependents under U.S.C. 101 should the applicant amend this one or more computer-readable tangible storage media to be non-transitory.
Subject Matter Eligibility Analysis Step 2A Prong 1:
Claim 15 recites
identifying one or more quantum hardware units available to a user based on the user credentials and the quantum circuit; (This limitation is a mental process as it encompasses a human mentally determining units that are available to a user and is thus an observation.)
generating a score for an orientation of the one or more quantum hardware units and the quantum circuit using noise information and a queuing delay for the one or more quantum hardware units and a pretrained machine learning model; (This limitation is a mental process as it encompasses a human mentally creating a score for hardware units based on other information and is thus an evaluation.)
generating outputs for the orientation based on the generated scores. (This limitation is a mental process as it encompasses a human mentally creating outputs based on the mentally created scores and is thus an evaluation.)
Therefore, claim 15 recites an abstract idea.
Subject Matter Eligibility Analysis Step 2A Prong 2:
Claim 15 further recites additional elements of
A computer program product, the computer program product comprising: one or more computer-readable tangible storage media and program instructions stored on at least one of the one or more tangible storage media, the program instructions executable by a processor capable of performing a method, the method comprising: (This element does not integrate the abstract idea into a practical application because it amounts to mere “apply it on a computer” (see MPEP 2106.05(f)).)
receiving a quantum circuit and one or more user credentials (This element does not integrate the abstract idea into a practical application because it recites insignificant extra-solution activity of data gathering (see MPEP 2106.05(g)).)
Therefore, claim 15 is not integrated into a practical application.
Subject Matter Eligibility Analysis Step 2B:
The additional elements of claim 15 do not provide significantly more than the abstract idea itself, taken alone and in combination because
A computer program product, the computer program product comprising: one or more computer-readable tangible storage media and program instructions stored on at least one of the one or more tangible storage media, the program instructions executable by a processor capable of performing a method, the method comprising: uses a computer as a tool to perform the abstract idea and cannot provide significantly more (see MPEP 2106.05(f)).
receiving a quantum circuit and one or more user credentials is the well understood, routine, and conventional activity of “transmitting or receiving data over a network” (see MPEP 2106.05(d)(II); OIP Techs., Inc., v. Amazon.com, Inc., 788 F.3d 1359, 1363, 115 USPQ2d 1090, 1093 (Fed. Cir. 2015) (sending messages over a network)).
Therefore, claim 15 is subject-matter ineligible.
Regarding claim 16, claim 16 recites substantially similar limitations to claim 2, and is therefore rejected under the same analysis.
Regarding claim 17, claim 17 recites substantially similar limitations to claim 3, and is therefore rejected under the same analysis.
Regarding claim 18, claim 18 recites substantially similar limitations to claim 4, and is therefore rejected under the same analysis.
Regarding claim 19, claim 19 recites substantially similar limitations to claim 5, and is therefore rejected under the same analysis.
Regarding claim 20, claim 20 recites substantially similar limitations to claim 6, and is therefore rejected under the same analysis.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Gonciulea et al. (US 12,530,607 B1) (hereafter referred to as Gonciulea) in view of Noda et al. (US 2026/0104922 A1) (hereafter referred to as Noda).
Regarding claim 1, Gonciulea teaches
A processor-implemented method, the method comprising: receiving a quantum circuit and one or more user credentials (Gonciulea, page 14, column 11, lines 12-13, “In some embodiments, one or more pre-determined quantum circuit designs may be obtained as input” and “For example, the processor 202 and communications hardware 206 may identify the set of input attributes by a user inputting a query in natural language, and the natural language may be subjected to interpretive analysis to identify the set of input attributes” (Gonciulea, page 13, column 9, lines 32-36). Examiner notes that the quantum circuit is a predetermined quantum circuit design and the user credentials are the input attributes provided by a user. );
identifying one or more quantum hardware units available to a user based on the user credentials and the quantum circuit (Gonciulea, page 14, column 12, lines 1-5, “The machine learning technique may take as input the attributes of a particular quantum circuit design and output a numerical value scoring the appropriateness of a quantum circuit design for the class of problem specified in the quantum circuit selection criteria.” Examiner notes that the appropriateness of a quantum circuit design is identifying one or more quantum hardware units available. );
generating a score for an orientation of the one or more quantum hardware units and the quantum circuit using … a pretrained machine learning model (Gonciulea, page 14, column 12, lines 1-5, “The machine learning technique may take as input the attributes of a particular quantum circuit design and output a numerical value scoring the appropriateness of a quantum circuit design for the class of problem specified in the quantum circuit selection criteria” where “The user may, after reviewing the generated quantum circuit output, provide feedback to the system to label the generated quantum circuit as acceptable or not acceptable. The user feedback may be stored in memory 204 or other storage, along with the selected quantum circuit design, where the feedback may act as a label for the selected quantum circuit design. As the number of generated quantum circuits grows, the memory 204 may collect a labeled dataset of quantum circuit designs which may be used as a factor to drive future quantum circuit selection decisions. For example, the labeled dataset may be used to train a decision tree mechanism for subsequent quantum circuit design selection” (Gonciulea, page 15, column 14, line 58 – page 16, column 15, line 3) Examiner notes that the numerical value is the score and the machine learning technique or decision tree is the pretrained machine learning model. );
and generating outputs for the orientation based on the generated scores (Gonciulea, page 17, column 17, line 61- column 18, line 9, “the quantum circuit selection circuitry may give a much stronger weight to accuracy than execution time for this particular problem, so quantum circuit design C may be given a higher score than quantum circuit design B. Thus, the quantum circuit selection circuitry in this example chooses quantum circuit design C, after comparing the scores of each of the pre-determined quantum circuit designs. Finally, the embodiment communicates with the remote quantum computer host, then the quantum circuit selection circuitry transpiles quantum circuit C and transfers the transpiled quantum circuit to the remote quantum computer with instructions and parameters for execution. The user may then review the results of the executed transpiled quantum circuit and use the results to update their set of input attributes to conduct further experimentation.” Examiner notes that the outputs are the selected quantum circuit and instructions for the user to review.).
Gonciulea does not explicitly teach noise information and a queuing delay, but Noda does teach
generating a score for an orientation of the one or more quantum hardware units and the quantum circuit using noise information and a queuing delay for the one or more quantum hardware units and a pretrained machine learning model (Noda, page 29, paragraph 0085, “Further, when selecting qubits for executing a job, variations in error among qubits need to be taken into account. Specifically, when a quantum circuit is executed on a QPU, an error may occur in the computation result due to the influence of various types of noise. The frequency and magnitude of error differ for each qubit” where “it is more efficient to execute the job J1 singly and then execute the job J3 singly. In this case, the job J3 is executed immediately after entering the execution queue, without any waiting time. Note that the purpose of parallel execution is to shorten the queue waiting time. However, if no waiting time occurs, there is no point in performing parallel execution. If the parallel execution is uselessly performed, the accuracy decreases due to differences in the error rate among qubits and the influence of crosstalk. Therefore, from the viewpoint of accuracy, it is preferable to perform single execution” (Noda, page 31, paragraph 0114) and “the accuracy refers to a low error rate” (Noda, page 30, paragraph 0102). Examiner notes that the accuracy is the score and the queuing delay is the queue waiting time. )
Gonciulea and Noda are considered analogous to the claimed invention because they both select quantum circuits or jobs to execute . It would have been obvious to one having ordinary skill in the art prior to the effective filing date to have modified Gonciulea to use the noise information and queuing delay like in Noda. Doing so is advantageous because “the accuracy of determining whether immediate execution is possible is improved” (Noda, page 27, paragraph 0055).
Regarding claim 2, Gonciulea in view of Noda teaches the method of claim 1. Gonciulea in view of Noda further teaches
determining whether to utilize parallelization based on the quantum circuit and the one or more quantum hardware units (Noda, page 31, paragraph 0108, FIG. 8 illustrates an example of quantum multiprogramming performed on the user side. For example, it is assumed that a user generates five jobs J1 to J5 using his/her own terminal device 401. The terminal device 401 determines a combination of jobs that are executable in parallel and groups these jobs into a single job.” Examiner notes that determining a combination of jobs that are executable in parallel is determining whether to utilize parallelization.);
and in response to determining to utilize parallelization, identifying a parallelization type based on the quantum circuit and the one or more quantum hardware units (Noda, page 31, paragraph 0111, “In the case where parallelization is performed on the user side as described above, jobs to be executed in parallel need to wait for completion of preprocessing on all the jobs. For this reason, the quantum computing system 300 is not able to exhibit sufficient efficiency as a whole. More specifically, jobs need to be preprocessed before execution. In the case where jobs are parallelized on the user side, the terminal device 401 determines a combination of jobs to be executed in parallel, performs part of the preprocessing (for example, the above-described processes (a) to (c)), and then transmits the jobs to the classical computer 100” and “for example, it is assumed that the job J1 and the job J3 are grouped together and executed in parallel as a single job” (Noda, page 31, paragraph 0113). Examiner notes that after parallelization is performed, the parallelization type is the jobs being grouped as a single job. ).
Gonciulea and Noda are considered analogous to the claimed invention because they both select quantum circuits or jobs to execute. It would have been obvious to one having ordinary skill in the art prior to the effective filing date to have modified Gonciulea to use parallelization like in Noda. Doing so is advantageous because “the purpose of parallel execution is to shorten the queue waiting time” (Noda, page 31, paragraph 0114).
Regarding claim 3, Gonciulea in view of Noda teaches the method of claim 1. Gonciulea in view of Noda further teaches
wherein the pretrained machine learning model is trained from a previous execution history for circuits with a preconfigured number of similarities as a quantum circuit and suggests a set of quantum hardware suitable to process the quantum circuit to satisfy a threshold (Gonciulea, page 15, column 14, line 58 – page 16, column 15, line 3, “The user may, after reviewing the generated quantum circuit output, provide feedback to the system to label the generated quantum circuit as acceptable or not acceptable. The user feedback may be stored in memory 204 or other storage, along with the selected quantum circuit design, where the feedback may act as a label for the selected quantum circuit design. As the number of generated quantum circuits grows, the memory 204 may collect a labeled dataset of quantum circuit designs which may be used as a factor to drive future quantum circuit selection decisions. For example, the labeled dataset may be used to train a decision tree mechanism for subsequent quantum circuit design selection” where “Using the scores assigned to the quantum circuit designs, the quantum circuit selection circuitry 208 may select multiple quantum circuit designs based on a threshold score. Any quantum circuit designs with a score above the threshold score may then be chosen” (Gonciulea, page 16, column 15, lines 13-17). Examiner notes that the pretrained machine learning model is the machine learning technique of a decision tree mechanism. Examiner further notes that the preconfigured number of similarities is the user accepting the generated circuit. Examiner additionally notes that the decision tree selecting circuits based on a threshold is the pretrained machine learning model suggesting quantum hardware to the user which has to satisfy a threshold.).
Regarding claim 4, Gonciulea in view of Noda teaches the method of claim 1. Gonciulea in view of Noda further teaches
wherein the pretrained machine learning model utilizes a training module to predict a quality degradation, queueing delay, running time, and classical computing overhead for each quantum hardware unit and an error mitigation technique for a particular orientation of the one or more quantum hardware units (Noda, page 31, paragraph 0120, “As the quantum multiprogramming, for example, the classical computer 100 first predicts the execution time of each of the jobs J1 to J4. Next, based on information including the execution times and the numbers of qubits to be used, the classical computer 100 determines an optimal execution order that minimizes the time slice numbers, using a bin packing algorithm” where “by predicting the preprocessing times and the job execution times of jobs, the classical computer 100 is able to more effectively avoid the conflict with the subsequent jobs with respect to the utilized qubits” (Noda, page 32, paragraph 0131) where “For a job for which the preprocessing has not yet started, the predicted time to preprocessing completion is obtained by adding the waiting time until the execution start of the preprocessing for that job to the time needed for the preprocessing. The waiting time until the execution start of the preprocessing is calculated based on, for example, the preprocessing times of preceding jobs registered before the job in the preprocessing completion waiting queue” (Noda, page 34, paragraph 0175) and “In the case of using the ‘fourth criterion’ related to the predicted output reliability of an output result, the classical computer 100 calculates the predicted output reliability of a job for each qubit region in order to ensure the accuracy of the output result of the job. Then, the classical computer 100 selects qubits to be used for the execution of the next job so that the reliability satisfies a criterion” (Noda, page 32, paragraph 0133) and “the execution job selection unit 180 calculates the predicted output reliability (a value reflecting the accuracy of the output result) for the job under examination” (Noda, page 37, paragraph 0224) where “for example, the execution job selection unit 180 compares the predicted output reliability obtained in the case of using a region with the smallest error rate (in the case where parallel execution is not performed) with the predicted output reliability obtained in the case where parallel execution is performed. If the reduction in the reliability is less than or equal to a predetermined threshold, the execution job selection unit 180 determines that the job under examination satisfies the ‘fourth criterion’ as to whether a job under examination is suitable as the next job” (Noda, page 37, paragraph 0225) and where “the preprocessing time may be predicted using, for example, a trained regression model. For example, the classical computer 100 creates, in advance, a regression model that predicts preprocessing time. Training data used for training the regression model is prepared by, for example, generating a large number of quantum circuits as follows” (Noda page 34, paragraph 0160). Examiner notes that the pretrained machine learning model is the machine learning model and the training module is the quantum circuits. The quality degradation is the output reliability. The queueing delay is the preprocessing times which includes the waiting queue time. The running time and the classical computing overhead is the execution times. The hardware units are the quantum circuits and jobs Examiner lastly notes that the error mitigation technique is comparing the output reliability with the smallest error rate with the output reliability where parallel execution is performed and comparing the reduction in reliability to a threshold. ).
Gonciulea and Noda are considered analogous to the claimed invention because they both select quantum circuits or jobs to execute. It would have been obvious to one having ordinary skill in the art prior to the effective filing date to have modified Gonciulea to predict quality degradation, queuing delay, running time, overhead, and error mitigation technique like in Noda. Doing so is advantageous because “the accuracy of determining whether immediate execution is possible is improved” (Noda, page 27, paragraph 0055).
Regarding claim 5, Gonciulea in view of Noda teaches the method of claim 1. Gonciulea in view of Noda further teaches
wherein the one or more outputs are selected from a group consisting of a queue time for a quantum hardware unit, a quality degradation for the quantum hardware unit, a mitigation method utilized, a run time, and classical computer overhead (Gonciulea, page 17, column 17, line 46- column 18, line 9, “The embodiment may then interpret the input to form a set of input attributes, and then may generate a set of selection criteria that comprises (i) a normal distribution should be represented in a quantum state prepared by the quantum circuit, (ii) an execution time between three to six second is permissible, (iii) 12 qubits are needed to store the desired quantum state, (iv) a device with quantum volume of at least 128 is needed to store the desired quantum state, and (v) an accuracy in the range of 10-3 to 10-6 is required. The quantum circuit selection circuitry may then consider three pre-determined quantum circuit designs, A, B, and C. Quantum circuit design A may require eight seconds to execute, so it is automatically assigned a score of zero. Quantum circuit design B may be able to execute in three seconds, but has accuracy of 10-3. Quantum circuit design C may be able to execute in four seconds, but has accuracy of 10-5. The quantum circuit selection circuitry may give a much stronger weight to accuracy than execution time for this particular problem, so quantum circuit design C may be given a higher score than quantum circuit design B. Thus, the quantum circuit selection circuitry in this example chooses quantum circuit design C, after comparing the scores of each of the pre-determined quantum circuit designs. Finally, the embodiment communicates with the remote quantum computer host, then the quantum circuit selection circuitry transpiles quantum circuit C and transfers the transpiled quantum circuit to the remote quantum computer with instructions and parameters for execution. The user may then review the results of the executed transpiled quantum circuit and use the results to update their set of input attributes to conduct further experimentation.” Examiner notes that the outputs are the selected quantum circuit and instructions for the user to review. Examiner further notes that the selected quantum circuit was selected based on execution time or run time. Thus, the outputs of the selected quantum circuit are selected from a group consisting of a run time.).
Regarding claim 6, Gonciulea in view of Noda teaches the method of claim 2. Gonciulea in view of Noda further teaches
wherein the parallelization type comprises intra-device parallelization and inter-device parallelization (Noda, page 31, paragraph 0111, “In the case where parallelization is performed on the user side as described above, jobs to be executed in parallel need to wait for completion of preprocessing on all the jobs. For this reason, the quantum computing system 300 is not able to exhibit sufficient efficiency as a whole. More specifically, jobs need to be preprocessed before execution. In the case where jobs are parallelized on the user side, the terminal device 401 determines a combination of jobs to be executed in parallel, performs part of the preprocessing (for example, the above-described processes (a) to (c)), and then transmits the jobs to the classical computer 100” and “for example, it is assumed that the job J1 and the job J3 are grouped together and executed in parallel as a single job” (Noda, page 31, paragraph 0113). Examiner notes that after parallelization is performed, the parallelization type is the jobs being grouped as a single job. Examiner further notes that according to paragraph 0071 which states “intra-device parallelization may relate to the accommodation of multiple circuits on a single hardware device”, grouping the jobs together to be processed as a single job is intra-device parallelization under broadest reasonable interpretation. According to the 112(b) rejection above, parallelization type comprises either intra-device or inter device parallelization.).
Gonciulea and Noda are considered analogous to the claimed invention because they both select quantum circuits or jobs to execute. It would have been obvious to one having ordinary skill in the art prior to the effective filing date to have modified Gonciulea to use parallelization like in Noda. Doing so is advantageous because “the purpose of parallel execution is to shorten the queue waiting time” (Noda, page 31, paragraph 0114).
Regarding claim 7, Gonciulea in view of Noda teaches the method of claim 1. Gonciulea in view of Noda further teaches
executing the circuit on the orientation with the score satisfying a preconfigured threshold (Gonciulea, page 16, column 15, lines 16-21, “Any quantum circuit designs with a score above the threshold score may then be chosen. In the case that multiple quantum circuit designs are chose, the multiple chose quantum circuit designs may be passed to the quantum circuit generation circuitry 210 for generation of the quantum circuit.” Examiner notes that executing the circuit is passing it the quantum circuit generation circuitry.).
Regarding claim 8, Gonciulea teaches
A computer system, the computer system comprising: one or more processors, one or more computer-readable memories, one or more computer-readable tangible storage media, and program instructions stored on at least one of the one or more tangible storage media for execution by at least one of the one or more processors via at least one of the one or more memories, wherein the computer system is capable of performing a method comprising (Gonciulea, page 11, column 6, lines 37-61, The processor 202 may be configured to execute software instructions stored in the memory 204 or otherwise accessible to the processor ( e.g., software instructions stored on a separate storage device 106, as illustrated in FIG. 1). In some cases, the processor may be configured to execute hard-coded functionality. As such, whether configured by hardware or software methods, or by a combination of hardware with software, the processor 202 represent an entity (e.g., physically embodied in circuitry) capable of performing operations according to various embodiments of the present invention while configured accordingly. Alternatively, as another example, when the processor 202 is embodied as an executor of software instructions, the soft- ware instructions may specifically configure the processor 202 to perform the algorithms and/or operations described herein when the software instructions are executed. Memory 204 is non-transitory and may include, for example, one or more volatile and/or non-volatile memories. In other words, for example, the memory 204 may be an electronic storage device (e.g., a computer readable storage medium). The memory 204 may be configured to store information, data, content, applications, software instructions, or the like, for enabling the apparatus to carry out various functions in accordance with example embodiments contemplated herein.):
receiving a quantum circuit and one or more user credentials (Gonciulea, page 14, column 11, lines 12-13, “In some embodiments, one or more pre-determined quantum circuit designs may be obtained as input” and “For example, the processor 202 and communications hardware 206 may identify the set of input attributes by a user inputting a query in natural language, and the natural language may be subjected to interpretive analysis to identify the set of input attributes” (Gonciulea, page 13, column 9, lines 32-36). Examiner notes that the quantum circuit is a predetermined quantum circuit design and the user credentials are the input attributes provided by a user. );
identifying one or more quantum hardware units available to a user based on the user credentials and the quantum circuit (Gonciulea, page 14, column 12, lines 1-5, “The machine learning technique may take as input the attributes of a particular quantum circuit design and output a numerical value scoring the appropriateness of a quantum circuit design for the class of problem specified in the quantum circuit selection criteria.” Examiner notes that the appropriateness of a quantum circuit design is identifying one or more quantum hardware units available. );
generating a score for an orientation of the one or more quantum hardware units and the quantum circuit using … a pretrained machine learning model (Gonciulea, page 14, column 12, lines 1-5, “The machine learning technique may take as input the attributes of a particular quantum circuit design and output a numerical value scoring the appropriateness of a quantum circuit design for the class of problem specified in the quantum circuit selection criteria” where “The user may, after reviewing the generated quantum circuit output, provide feedback to the system to label the generated quantum circuit as acceptable or not acceptable. The user feedback may be stored in memory 204 or other storage, along with the selected quantum circuit design, where the feedback may act as a label for the selected quantum circuit design. As the number of generated quantum circuits grows, the memory 204 may collect a labeled dataset of quantum circuit designs which may be used as a factor to drive future quantum circuit selection decisions. For example, the labeled dataset may be used to train a decision tree mechanism for subsequent quantum circuit design selection” (Gonciulea, page 15, column 14, line 58 – page 16, column 15, line 3) Examiner notes that the numerical value is the score and the machine learning technique or decision tree is the pretrained machine learning model. );
and generating outputs for the orientation based on the generated scores (Gonciulea, page 17, column 17, line 61- column 18, line 9, “the quantum circuit selection circuitry may give a much stronger weight to accuracy than execution time for this particular problem, so quantum circuit design C may be given a higher score than quantum circuit design B. Thus, the quantum circuit selection circuitry in this example chooses quantum circuit design C, after comparing the scores of each of the pre-determined quantum circuit designs. Finally, the embodiment communicates with the remote quantum computer host, then the quantum circuit selection circuitry transpiles quantum circuit C and transfers the transpiled quantum circuit to the remote quantum computer with instructions and parameters for execution. The user may then review the results of the executed transpiled quantum circuit and use the results to update their set of input attributes to conduct further experimentation.” Examiner notes that the outputs are the selected quantum circuit and instructions for the user to review.).
Gonciulea does not explicitly teach noise information and a queuing delay, but Noda does teach
generating a score for an orientation of the one or more quantum hardware units and the quantum circuit using noise information and a queuing delay for the one or more quantum hardware units and a pretrained machine learning model (Noda, page 29, paragraph 0085, “Further, when selecting qubits for executing a job, variations in error among qubits need to be taken into account. Specifically, when a quantum circuit is executed on a QPU, an error may occur in the computation result due to the influence of various types of noise. The frequency and magnitude of error differ for each qubit” where “it is more efficient to execute the job J1 singly and then execute the job J3 singly. In this case, the job J3 is executed immediately after entering the execution queue, without any waiting time. Note that the purpose of parallel execution is to shorten the queue waiting time. However, if no waiting time occurs, there is no point in performing parallel execution. If the parallel execution is uselessly performed, the accuracy decreases due to differences in the error rate among qubits and the influence of crosstalk. Therefore, from the viewpoint of accuracy, it is preferable to perform single execution” (Noda, page 31, paragraph 0114) and “the accuracy refers to a low error rate” (Noda, page 30, paragraph 0102). Examiner notes that the accuracy is the score and the queuing delay is the queue waiting time. )
Gonciulea and Noda are considered analogous to the claimed invention because they both select quantum circuits or jobs to execute . It would have been obvious to one having ordinary skill in the art prior to the effective filing date to have modified Gonciulea to use the noise information and queuing delay like in Noda. Doing so is advantageous because “the accuracy of determining whether immediate execution is possible is improved” (Noda, page 27, paragraph 0055).
Regarding claim 9, claim 9 recites substantially similar limitations to claim 2, and is therefore rejected under the same analysis.
Regarding claim 10, claim 10 recites substantially similar limitations to claim 3, and is therefore rejected under the same analysis.
Regarding claim 11, claim 11 recites substantially similar limitations to claim 4, and is therefore rejected under the same analysis.
Regarding claim 12, claim 12 recites substantially similar limitations to claim 5, and is therefore rejected under the same analysis.
Regarding claim 13, claim 13 recites substantially similar limitations to claim 6, and is therefore rejected under the same analysis.
Regarding claim 14, claim 14 recites substantially similar limitations to claim 7, and is therefore rejected under the same analysis.
Regarding claim 15, Gonciulea teaches
A computer program product, the computer program product comprising: one or more computer-readable tangible storage media and program instructions stored on at least one of the one or more tangible storage media, the program instructions executable by a processor capable of performing a method, the method comprising: (Gonciulea, page 11, column 6, lines 37-61, The processor 202 may be configured to execute software instructions stored in the memory 204 or otherwise accessible to the processor ( e.g., software instructions stored on a separate storage device 106, as illustrated in FIG. 1). In some cases, the processor may be configured to execute hard-coded functionality. As such, whether configured by hardware or software methods, or by a combination of hardware with software, the processor 202 represent an entity (e.g., physically embodied in circuitry) capable of performing operations according to various embodiments of the present invention while configured accordingly. Alternatively, as another example, when the processor 202 is embodied as an executor of software instructions, the soft- ware instructions may specifically configure the processor 202 to perform the algorithms and/or operations described herein when the software instructions are executed. Memory 204 is non-transitory and may include, for example, one or more volatile and/or non-volatile memories. In other words, for example, the memory 204 may be an electronic storage device (e.g., a computer readable storage medium). The memory 204 may be configured to store information, data, content, applications, software instructions, or the like, for enabling the apparatus to carry out various functions in accordance with example embodiments contemplated herein.):
receiving a quantum circuit and one or more user credentials (Gonciulea, page 14, column 11, lines 12-13, “In some embodiments, one or more pre-determined quantum circuit designs may be obtained as input” and “For example, the processor 202 and communications hardware 206 may identify the set of input attributes by a user inputting a query in natural language, and the natural language may be subjected to interpretive analysis to identify the set of input attributes” (Gonciulea, page 13, column 9, lines 32-36). Examiner notes that the quantum circuit is a predetermined quantum circuit design and the user credentials are the input attributes provided by a user. );
identifying one or more quantum hardware units available to a user based on the user credentials and the quantum circuit (Gonciulea, page 14, column 12, lines 1-5, “The machine learning technique may take as input the attributes of a particular quantum circuit design and output a numerical value scoring the appropriateness of a quantum circuit design for the class of problem specified in the quantum circuit selection criteria.” Examiner notes that the appropriateness of a quantum circuit design is identifying one or more quantum hardware units available. );
generating a score for an orientation of the one or more quantum hardware units and the quantum circuit using … a pretrained machine learning model (Gonciulea, page 14, column 12, lines 1-5, “The machine learning technique may take as input the attributes of a particular quantum circuit design and output a numerical value scoring the appropriateness of a quantum circuit design for the class of problem specified in the quantum circuit selection criteria” where “The user may, after reviewing the generated quantum circuit output, provide feedback to the system to label the generated quantum circuit as acceptable or not acceptable. The user feedback may be stored in memory 204 or other storage, along with the selected quantum circuit design, where the feedback may act as a label for the selected quantum circuit design. As the number of generated quantum circuits grows, the memory 204 may collect a labeled dataset of quantum circuit designs which may be used as a factor to drive future quantum circuit selection decisions. For example, the labeled dataset may be used to train a decision tree mechanism for subsequent quantum circuit design selection” (Gonciulea, page 15, column 14, line 58 – page 16, column 15, line 3) Examiner notes that the numerical value is the score and the machine learning technique or decision tree is the pretrained machine learning model. );
and generating outputs for the orientation based on the generated scores (Gonciulea, page 17, column 17, line 61- column 18, line 9, “the quantum circuit selection circuitry may give a much stronger weight to accuracy than execution time for this particular problem, so quantum circuit design C may be given a higher score than quantum circuit design B. Thus, the quantum circuit selection circuitry in this example chooses quantum circuit design C, after comparing the scores of each of the pre-determined quantum circuit designs. Finally, the embodiment communicates with the remote quantum computer host, then the quantum circuit selection circuitry transpiles quantum circuit C and transfers the transpiled quantum circuit to the remote quantum computer with instructions and parameters for execution. The user may then review the results of the executed transpiled quantum circuit and use the results to update their set of input attributes to conduct further experimentation.” Examiner notes that the outputs are the selected quantum circuit and instructions for the user to review.).
Gonciulea does not explicitly teach noise information and a queuing delay, but Noda does teach
generating a score for an orientation of the one or more quantum hardware units and the quantum circuit using noise information and a queuing delay for the one or more quantum hardware units and a pretrained machine learning model (Noda, page 29, paragraph 0085, “Further, when selecting qubits for executing a job, variations in error among qubits need to be taken into account. Specifically, when a quantum circuit is executed on a QPU, an error may occur in the computation result due to the influence of various types of noise. The frequency and magnitude of error differ for each qubit” where “it is more efficient to execute the job J1 singly and then execute the job J3 singly. In this case, the job J3 is executed immediately after entering the execution queue, without any waiting time. Note that the purpose of parallel execution is to shorten the queue waiting time. However, if no waiting time occurs, there is no point in performing parallel execution. If the parallel execution is uselessly performed, the accuracy decreases due to differences in the error rate among qubits and the influence of crosstalk. Therefore, from the viewpoint of accuracy, it is preferable to perform single execution” (Noda, page 31, paragraph 0114) and “the accuracy refers to a low error rate” (Noda, page 30, paragraph 0102). Examiner notes that the accuracy is the score and the queuing delay is the queue waiting time. )
Gonciulea and Noda are considered analogous to the claimed invention because they both select quantum circuits or jobs to execute . It would have been obvious to one having ordinary skill in the art prior to the effective filing date to have modified Gonciulea to use the noise information and queuing delay like in Noda. Doing so is advantageous because “the accuracy of determining whether immediate execution is possible is improved” (Noda, page 27, paragraph 0055).
Regarding claim 16, claim 16 recites substantially similar limitations to claim 2, and is therefore rejected under the same analysis.
Regarding claim 17, claim 17 recites substantially similar limitations to claim 3, and is therefore rejected under the same analysis.
Regarding claim 18, claim 18 recites substantially similar limitations to claim 4, and is therefore rejected under the same analysis.
Regarding claim 19, claim 19 recites substantially similar limitations to claim 5, and is therefore rejected under the same analysis.
Regarding claim 20, claim 20 recites substantially similar limitations to claim 6, and is therefore rejected under the same analysis.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Basu et al. (US 2025/0238700 A1) also discloses selecting quantum hardware with the best score.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAITLYN R LAU whose telephone number is (571)272-1429. The examiner can normally be reached Monday - Thursday: 8:00 am - 6:00 pm EST.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michelle Bechtold can be reached at (571) 431-0762. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/K.R.L./Examiner, Art Unit 2148
/PAUL M KNIGHT/Examiner, Art Unit 2148
Prosecution Insights