DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after allowance or after an Office action under Ex Parte Quayle, 25 USPQ 74, 453 O.G. 213 (Comm'r Pat. 1935). Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, prosecution in this application has been reopened pursuant to 37 CFR 1.114. Applicant's submission filed on 1/2/2026 has been entered.
Status of Claims
Claims 1-20 are pending, of which all pending claims are rejected.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 1 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out the feature "computing a parity portion based on a payload and index bits for a codeword". It is not clear or unambiguous from the claim wording alone what "index bits" refers to. There is not enough information in the claim about “index bits”. Therefore, it is unclear and indefinite. It would appear that this feature could be clarified by including the additional features of dependent claim 2 which define what index comprises. Clarification and correction is required.
Claim 10 is also rejected for similar reason as claim 1. Dependent claims 2-9 and 11-14 are also rejected due to their dependency on a rejected base claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 10-12, and 14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Laurent et al. (US 2022/0321147 A1), (hereinafter Laurent).
Regarding claim 10, Laurent teaches, a method comprising: performing error correction on a codeword using an error code correction (ECC) engine (Laurent: “To increase the reliability of the memory device 110, the memory device 110 may implement an error correction scheme to detect, identify, and correct such errors. For example, before storing a set of data bits the memory device 110 may use an error correction code to generate a codeword” [0032]); extracting index bits from the codeword; inverting a subset of the codeword based on the index bits to obtain a payload (Laurent: “To ensure that the original logic values of a balanced codeword can be accurately recovered during a subsequent read operation, the memory device 110 may explicitly or implicitly store balancing information bits that indicate which packets of the data were inverted during the balancing process. During a read operation, the memory device 110 may reference the balancing information bits so that the memory device 110 can un-invert the proper packets of the bits (e.g., those inverted during the balancing process) before data bits from the codeword are returned to a requesting device.” [0035]); and returning the payload to a host processor (Laurent: ‘the ecc decoding process to detect an error to obtain data bits or payload’; “the memory device may unbalance codeword(x, y, z) based on balancing information bits that indicate the packets (e.g., portions) of codeword(x, y, z) that were inverted during the balancing process.” [0095-0096]).
Regarding claim 11, Laurent teaches, the method of claim 10, wherein the codeword comprises an inverted payload, wherein a subset of a plurality of packets forming the codeword are inverted (Laurent: ‘the ecc decoding process to detect an error to obtain data bits or payload’; “the memory device may unbalance codeword(x, y, z) based on balancing information bits that indicate the packets (e.g., portions) of codeword(x, y, z) that were inverted during the balancing process.” [0095-0096]).
Regarding claim 12, Laurent teaches, the method of claim 11, wherein the index bits comprise quantized Knuth (QK) index bits; wherein inverting a subset of the codeword based on the QK index bits comprises inverting a first subset of successive packets of the plurality of packets based on the QK index bits (Laurent: ‘QK index bits or balancing information bits’ [0035-0036]; ‘the ecc decoding process to detect an error to obtain data bits or payload’; “the memory device may unbalance codeword(x, y, z) based on balancing information bits that indicate the packets (e.g., portions) of codeword(x, y, z) that were inverted during the balancing process.” [0095-0096]).
Regarding claim 14, Laurent teaches, the method of claim 12, wherein performing error correction on the codeword comprises correcting an error in the QK index bits (Laurent: ‘the ecc decoding process to detect an error to obtain data bits or payload’; “the memory device may unbalance codeword(x, y, z) based on balancing information bits that indicate the packets (e.g., portions) of codeword(x, y, z) that were inverted during the balancing process.” [0095-0096]).
Claims 15-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pande (US 2005/0091429 A1), (hereinafter Pande).
Regarding claim 15, Pande teaches, a method comprising: receiving a number of packets (Pande: ‘designing a data structure include receiving data as packets and then writing data to and reading data from a memory’ [0010]); generating a Gray coding (Pande: “FIG. 2 shows a flow chart illustrating an embodiment of a process that generates a Gray-code sequence” [0031]); trimming the Gray coding to obtain a list (Pande: ‘FIG. 4 shows an embodiment of a method for reducing a Gray-code sequence according to the present invention.’ [0033] & [Fig.4]); and removing successive values in the list to reduce a size of the list (Pande: ‘removing successive values in Figs. 4, 5, 6A’ [Fig. 2, block 250] & [0033] “FIG. 4 shows an embodiment of a method for reducing a Gray-code sequence according to the present invention. The Gray-code sequence may be reduced by removing a middle portion centered on the centerline. For example, the middle portion may include three mirrored pairs: 0111 and 1111; 0101 and 1101; and 0100 and 1100. With the removal of the middle portion, the original Gray-code sequence may be reduced from a sequence length of 16 to a sequence length of 10. Even though the sequence has been reduced in length, the sequence may still retain its circular properties and have a Hamming distance equal to one for any two consecutive codes. [0034] FIG. 5 shows another embodiment of a method for reducing a Gray-code sequence according to the present invention. The Gray-code sequence may be reduced by removing a top portion and a corresponding bottom portion (i.e., a mirrored portion with respect to the center line). For example, the top portion and the bottom portion may include three mirrored pairs: 0000 and 1000; 0001 and 1001; and 0011 and 1011. With the removal of the middle portion, the original Gray-code sequence may be reduced from a sequence length of 16 to a sequence length of 10. [0035] FIGS. 6A-B show two more embodiments of a method for reducing a Gray-code sequence according to the present invention. The Gray-code sequence may be reduced by removing a middle portion and a top portion with a corresponding bottom portion. In FIG. 6A, the middle portion includes a single pair of mirrored codes and the top/bottom portion includes two pairs of mirrored codes. In FIG. 6B, the middle portion includes two pairs of mirrored codes and the top/bottom portion includes a single pair of mirrored codes.” ) to a size equal to the number of packets (Pande: ‘designing a data structure include receiving data as packets and then writing data to and reading data from a memory’ [0010]; “FIGS. 4-6 illustrate, for example, that a particular Gray-code sequence may be reduced a number of different ways to create a number of different reduced sequences. From a plurality of different reduced sequences, an optimal code sequence may be chosen which optimizes the mapping of the transformation function and design of the counters that are used for the read and write pointers. [0037] Some embodiments according to the present invention may have one or more of the following advantages. By releasing the restriction that a FIFO data structure be of depth 2n, many inefficiencies may be avoided such as, for example, underused FIFO data structure depth. Furthermore, many of the efficiencies such as excessive FIFO data structure depth may become quite substantial as FIFO data structure width or the number of FIFO data structures increases. In addition, by designing a FIFO data structure of any depth, many of the fan-out constraints on clock and data signals may be maintained [0036-0037].);
Regarding claim 16, Pande teaches, the method of claim 15, wherein the list comprises a special Gray list; wherein trimming the Gray coding comprises identifying an ending value that is an inverse of a first value of the special Gray list and removing all Gray code values appearing after the ending value (Pande: ‘any modified or reduced ‘standard Gray list’ could be considered as ‘special Gray list’;’ ‘reducing a gray-code sequence by removing one or more codes and corresponding mirrored codes’ [Fig.2, block 250] & [0033-0035]; ‘the removal of pairs of codes may reduce the gray-code sequence to the desired length’ [0031]; Further, what gray-code are to be removed from a gray code sequence and where the gray-code sequence(s) are to be removed from would have been a matter of design choice for a person ordinary skill in the art depending on the goal of a particular application/analysis).
Regarding claim 17, Pande teaches, the method of claim 15, wherein the list comprises a special Gray list; wherein generating a Gray coding comprises generating the Gray coding using a binary-reflected Gray code (BRGC) algorithm (Pande: ‘any modified or reduced ‘standard Gray list’ could be considered as ‘special Gray list’;’ ‘binary gray code’ [0025]).
Regarding claim 18, Pande teaches, the method of claim 15, wherein the list comprises a special Gray list; wherein iteratively identifying and removing successive values in the special Gray list further comprises determining when a size of the special Gray list is equal to the number of packets and storing the special Gray list (Pande: ‘any modified or reduced ‘standard Gray list’ could be considered as ‘special Gray list’;’ ‘the removal of pairs of codes may reduce the gray-code sequence to the desired length’ [0031]).
Regarding claim 19, Pande teaches, the method of claim 15, wherein the list comprises a special Gray list; wherein iteratively identifying and removing successive values in the special Gray list comprises: identifying a pair of Gray code values, the pair of Gray code values appearing between a first Gray code value and second Gray code value; determining that the pair of Gray code values can be removed when the first Gray code value and second Gray code value can be adjacent to one another without affecting conformance with a Gray encoding; and removing the pair of Gray code values to generate a new special Gray list (Pande: ‘any modified or reduced ‘standard Gray list’ could be considered as ‘special Gray list’;’ ‘reducing a gray-code sequence by removing one or more codes and corresponding mirrored codes’ [Fig.2, block 250] & [0033-0035]).
Regarding claim 20, Pande teaches, the method of claim 15, wherein the list comprises a special Gray list; wherein iteratively identifying and removing successive values in the special Gray list comprises analyzing successive pairs of Gray code values from one of a beginning of the Gray coding or an ending of the Gray coding (Pande: ‘any modified or reduced ‘standard Gray list’ could be considered as ‘special Gray list’;’ ‘reducing a gray-codes by removing one or more codes and corresponding mirrored codes from the top, middle or bottom portion’ [Fig.2, block 250], [Figs.4-6] & [0033-0035]).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 1 is rejected under 35 U.S.C. 103 as being unpatentable over Laurent et al. (US 2022/0321147 A1) in view of Oren (US 2017/0078047 A1), (hereinafter Laurent-Oren).
Regarding claim 1, Laurent teaches, a method comprising: combining the payload, parity portion, and the index bits to form a codeword (Laurent: ‘generating a codeword using payload (or data bits), parity, and balancing information bits’ [0032, 0035, 0052-0053, 0057-0058]); and writing the codeword to a memory device (Laurent: “… a memory device may generate a codeword for a data set. After inverting a portion of the codeword according to the coding scheme and so that the codeword is associated with a target distribution of programmable states, the memory device may store the codeword…” [0014]).
Laurent teaches computing parity bits but does not explicitly disclose protecting the index bits by the parity bits.
However, Oren teaches in an analogous art, computing a parity portion based on a payload and index bits for a codeword (Oren: ‘ the data bits and index bits are protected by the redundancy bits,’ “[0015] ….In an example implementation of this disclosure, a codeword comprises Ndbcw data bits, Nibcw index bits, and Nrbcw redundancy bits, and thus Ntbcw = Ndbcw+Nibcw+Nrbcw. In such an implementation, the circuit 120 may append Nibcw mock index bits to the Ndbcw data bits 103, and then append Nrbcw mock redundancy bits after the index bits. In this manner, the mock codeword 121 mocks a systematic codeword having information bits (the data bits and index bits) embedded in the mock codeword 121 along with the redundancy bits that protect those information bits.”)
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine Laurent’s teachings of ‘storing balancing information bits’ with Oren’s teaching of ‘protecting data bits and index bits by the redundancy bits’ to provide .system and methods that improves transmitter distortion management substantially [0003].
Claims 2-9 are rejected under 35 U.S.C. 103 as being unpatentable over Laurent et al. (US 2022/0321147 A1) in view of Oren (US 2017/0078047 A1), and further in view of Pande (US 2005/0091429 A1), (hereinafter Laurent-Oren-Pande).
Regarding claim 2, Laurent-Oren teaches, the method of claim 1, further comprising generating the index bits ….wherein the index bits comprise quantized Knuth (QK) index bits for a codeword. (Laurent: ‘QK index bit or balancing information bits’ [0035-0036]) …;
Laurent-Oren does not explicitly disclose, …by selecting a Gray coding from a special Gray list,
However, Pande teaches in an analogous art, ‘with broadest reasonable interpretation, and/or as per applicant’s disclosure [0068] any modified or reduced ‘standard Gray list’ could be considered as ‘special Gray list’ [Fig. 2, block 250] & [0033] FIG. 4 shows an embodiment of a method for reducing a Gray-code sequence according to the present invention. The Gray-code sequence may be reduced by removing a middle portion centered on the centerline. For example, the middle portion may include three mirrored pairs: 0111 and 1111; 0101 and 1101; and 0100 and 1100. With the removal of the middle portion, the original Gray-code sequence may be reduced from a sequence length of 16 to a sequence length of 10. Even though the sequence has been reduced in length, the sequence may still retain its circular properties and have a Hamming distance equal to one for any two consecutive codes. [0034] FIG. 5 shows another embodiment of a method for reducing a Gray-code sequence according to the present invention. The Gray-code sequence may be reduced by removing a top portion and a corresponding bottom portion (i.e., a mirrored portion with respect to the center line). For example, the top portion and the bottom portion may include three mirrored pairs: 0000 and 1000; 0001 and 1001; and 0011 and 1011. With the removal of the middle portion, the original Gray-code sequence may be reduced from a sequence length of 16 to a sequence length of 10. [0035] FIGS. 6A-B show two more embodiments of a method for reducing a Gray-code sequence according to the present invention. The Gray-code sequence may be reduced by removing a middle portion and a top portion with a corresponding bottom portion. In FIG. 6A, the middle portion includes a single pair of mirrored codes and the top/bottom portion includes two pairs of mirrored codes. In FIG. 6B, the middle portion includes two pairs of mirrored codes and the top/bottom portion includes a single pair of mirrored codes.
With the teaching of Pande of reducing the length of gray code sequence from the middle portion (as in Fig. 4), or from the top and corresponding mirrored bottom portion (as in Fig.5), or from the middle portion and a top portion with a corresponding bottom portion (as in Fig. 6A-B) it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to remove values in the gray list to reduce size of the gray list. Even though the sequence has been reduced in length, the sequence may still retain its circular properties and have a Hamming distance equal to one for any two consecutive codes. A particular Gray-code sequence may be reduced a number of different ways to create a number of different reduced sequences. By doing so, from a plurality of different reduced sequences, an optimal code sequence may be chosen which optimizes the mapping of the transformation function and design of the counters that are used for the read and write pointers.
Regarding claim 3, Laurent-Oren-Pande teaches, the method of claim 2, further comprising generating the special Gray list by: receiving a number of packets; generating a Gray coding; trimming the Gray coding to obtain a special Gray list; and iteratively identifying and removing successive values in the special Gray list to reduce a size of the special Gray list to a size equal to the number of packets (Pande: ‘trimming gray coding to get a special gray list’ [Fig. 2, block 250] & [0033-0035]; ‘With the teaching of Pande, choosing an optimal code sequence from a plurality of different reduced sequences is a design choice for a person ordinary skill in the art’, “FIGS. 4-6 illustrate, for example, that a particular Gray-code sequence may be reduced a number of different ways to create a number of different reduced sequences. From a plurality of different reduced sequences, an optimal code sequence may be chosen which optimizes the mapping of the transformation function and design of the counters that are used for the read and write pointers. [0037] Some embodiments according to the present invention may have one or more of the following advantages. By releasing the restriction that a FIFO data structure be of depth 2n, many inefficiencies may be avoided such as, for example, underused FIFO data structure depth. Furthermore, many of the efficiencies such as excessive FIFO data structure depth may become quite substantial as FIFO data structure width or the number of FIFO data structures increases. In addition, by designing a FIFO data structure of any depth, many of the fan-out constraints on clock and data signals may be maintained [0036-0037].).
Regarding claim 4, Laurent-Oren-Pande teaches, the method of claim 3, wherein the number of packets is identified based on a Hamming distance of an error correction code (ECC) (Pande: ‘hamming distance’ [0023,0030, 0033]).
Regarding claim 5, Laurent-Oren-Pande teaches, the method of claim 2, wherein combining the payload, parity portion, and the QK index bits to form a codeword comprises concatenating the payload, parity portion, and QK index bits (Laurent: ‘generating a codeword using payload (or data bits), parity, and balancing information bits’ [0032, 0035, 0052-0053, 0057-0058]; Oren: ‘ the data bits and index bits are protected by the redundancy bits,’ [0015]).
Regarding claim 6, Laurent-Oren-Pande teaches, the method of claim 5, further comprising adding one or more padding bits to the codeword (Laurent: “… the padding module 755 may be configured as or otherwise support a means for adding one or more bits to the codeword after the inverting and based at least in part on a difference between a distribution of states for the codeword and the target distribution, where storing the codeword is based at least in part on adding the one or more bits to the codeword” [0060, 0117, 0134-0135]).
Regarding claim 7, Laurent-Oren-Pande teaches, the method of claim 2, wherein selecting the QK index bits comprises selecting a binary coding of a number of QK index bits (Pande: ‘binary code’ [0027-0028]).
Regarding claim 8, Laurent-Oren-Pande teaches, the method of claim 2, wherein the codeword comprises a plurality of packets and the method further comprising inverting a subset of the plurality of packets to obtain a QK index (Laurent: ‘ the memory device may invert a portion of codeword(x, y, z) so that codeword(x, y, z) has a fixed weight. [0070, 0076, 0082,0099]).
Regarding claim 9, Laurent-Oren-Pande teaches, the method of claim 8, further comprising distributing the QK index bits among the plurality of packets (Laurent: ‘generating a codeword using payload (or data bits), parity, and balancing information bits’ [0032, 0035, 0052-0053, 0057-0058]).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Laurent et al. (US 2022/0321147 A1) in view of Pande (US 2005/0091429 A1), (hereinafter Laurent-Pande).
Regarding claim 13, Laurent teaches, the method of claim 12, comprising converting the QK index bits to a QK index ….(Laurent: ‘QK index bit or balancing information bits’ [0035-0036]);
Laurent does not explicitly disclose, …using a special Gray list, the special Gray list comprising a Gray list beginning with a first value and ending with a second value comprising an inverse of the first value, wherein a size of the special Gray list is equal to a size of the plurality of packets
However, Pande teaches in an analogous art, ‘with broadest reasonable interpretation, and/or as per applicant’s disclosure [0068] any modified or reduced ‘standard Gray list’ could be considered as ‘special Gray list’ [Fig. 2, block 250] & [0033] FIG. 4 shows an embodiment of a method for reducing a Gray-code sequence according to the present invention. The Gray-code sequence may be reduced by removing a middle portion centered on the centerline. For example, the middle portion may include three mirrored pairs: 0111 and 1111; 0101 and 1101; and 0100 and 1100. With the removal of the middle portion, the original Gray-code sequence may be reduced from a sequence length of 16 to a sequence length of 10. Even though the sequence has been reduced in length, the sequence may still retain its circular properties and have a Hamming distance equal to one for any two consecutive codes. [0034] FIG. 5 shows another embodiment of a method for reducing a Gray-code sequence according to the present invention. The Gray-code sequence may be reduced by removing a top portion and a corresponding bottom portion (i.e., a mirrored portion with respect to the center line). For example, the top portion and the bottom portion may include three mirrored pairs: 0000 and 1000; 0001 and 1001; and 0011 and 1011. With the removal of the middle portion, the original Gray-code sequence may be reduced from a sequence length of 16 to a sequence length of 10. [0035] FIGS. 6A-B show two more embodiments of a method for reducing a Gray-code sequence according to the present invention. The Gray-code sequence may be reduced by removing a middle portion and a top portion with a corresponding bottom portion. In FIG. 6A, the middle portion includes a single pair of mirrored codes and the top/bottom portion includes two pairs of mirrored codes. In FIG. 6B, the middle portion includes two pairs of mirrored codes and the top/bottom portion includes a single pair of mirrored codes.
With the teaching of Pande of reducing the length of gray code sequence from the middle portion (as in Fig. 4), or from the top and corresponding mirrored bottom portion (as in Fig.5), or from the middle portion and a top portion with a corresponding bottom portion (as in Fig. 6A-B) it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to remove values in the gray list to reduce size of the gray list. Even though the sequence has been reduced in length, the sequence may still retain its circular properties and have a Hamming distance equal to one for any two consecutive codes. ‘the removal of pairs of codes may reduce the gray-code sequence to the desired length’ [0031]; Further, what gray-code are to be removed from a gray code sequence and where the gray-code sequence(s) are to be removed from would have been a matter of design choice for a person ordinary skill in the art depending on the goal of a particular application/analysis. A particular Gray-code sequence may be reduced a number of different ways to create a number of different reduced sequences. By doing so, from a plurality of different reduced sequences, an optimal code sequence may be chosen which optimizes the mapping of the transformation function and design of the counters that are used for the read and write pointers.
Citation of Pertinent Prior Art
It is noted that any citations to specific, pages, columns, lines, or figures in the prior art references and any interpretation of the reference should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. See MPEP 2123.
Conclusion
The following prior arts made of record, listed on form PTO-892, and not relied upon, if any, are considered pertinent to applicant's disclosure:
Lim et al. (US 6,970,113 B1) teaches [Summary of the Invention] A solution to the problem of finding a cyclic Gray code of n-many bits with less than 2.sup.n entries is provided by a disclosed algorithm that allows the generation of a cyclic Gray code in n-many bits having 2k-many entries ("2k Gray codes"), for any natural number k, where 2.sup.(n-1) <2k<2.sup.n and n is a positive integer. We shall call such Gray codes "reduced" Gray codes. In brief, the method involves the construction of a 2.sup.n -many entry code in n-many bits with a reflected binary technique, and then selecting the last k-many ordered entries in the first half of the full reflected binary code, followed by the first k-many ordered entries in the second half of the full reflected binary code. These selected ordered 2k-many entries are a shortened, yet still cyclic, (reduced) Gray code in n-many bits. Alternatively, the first k-many ordered entries in the first half of the full reflected binary code can be selected, followed by the last k-many ordered entries in the second half of the full reflected binary code. If a Gray code is represented as a table whose columns are bit positions and whose rows are the code entries, then entire columns can optionally be interchanged at will, either before or after the 2k-many selection, to produce additional different cyclic reduced Gray codes that do not outwardly appear to be `reflected` ones. Once a cyclic reduced Gray code is identified its gate level circuit realization in hardware (e.g., counter, Gray-binary converter) is readily obtained with a standard synthesis tools such as Synopsys or Simplify that is driven by, say, a description in Verilog of how the entries in the code are related to each other (e.g., sequence, mapping) and to any applied control signals (e.g., increment, decrement).
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ENAMUL MD KABIR whose telephone number is (571)270-7256. The examiner can normally be reached on 10:00-6:30 pm.
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/ENAMUL M KABIR/
Examiner, Art Unit 2112
/ALBERT DECADY/Supervisory Patent Examiner, Art Unit 2112