DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
RESPONSE TO AMENDMENT
Claim rejections based on prior art
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/18/2026 has been entered.
Applicant’s arguments filed on 02/18/2025 with respect to claims 1-20 have been fully considered but are moot in view of newly cited reference.
OBJECTIONS TO THE CLAIMS
Claims 1-20 are objected to as being indefinite for failing to particularly point out and distinctly claim the subject matter which applicant regards as the invention.
As per claim 1, limitations “wherein the first specified time is determined based on a command mix corresponding to a relative number of incoming read commands to a number of incoming write commands”, and “wherein the second specified time is determined based on the command mix corresponding to the relative number of incoming read commands to the number of incoming write commands” are confusing, particularly because of language “number of incoming read commands to a number of incoming write commands”. It’s not clear if read and write commands are combined. Claims 7 and 16 have the same problem. Correction is needed.
REJECTIONS BASED ON PRIOR ART
Claim Rejections - 35 USC § 103
1. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
2. Claims 1-16 are rejected under 35 U.S.C. 103(a) as being unpatentable over Shen et al. (US pub. # 2019/0196995), hereinafter, “Shen”, in view of Malik et al. (US pub. # 2022/0066961), hereinafter, “Malik”.
3. As per claim 1, Shen discloses a method for command scheduling in a memory controller (memory controller 200 of fig. 2, as also discloses in fig. 1), the method comprising: processing commands of a first command type from a command queue including transmitting data in a first direction using a data bus [see fig. 2 and paragraph 0016, which discloses “the control logic in the memory controller determines which one of a read mode and a write mode is a current mode for the off-chip data bus and the memory device. In an embodiment, each mode has a threshold number of memory access requests to send from the memory controller to the memory device prior to an off-chip data bus turnaround being performed. A data bus turnaround refers to changing a transmission mode of a bus from transmitting in one direction to the other (opposite) direction. For example, when changing from a read mode to a write mode, or vice versa, a data bus turnaround is performed. This threshold number of memory access requests to send is referred to as the “burst length””] during a first specified time comprising a first phase time duration or a first cycle count limit (note, claim ‘first cycle count limit’ is being equated to a threshold number, burst length, during a first read or write mode; see paragraph 0017, which discloses “in some embodiments, a count of remaining read requests to send is updated when memory read requests are sent from the memory controller to the memory device. The count is incremented or decremented depending on the initial value of the count, which may increment from zero to the threshold number of memory read requests, or read burst length, or alternatively decrement from the read burst length to zero. In various embodiments, a write count is updated in a similar manner based on the initial value of count when memory write requests are sent from the memory controller to the memory device. For sending write requests to the memory device, a write burst length is used”); turning around the data bus upon elapsing the first phase time duration or the first cycle count limit based on a timer or counter measurement (note, a ‘counter measurement’ is being equated to a count increment or count decrement, as discloses in paragraph 0017), wherein turning around the data bus incurs a first number of idle data bus cycles (see paragraphs 0019 and 0020, which teach turning a data bus around after a number of clock cycles), wherein turning around the data bus incurs a first number of idle data bus cycles (see paragraphs 0020 and 0051); and following the idle data bus cycles, processing commands of a second command type from the command queue including transmitting data in a second direction using the data bus during a second specified time comprising a second phase time duration or a second cycle count limit [note, claim ‘second cycle count limit’ is being equated to a threshold number, burst length, during a second read or second write mode; see paragraph 0048, which discloses “in some embodiments, control registers 270 store an indication of a current mode. For example, the off-chip memory data bus and memory device support either a read mode or a write mode at a given time. Therefore, traffic is routed in a given single direction during the current mode and changes direction when the current mode is changed after a data bus turnaround latency. In various embodiments, control registers 270 store a threshold number of read requests (read burst length) to send during the read mode. In some embodiments, the control registers 270 also store a write bust length. In some embodiments, the burst length is the same for each of the read mode and the write mode. In other embodiments, two different burst lengths are used for the read mode and the write mode”].
But fails to specifically disclose wherein the first specified time is determined based on a command mix corresponding to a relative number of incoming read commands to a number of incoming write commands, and wherein the second specified time is determined based on the command mix corresponding to the relative number of incoming read commands to the number of incoming write commands.
Malik discloses wherein the first specified time (a first timing constraint during a first operation; see paragraph 0148) is determined based on a command mix corresponding to a relative number of incoming read commands to a number of incoming write commands, and wherein the second specified time (a second timing constraint during a second operation) is determined based on the command mix corresponding to the relative number of incoming read commands to the number of incoming write commands (see paragraph 0148, which discloses “determining that a quantity of write commands queued for the memory are for banks that have satisfied a timing constraint for activating different rows in a same bank, and configuring, based on determining that the quantity of write commands queued for the memory are for banks that have satisfied the timing constraint, the data bus to operate in a second direction for communicating data to the memory”).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Malik’s teaching of efficiently schedule access commands for a non-volatile memory by using a turnaround policy that accounts for timing constraints for activating different areas, such as different rows of the same bank, into Shen’s teaching of a memory controller in a computing system to determine a threshold number of memory access requests that have not been sent to a memory device in a current mode of a read mode and a write mode, for the benefit of increasing scheduling efficiency of access commands of a device.
4. As per claim 2, the combination of Shen and Malik discloses “The method of claim 1” [See rejection to claim 1 above], further comprising turning around the data bus again upon elapsing the second phase time duration or the second cycle count limit, wherein turning around the data bus again incurs a second number of idle data bus cycles [see paragraph 0019 of Shen, which discloses “when the control logic determines the threshold number of memory access requests, or burst length, has been sent from the memory controller in the current mode, the control logic indicates it is time for a data bus turnaround and changes the current mode to another mode of the read mode and the write mode. For example, when the current mode is a read mode and the control logic determines the threshold number of memory read requests (read burst length) sent from the read queue have been sent, the control logic indicates it is time for a data bus turnaround and changes the current mode of the memory controller from the read mode to the write mode. The latency for the data bus turnaround begins at this time”].
5. As per claim 3, Shen discloses wherein the first and second number of idle data bus cycles are different (see paragraph 0051).
6. As per claim 4, Shen discloses comprising determining the first phase time duration or first cycle count limit elapsed by comparing a timer or counter value, respectively, to a stored phase duration value (see paragraphs 0017 and 0049).
7. As per claim 5, Shen discloses wherein the commands of the first command type are exclusively read commands and wherein the commands of the second command type are exclusively write commands (see paragraph 0017).
8. As per claim 6, Shen discloses comprising interrupting the processing of commands of the first command type when the command queue includes only commands of the second command type, wherein interrupting the processing commands of the first command type includes turning around the data bus and processing commands of the second command type from the command queue (see abstract and paragraph 0017).
9. As per claim 7, Shen discloses a method for command selection by a memory controller (memory controller 200 of fig. 2, as also discloses in fig. 1), the method comprising: queuing multiple commands including read commands and write commands in a command queue bus [see fig. 2 and paragraph 0016, which discloses “the control logic in the memory controller determines which one of a read mode and a write mode is a current mode for the off-chip data bus and the memory device. In an embodiment, each mode has a threshold number of memory access requests to send from the memory controller to the memory device prior to an off-chip data bus turnaround being performed. A data bus turnaround refers to changing a transmission mode of a bus from transmitting in one direction to the other (opposite) direction. For example, when changing from a read mode to a write mode, or vice versa, a data bus turnaround is performed. This threshold number of memory access requests to send is referred to as the “burst length””]; initiating a first read phase for a specified (claim ‘specified’ is being equated to configured, for example, a first configuration of Shen to perform a first function. Claim language doesn’t recite how this ‘specification’ is expressed/done) first duration of time and, during the first read phase, processing read commands from the command queue exclusively of write commands in the command queue, and sending read data in a first direction using a data bus (see paragraphs 0017 and 0018); at expiration of the specified first duration of time, initiating a first write phase for a specified second duration of time, including turning the data bus around, processing write commands from the command queue exclusively of read commands in the command queue, and sending write data in a second direction using the data bus (see paragraphs 0019 and 0020); and at expiration of the specified second duration of time, initiating a second read phase including turning the data bus around, and processing additional read commands from the command queue exclusively of write commands in the command queue, and sending read data in the first direction using the data bus [see paragraph 0048, which discloses “in some embodiments, control registers 270 store an indication of a current mode. For example, the off-chip memory data bus and memory device support either a read mode or a write mode at a given time. Therefore, traffic is routed in a given single direction during the current mode and changes direction when the current mode is changed after a data bus turnaround latency. In various embodiments, control registers 270 store a threshold number of read requests (read burst length) to send during the read mode. In some embodiments, the control registers 270 also store a write bust length. In some embodiments, the burst length is the same for each of the read mode and the write mode. In other embodiments, two different burst lengths are used for the read mode and the write mode”].
But fails to specifically disclose wherein the specified first duration of time is based on a number of incoming read commands and a number of incoming write commands, and wherein the specified second duration of time is based on the number of incoming read commands and the number of incoming write commands.
Malik discloses wherein the specified first duration of time (a first timing constraint during a first operation; see paragraph 0148) is based on a number of incoming read commands and a number of incoming write commands, and wherein the specified second duration of time (a second timing constraint during a second operation) is based on the number of incoming read commands and the number of incoming write commands (see paragraph 0148, which discloses “determining that a quantity of write commands queued for the memory are for banks that have satisfied a timing constraint for activating different rows in a same bank, and configuring, based on determining that the quantity of write commands queued for the memory are for banks that have satisfied the timing constraint, the data bus to operate in a second direction for communicating data to the memory”).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Malik’s teaching of efficiently schedule access commands for a non-volatile memory by using a turnaround policy that accounts for timing constraints for activating different areas, such as different rows of the same bank, into Shen’s teaching of a memory controller in a computing system to determine a threshold number of memory access requests that have not been sent to a memory device in a current mode of a read mode and a write mode, for the benefit of increasing scheduling efficiency of access commands of a device.
10. As per claim 8, Shen discloses, comprising receiving, at respective phase registers, duration information indicating a specified time duration or a cycle count of the first read phase and the first write phase (see paragraphs 0017 and 0049).
11. As per claim 9, Shen discloses wherein the duration information is the same for the first read phase and the first write phase (see paragraphs 0048 and 0051).
12. As per claim 10, Shen discloses wherein the duration information is different for the first read phase and the first write phase (see paragraph 0051).
13. As per claim 11, Shen discloses, comprising receiving, following expiration of at least one of the first and second specified durations of time (see paragraphs 0019 and 0020), updated duration information for at least one of the phase registers (see paragraph 0048).
14. As per claim 12, Shen discloses wherein a duration of the second read phase corresponds to the updated duration information (see paragraph 0048).
15. As per claim 13, Shen discloses wherein processing the read commands from the command queue exclusively of write commands includes: determining whether an unprocessed read command is available in the multiple commands; and responsive to determining no unprocessed read command is available, turning the data bus around during the first read phase, selecting a write command from the command queue, processing the selected write command, and sending write data for the selected write command in the second direction using the data bus (see paragraphs 0019 and 0020).
16. As per claim 14, Shen discloses, comprising: receiving an indication of a new read command available in the command queue; and following the processing the selected write command, turning the data bus around again and processing the new read command (see paragraph 0019).
17. As per claim 15, Shen discloses wherein processing the write commands from the command queue exclusively of read commands includes: determining whether an unprocessed write command is available in the multiple commands; and responsive to determining no unprocessed write command is available, turning the data bus around during the first write phase, selecting a read command from the command queue, processing the selected read command, and sending read data for the selected read command in the first direction using the data bus (see paragraph 0069).
18. As per claim 16, Shen discloses an apparatus (computing system 100 of fig. 1) comprising: a memory device (DRAM 170 and disk memory 162 of fig. 1, as discloses in paragraph 0023); and a controller coupled (memory controller 130/200 of fig. 1/2, as also disclose in fig. 1/2) to the memory device (see fig. 1), wherein the controller comprises: a read phase register (a first control registers 270) configured to store information about a read phase duration (see paragraph 0048, which discloses “in various embodiments, control registers 270 store a threshold number of read requests (read burst length) to send during the read mode. In some embodiments, the control registers 270 also store a write bust length. In some embodiments, the burst length is the same for each of the read mode and the write mode. In other embodiments, two different burst lengths are used for the read mode and the write mode”); a write phase register (a second control registers 270) configured to store information about a write phase duration (see paragraphs 0048 and 0051); a timer circuit (see paragraph 0020, which teaches measurement in time, e.g., nanoseconds, a function of claim ‘timer circuit’; see also paragraph 0021, which discloses “then in some embodiments the control logic indicates it is time for a data bus turnaround and changes the current mode of the memory controller, the data bus, and the memory device”); and command scheduling logic configured to select a particular read command or write command from a command queue based on a command phase (see paragraph 0020), wherein the command phase alternates between a read phase and a write phase according to respective duration values stored in the phase registers and an elapsed time duration measured by the timer circuit (see paragraph 0041, which discloses “In various embodiments, memory bus 150 supports sending data traffic in a single direction for a given amount of time, such as during a given mode of the read mode and the write mode, and then sends data traffic in the opposite direction for another given amount of time such as during the other mode of the read mode and the write mode. In an embodiment, memory bus 150 utilizes at least a command bus and a data bus, and memory bus 150 supports a read mode for sending data traffic on the data bus from DRAM 170 to memory controller 130. Additionally, memory bus 150 supports a write mode for sending data traffic on the data bus from memory controller 130 to DRAM 170”), wherein the memory device is configured to exclusively process read commands during the read phase and exclusively process write commands during the write phase [see paragraph 0048, which discloses “in some embodiments, control registers 270 store an indication of a current mode. For example, the off-chip memory data bus and memory device support either a read mode or a write mode at a given time. Therefore, traffic is routed in a given single direction during the current mode and changes direction when the current mode is changed after a data bus turnaround latency. In various embodiments, control registers 270 store a threshold number of read requests (read burst length) to send during the read mode. In some embodiments, the control registers 270 also store a write bust length. In some embodiments, the burst length is the same for each of the read mode and the write mode. In other embodiments, two different burst lengths are used for the read mode and the write mode”].
But fails to specifically disclose adjust the information about the read phase duration and the information about the write phase duration for at least subsequent read phase and at least one subsequent write phase based on a relative number of incoming read commands to a number of incoming write commands.
Malik discloses adjust the information about the read phase duration and the information about the write phase duration for at least subsequent read phase and at least one subsequent write phase based on a relative number of incoming read commands to a number of incoming write commands (see paragraph 0148, which discloses “determining that a quantity of write commands queued for the memory are for banks that have satisfied a timing constraint for activating different rows in a same bank, and configuring, based on determining that the quantity of write commands queued for the memory are for banks that have satisfied the timing constraint, the data bus to operate in a second direction for communicating data to the memory”).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Malik’s teaching of efficiently schedule access commands for a non-volatile memory by using a turnaround policy that accounts for timing constraints for activating different areas, such as different rows of the same bank, into Shen’s teaching of a memory controller in a computing system to determine a threshold number of memory access requests that have not been sent to a memory device in a current mode of a read mode and a write mode, for the benefit of increasing scheduling efficiency of access commands of a device.
19. Claims 17, 19 and 20 are rejected under 35 U.S.C. 103(a) as being unpatentable Shen et al. (US pub. # 2019/0196995), hereinafter, “Shen”, in view of Malik et al. (US pub. # 2022/0066961), hereinafter, “Malik” and further in view of Redfern et al. (US pub. # 2018/0246855), hereinafter, “Redfern”.
20. As per claim 17, the combination of Shen and Malik discloses “The apparatus of claim 16” [See rejection to claim 16 above], but fails to expressly discloses wherein the command scheduling logic includes: a multiplexer circuit coupled to the read phase register and the write phase register and configured to output a time limit corresponding to information in a selected one of the read phase register and the write phase register based on a phase-indicating signal; and a flip-flop circuit configured to provide the phase-indicating signal responsive to information about a relationship between the elapsed time duration from the timer circuit and the time limit from a multiplexer circuit; wherein the phase-indicating signal indicates the command phase.
Redfern discloses wherein the command scheduling logic includes: a multiplexer circuit coupled to the read phase register and the write phase register and configured to output a time limit corresponding to information in a selected one of the read phase register and the write phase register based on a phase-indicating signal; and a flip-flop circuit configured to provide the phase-indicating signal responsive to information about a relationship between the elapsed time duration from the timer circuit and the time limit from a multiplexer circuit; wherein the phase-indicating signal indicates the command phase (see paragraphs 0150 and 0186).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Redfern’s teaching of a method to dynamically reconfigure an interpretation of a fixed external memory data bus (EMB) as having different scalar data bit widths, into Malik’s teaching of efficiently schedule access commands for a non-volatile memory by using a turnaround policy that accounts for timing constraints for activating different areas, such as different rows of the same bank and Shen’s teaching of predicting a result of a second access to a nonvolatile memory device after a first access by performing machine learning based on information collected, for the ability/benefit of a single multiplication/accumulation processor to both reuse multiplication hardware but also permit changing the point scalar resolution dynamically thus allowing a variety of data interpretations to occur within the context of a single data source.
21. As per claim 19, the combination of Shen, Malik and Redfern discloses “The apparatus of claim 17” [See rejection to claim 17 above], wherein the controller is configured to determine a read/write command ratio for commands in the command queue and, in response, update or adjust the duration values in one or both of the phase registers (see paragraph 0017 of Shen).
22. As per claim 20, the combination of Shen, Malik and Redfern discloses “The apparatus of claim 17” [See rejection to claim 17 above], wherein during a read phase, the command scheduling logic is configured to interrupt the read phase when the command queue is unoccupied by a read command, and the command scheduling logic is configured to interrupt the write phase when the command queue is unoccupied by a write command (see abstract and paragraph 0017 of Shen).
23. Claim 18 is rejected under 35 U.S.C. 103(a) as being unpatentable Shen et al. (US pub. # 2019/0196995), hereinafter, “Shen”, in view of Malik et al. (US pub. # 2022/0066961), hereinafter, “Malik”, in view of Redfern et al. (US pub. # 2018/0246855), hereinafter, “Redfern”, and further in view of Roberts (US pub. # 2016/0371014), hereinafter, “Roberts”.
24. As per claim 18, the combination of Shen, Malik and Redfern discloses “The apparatus of claim 17” [See rejection to claim 17 above], but fails to expressly discloses wherein the command scheduling logic further includes first-ready, first-come, first-served (FRFCFS) logic configured to select the particular read command or write command for processing by the controller during the command phase.
Roberts discloses wherein the command scheduling logic further includes first-ready, first-come, first-served (FRFCFS) logic configured to select the particular read command or write command for processing by the controller during the command phase (see paragraph 0038).
It would have been obvious to one having ordinary skills in the art before the effective filling date of the claimed invention to incorporate Roberts’ teaching of for ordering memory commands in computer systems based on the latency of the memory commands and/or other properties of the memory commands, into Malik’s teaching of efficiently schedule access commands for a non-volatile memory by using a turnaround policy that accounts for timing constraints for activating different areas, such as different rows of the same bank, into Redfern’s teaching of a method to dynamically reconfigure an interpretation of a fixed external memory data bus (EMB) as having different scalar data bit widths, and into Shen’s teaching of predicting a result of a second access to a nonvolatile memory device after a first access by performing machine learning based on information collected, for the benefit of improving efficiency of memory commands by ordering the memory commands based on latency and/or other aspects/properties of the memory commands.
CLOSING COMMENTS
CONCLUSION
a. STATUS OF CLAIMS IN THE APPLICATION
The following is a summary of the treatment and status of all claims in the
application as recommended by M.P.E.P. 707.07(i):
a (1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-20 have received a first action on the merits and are subject of a first action non-final.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the
Examiner should be directed to Ernest Unelus whose telephone number is (571) 272-
8596. The examiner can normally be reached on Monday to Friday 9:00 AM to 5:00 PM.
IMPORTANT NOTE
If attempts to reach the above noted Examiner by telephone are unsuccessful, the Examiner's supervisor, Mr. Idriss Alrobaye, can be reached at the following telephone number: Area Code (571) 270-1023.
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/Ernest Unelus/
Primary Examiner
Art Unit 2181
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