Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This Office Action is in response to the application 18/443,969 filed on 02/16/2024.
Claims 1 – 10 have been examined and are pending in this application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 02/16/2019. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that use the word “means” or “step” but are nonetheless not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph because the claim limitation(s) recite(s) sufficient structure, materials, or acts to entirely perform the recited function. Such claim limitation(s) is/are: "control circuit", "delay circuit", "determination circuit", “generation circuit”, “element”, “detector” in claim 1 - 3 and 8 - 10..
Because this/these claim limitation(s) is/are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 – 7, 10 are rejected under 35 U.S.C. 102(a)(1) as being by Nishino et al. (US 2020/0296313 A1).
Regarding claim 1, Nishino discloses: “a light detector comprising:
a single-photon avalanche diode (SPAD) having one end connected to a first node [see abstract: an SPAD (single photon avalanche photodiode)];
a resistor component having one end connected to the first node [see abstract: a resistance component configured to be connected serially with the SPAD];
a switch element having one end connected to the first node [see abstract: a switch configured to be connected interposingly between the SPAD and the resistance component]; and
a control circuit configured to control the switch element to discharge or charge the first node, wherein in response to a change in a potential of the first node from a first potential to a second potential [see abstract: a switch configured to be connected interposingly between the SPAD and the resistance component and turned off in synchronism with the pulse signal],
the control circuit turns on the switch element until a second period elapses after a lapse of a first period measured from the change to the second potential, or until the potential of the first node changes back to the first potential during the second period [see para: 0088; FIG. 12 illustrates other exemplary output characteristics of the light reception signal PFout of the pixel 1. More specifically, FIG. 12 depicts an exemplary distribution of time intervals between adjacent pulses of the light reception signal PFout. The horizontal axis of the upper and the lower graphs in FIG. 12 represents time intervals between adjacent pulses of the light reception signal PFout. The vertical axis of the two graphs denotes counts totaling the pulse-to-pulse time intervals. The upper graph depicts a distribution of time intervals between adjacent pulses of the light reception signal PFout in the case where large quantities of after-pulses are generated. The lower graph illustrates a distribution of time intervals between adjacent pulses of the light reception signal PFout in the case where small quantities of after-pulses are generated. Further, broken-line waveforms in the upper and the lower graphs indicate an ideal gradient of a graphic distribution of time intervals between adjacent pulses of the light reception signal PFout. And see para: 0120], and
the control circuit turns off the switch element upon a lapse of the second period without the potential of the first node changing back to the first potential, and the control circuit turns on the switch element again after a lapse of a third period measured from the turning off of the switch element [see para: 0166; The pulse generation section 314 outputs the pulse signal Pc of a predetermined width upon detection of the light reception signal PFout. [0167] The pulse signal Pc is input to the control terminal of the switch 315. While the pulse signal Pc is being input, the switch 315 is turned off. This blocks the input path of the input current Iin to the SPAD 311. That is, the pulse signal Pc is output in synchronism with the output of the light reception signal PFout. The switch 315 is turned off in synchronism with the pulse signal Pc. This blocks the current flowing through the SPAD 311. And see para: 0168; 0169].
Regarding claim 2, Nishino discloses: “wherein the control circuit includes
a first delay circuit configured to delay a signal based on the potential of the first node [see para: 0009; Furthermore, the refresh period is started following the delay with the delay circuit after the capacitance voltage drops below the breakdown voltage],
a determination circuit configured to determine whether to discharge or charge the first node in accordance with an output of the first delay circuit [see para: 0049; The transistor 12, which is a current source operating in a saturation region, works as a quenching resistance that performs passive quenching. That is, when avalanche amplification occurs in the SPAD 11 causing a current to flow therethrough, a current also flows through the transistor 12 causing its resistance component to produce a voltage drop. This lowers the cathode potential Vs of the SPAD 11. When the voltage applied to the SPAD 11 becomes equal to or lower than the breakdown voltage Vbd, avalanche multiplication stops. Thereafter, the carriers accumulated in the SPAD 11 by avalanche multiplication are discharged through the transistor 12. This allows the cathode potential Vs to recover to a level near the initial potential Ve, setting the SPAD 11 again to Geiger mod],
a first pulse control circuit configured to generate [see para: 0119; a pulse generation section 314], in accordance with an output of the determination circuit, a pulse signal that enables the switch element to be turned on during the second period [see para: 0128; The switch 315 is turned off in synchronism with the pulse signal Pc from the pulse generation section 314. More specifically, the switch 315 is turned off during the period in which the pulse signal Pc is being input and is turned on during other periods],
a second pulse control circuit configured to disable the pulse signal in response to a change in the potential of the first node from the second potential to the first potential [see para: 0129; The transistor 316 is turned on in synchronism with the pulse signal Pc from the pulse generation section 314. More specifically, the transistor 316 is turned on during the period in which the pulse signal Pc is being input to the gate and is turned off during other periods], and
a third pulse control circuit configured to cause the determination circuit to determine again whether to discharge or charge the first node, upon a lapse of the second period without the potential of the first node reaching the first potential [see para: 0049; The transistor 12, which is a current source operating in a saturation region, works as a quenching resistance that performs passive quenching. That is, when avalanche amplification occurs in the SPAD 11 causing a current to flow therethrough, a current also flows through the transistor 12 causing its resistance component to produce a voltage drop. This lowers the cathode potential Vs of the SPAD 11. When the voltage applied to the SPAD 11 becomes equal to or lower than the breakdown voltage Vbd, avalanche multiplication stops. Thereafter, the carriers accumulated in the SPAD 11 by avalanche multiplication are discharged through the transistor 12. This allows the cathode potential Vs to recover to a level near the initial potential Ve, setting the SPAD 11 again to Geiger mode].
Regarding claims 3 – 5, the limitations from these claims are basically a matter of design choice because it only requires mere selection of specific component according to specific conditions so that control circuit to drive a low-resistance switch element that resets the node after SPAD breakdown.
Regarding claim 6, Nishino discloses: “wherein a transition speed of a logic level of an output signal of the first delay circuit is different between a transition of an input signal of the first delay circuit from a first logic level to a second logic level different from the first logic level, and a transition of the input signal from the second logic level to the first logic level [see para: 0168; Also, the pulse signal Pc is input to the gate of the transistor 316. While the pulse signal Pc is being input to the gate, the transistor 316 is turned on. This causes the path through which the input current Iin flows to transition from the SPAD 311 to the transistor 316. That is, the input current Iin is pulled into the transistor 316, so that the flow of the input current Iin to the SPAD 311 is suppressed. That is to say, the pulse signal Pc is output in synchronism with the output of the light reception signal PFout, with the transistor 316 turned on in synchronism with the pulse signal Pc, thereby pulling in the input current Iin. This suppresses the current flowing through the SPAD 311].
Regarding claim 7, Nishino discloses: “wherein the potential of the first node rises or lowers from the first potential to the second potential in consequence of a voltage drop based on a current that flows in consequence of a breakdown in the SPAD [see para: 0055; At time t1, a photon entering the SPAD 11 produces avalanche multiplication causing a current to flow through the SPAD 11. This in turn causes a current to flow through the transistor 12, producing a voltage drop and lowering the cathode potential Vs. When the cathode potential Vs drops to the breakdown voltage Vbd plus the potential Vspad, with the applied voltage of the SPAD 11 reaching the breakdown voltage Vbd, avalanche multiplication stops. Thereafter, the carriers accumulated in the SPAD 11 by avalanche multiplication are discharged through the transistor 12. This causes the cathode voltage Vs to rise gradually and recover ultimately to the potential Ve], and
in response to an occurrence of a breakdown in the SPAD again during the second period, the second period elapses without the potential of the first node reaching the first potential [see para: 0081; When the cathode potential Vs drops to the breakdown voltage Vbd plus the potential Vspad, with the applied voltage of the SPAD 11 reaching the breakdown voltage Vbd, avalanche multiplication stops. Thereafter, the cathode potential Vs starts to recover but, upon generation of an after-pulse, avalanche multiplication again occurs and the cathode potential Vs again decreases. When the cathode potential Vs drops to the breakdown voltage Vbd plus the potential Vspad, with the anode-to-cathode voltage of the SPAD 11 reaching the breakdown voltage Vbd, avalanche multiplication stops and the cathode potential Vs again starts to recover].
Regarding claim 10, claim 10 is rejected under the same art and evidentiary limitations as determined for the method of claim 1.
Furthermore, Nishino discloses: ”a light-emitting element configured to emit pulsed light to a detection target at predetermined time intervals [see para: 0013; a lighting apparatus configured to emit irradiation light];
a light detector configured to receive reflected light that is the pulsed light emitted from the light-emitting element, and that is reflected on the detection target [see para: 0013; an imaging apparatus configured to receive reflected light stemming from the irradiation light. The imaging apparatus includes a pixel array section having pixel sections arrayed therein, each of the pixel sections including: an SPAD (single photon avalanche photodiode)]; and
a distance operation circuit configured to perform an operation of a distance to the detection target in accordance with a timing at which the pulsed light is emitted by the light-emitting element [see para: 0045; FIG. 1 depicts a configuration example of a pixel 1 in an imaging element that measures distance by the ToF (Time of Flight) method using the SPAD], and
a timing at which the reflected light is received by the light detector, wherein the light detector includes a single-photon avalanche diode (SPAD) having one end connected to a first node, and configured to receive the reflected light [see para: 0047; The cathode of the SPAD 11 is connected with the source of the transistor 12 and with the input terminal of the inverter 21. The anode of the SPAD 11 is connected with a power source Vspad (not depicted). The drain of the transistor 12 is connected with a power source Ve (not depicted). The output terminal of the inverter 21 is connected with the input terminal of the inverter 22. The inverter 21 is supplied with an operating voltage from the power source Ve],
Allowable Subject Matter
Claims 8 and 9 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Eldesouki et al (US 8,410,416 B2)
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/MASUM BILLAH/Primary Patent Examiner, Art Unit 2486
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