DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
This Office action is in respond to Applicant’s amendment filed on 12/8/2025. Claims 1-20 are pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 10, 13-14 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lo et al. (US 9,977,612 B1, hereinafter Lo) in view of Prasad et al. (US 2022/0283954 A1, hereinafter Prasad) and Bernat et al. (US 10,990,480 B1, hereinafter Bernat).
Regarding claim 1, Lo discloses an apparatus as shown in figure 1, comprising: a memory device (figure 1, 150 and 160); and a controller (figure 1, 130) coupled with the memory device and configured to cause the apparatus to: write data to a plurality of contiguous pages of a non-volatile memory device of a memory system (col. 4 lines 25-47, the controller can be configured to receive data and/or storage access commands including write commands which can specify a logical address used to access the data storage system such that it can write data to a plurality of contiguous pages of a non-volatile memory device of a memory system); write an entry to a change log associated with updating logical-to-physical mapping information associated with the data (col. 5 lines 2-30, changes reflected by logs stored later in memory can correspond to more recent changes to the volatile copy of the system data than those reflect by the earlier stored logs comprise mappings or associations between logical and physical addresses in the data storage system, such as associations between logical chunk numbers (LCNs) and physical chunk number (PCNs), associations between logical block addresses (LBAs) and PCNs, and the like such that the entry of the change log comprising a first indication of a virtual block that comprises the plurality of contiguous pages); and update the logical-to-physical mapping information associated with the data based at least in part on the entry of the change log (figure 5 and col. 7 line 56 through col. 8 line 39, generate logs to record changes to the system data stored in the non-volatile memory array). Lo differs from the claimed invention in not specifically teaching that the entry of the change log comprising a first indication of a virtual block that comprises the plurality of contiguous pages and a second indication of a quantity of the plurality of contiguous pages. However, Prasad teaches a method comprising: receiving an indication of a total number of pages desired to be reclaimed from a plurality of virtual memory areas (VMAs) of a shared memory system, wherein a contiguity-aware translation lookaside buffer (TLB) maintains respective sets of TLB entries mapping contiguous regions of virtual memory pages of the plurality of VMAs to corresponding contiguous regions of physical memory pages ([0094]) in order to maintain the contiguity of virtual to physical address mappings. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Lo in having that that the entry of the change log comprising a first indication of a virtual block that comprises the plurality of contiguous pages and a second indication of a quantity of the plurality of contiguous pages, as per teaching of Prasad, in order to maintain the contiguity of virtual to physical address mappings. The combination of Lo and Prasad differs from the claimed invention in not specifically teaching the entry of the change log comprising a third indication of a logical address associated with the data. However, Bernat teaches a rebuild operation to reconstruct the data to improve the performance of a storage system for updating a mapping data structure to associate a logical address associated with the reconstructed data to the physical address of the data blocks storing the reconstructed data (col. 62 lines 15-32). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Lo and Prasad in having the entry of the change log comprising a third indication of a logical address associated with the data, as per teaching of Bernat, in order to improve the performance of a storage system.
Regarding claim 10, Lo discloses that the entry of the change log comprises a fourth indication of whether the data corresponding to the entry of the change log is valid, and the logical-to-physical mapping information associated with the data is updated based at least in part on the fourth indication indicating that the data is valid (col. 7 lines 46-55, applying changes recorded in those logs that are valid, which can be bounded by a threshold).
Regarding claim 13, Lo discloses that a set of logical addresses, i.e., contiguous address, where host data can be stored (col. 4 lines 36-47) such that one of ordinary skill in the art would recognize the plurality of contiguous pages comprising a plurality of contiguous 4 kilobyte chunks of data. In addition, Prasad teaches TLB entries to map the region with normal TLBs when backed by 4K pages ([0003]).
Regarding claim 14, the limitations of the claim are rejected as the same reasons as set forth in claim 1.
Regarding claim 19, the limitations of the claim are rejected as the same reasons as set forth in claim 10.
Regarding claim 20, the limitations of the claim are rejected as the same reasons as set forth in claim 1.
Claims 2 and 15 are rejected under 35 U.S.C. 103 as being unpatentable over Lo et al. (US 9,977,612 hereinafter Lo) in view of Prasad et al. (US 2022/0283954 hereinafter Prasad) and Bernat et al. (US 10,990,480 B1, hereinafter Bernat) as applied in claims above, and further in view of Amato (US 2019/0370169).
Regarding 2, the combination of Lo, Prasad and Bernat differs from the claimed invention in not specifically teaching that the controller is further configured to cause the apparatus to: store a mapping between a set of indexes used as indications of the virtual block in the entry and identifiers of virtual blocks, wherein the first indication of the virtual block comprises a first index mapped to an identifier of the virtual block. However, Amato teaches an index located in the first L2P mapping table using the hash functions may then be used to locate a physical location of a corresponding physical block address in the second L2P mapping table ([0019]) in order to easily identify a logical sector of data. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Lo, Prasad and Bernat in having that the controller is further configured to cause the apparatus to: store a mapping between a set of indexes used as indications of the virtual block in the entry and identifiers of virtual blocks, wherein the first indication of the virtual block comprises a first index mapped to an identifier of the virtual block, as per teaching of Amato, in order easily identify a logical sector of data.
Regarding claim 15, the limitations of the claim are rejected as the same reasons as set forth in claim 2.
Claims 5 and 17 are rejected under 35 U.S.C. 103 as being unpatentable over Lo et al. (US 9,977,612 hereinafter Lo) in view of Prasad et al. (US 2022/0283954 hereinafter Prasad) and Bernat et al. (US 10,990,480 B1, hereinafter Bernat) as applied in claims above, and further in view of Durham et al. (US 2019/0042799 hereinafter Durham).
Regarding claim 5, the combination of Lo, Prasad and Bernat differs from the claimed invention in not specifically teaching that the first indication of the virtual block comprises a first quantity of bits that is less than a second quantity of bits of an identifier of the virtual block. However, Durham teaches to set the meta-data tags to a value corresponding to the pointer's virtual address identification tag, and set the small object tag indicator bit in the pointer's virtual address ([0047]) in order to prevent use-after-free of the previous pointer identification tags. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Lo, Prasad and Bernat in having the first indication of the virtual block comprises a first quantity of bits that is less than a second quantity of bits of an identifier of the virtual block, as per teaching of Durham, in order to prevent use-after-free of the previous pointer identification tags.
Regarding claim 17, the limitations of the claim are rejected as the same reasons as set forth in claim 5.
Claims 6 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Lo et al. (US 9,977,612 hereinafter Lo) in view of Prasad et al. (US 2022/0283954 hereinafter Prasad) and Bernat et al. (US 10,990,480 B1, hereinafter Bernat) as applied in claims above, and further in view of Mulani et al. (US 2019/0012099 hereinafter Mulani).
Regarding claim 6, the combination of Lo, Prasad and Bernat differs from the claimed invention in not specifically teaching that the entry of the change log comprises a fourth indication of a page offset within the virtual block, the page offset indicating a first page of the plurality of contiguous pages to which the entry of the change log corresponds. However, Mulani teaches where data is stored contiguously, there may be an offset between the lowest address of a logical group and the lowest address of the metablock to which it is mapped ([0078]) such that there is an indication of a page offset within the virtual block, and the page offset indicating a first page of the plurality of contiguous pages to which the entry of the change log corresponds in order to minimize the time needed to access the address directory system in the volatile memory. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Lo, Prasad and Bernat in having the entry of the change log comprises a fourth indication of a page offset within the virtual block, the page offset indicating a first page of the plurality of contiguous pages to which the entry of the change log corresponds, as per teaching of Mulani, in order to minimize the time needed to access the address directory system in the volatile memory.
Regarding claim 18, the limitations of the claim are rejected as the same reasons as set forth in claim 6.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Lo et al. (US 9,977,612 hereinafter Lo) in view of Prasad et al. (US 2022/0283954 hereinafter Prasad), Bernat et al. (US 10,990,480 B1, hereinafter Bernat) and Mulani et al. (US 2019/0012099 hereinafter Mulani) as applied in claim 6 above, and further in view of Durham et al. (US 2019/0042799 hereinafter Durham).
Regarding claim 9, the combination of Lo, Prasad, Bernat and Mulani differs from the claimed invention in not specifically teaching that the fourth indication of the page offset comprises a first quantity of bits that is less than a second quantity of bits of the page offset. However, Durham teaches to set the meta-data tags to a value corresponding to the pointer's virtual address identification tag, and set the small object tag indicator bit in the pointer's virtual address ([0047]) in order to prevent use-after-free of the previous pointer identification tags. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Lo, Prasad, Bernat and Mulani in having that the fourth indication of the page offset comprises a first quantity of bits that is less than a second quantity of bits of the page offset, as per teaching of Durham, in order to prevent use-after-free of the previous pointer identification tags.
Allowable Subject Matter
Claims 3-4, 7-8, 11-12 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ZHUO H LI whose telephone number is (571)272-4183. The examiner can normally be reached Mon. Tue. and Thurs. 8:00-4:00 PM.
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/ZHUO H LI/Primary Examiner, Art Unit 2133