DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1, 3-4, 6-10, 12-13, and 15-20 are pending in this application. Claims 1, 10, and 17 are independent claims. This Office Action is Non-Final.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office Action has been withdrawn pursuant to 37 CFR 1.114. Applicant’s submission filed on 01/09/2026 has been entered.
Claim Objections
Claims 17-20 are objected to because of the following informalities.
Claim 17, lines 10-11 and line 13 recites “the plurality of I/O components” that is unclear if refers back to line 3 “a plurality of linked I/O components”? For purposes of this Office Action, the Examiner will interpret claim 17, line 10 as “the plurality of linked I/O components”. Appropriate correction is required.
Claims 18-20 depend on claim 17 and inherit the deficiencies of claim 17. Applicant may cancel the claims, amend the claims to place the claims in proper dependent form, rewrite the claims in independent form, or present a sufficient showing that these dependent claims comply with the requirements.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 10, 12-13, and 15-16 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 10, line 5; claim 10, line 8; claim 10, line 9 “the respective I/O component” lacks antecedent basis. Appropriate correction is required.
Claims 12-13 and 15-16 depend on claim 10 and inherit the deficiencies of claim 10. Applicant may cancel the claims, amend the claims to place the claims in proper dependent form, rewrite the claims in independent form, or present a sufficient showing that these dependent claims comply with the statutory requirements.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 3-4, 6-10, 12-13, and 15-20 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Baker, (U.S. Patent Publn Num. 2007/0109888 A1), hereinafter Baker.
Regarding claim 1, Baker teaches:
An apparatus, comprising:
a plurality of input/output (I/O) components (Baker, Fig. 1, memory components 100a-100x each include I/O components of Fig. 2 that paragraphs 0036-0038 describe as test circuit 150 that paragraph 0038 teaches has I/O pins/pads), each I/O component including:
an I/O pad (Baker, Fig. 2, paragraph 0038, I/O pin/pad 152);
a transceiver component (Baker, Fig. 2, transceiver 154, 156, 190) coupled to the I/O pad (Baker, Fig. 2, transceiver 154, 156, 190, paragraph 0038, 0042) via a first signal line (Baker, Fig. 2, paragraph 0038 I/O communications path 160); and
a respective first set of switches configured to selectively decouple, in an open position, a respective I/O component of the plurality of I/O components from another I/O component of the plurality of I/O components (Baker, Fig. 2, switch 164 in open position and 188 in open position decouples output result pad 186 that does not allow test circuit 150 in memory component zero 100a [i.e. different I/O component] (Baker, paragraph 0036) to connect to slave memory component two to memory component X (i.e. selectively decouple I/O component). Slave memory component one is respective I/O component and slave memory component two is another I/O component. Switch 188 is in open position as system is not working properly paragraph 0042 “Test system 102 reads the open/closed state of result switch 188 via an opens test, such as an open current test.” 164 is in open position by test system 102 (paragraph 0043) in test mode and not normal mode so I/O components selectively decoupled), which prevents a signal received at the respective I/O component from a different I/O component from being propagated to a respective transceiver component of the another I/O component (Baker, Fig. 1, Tester Driver 104 and 106, paragraphs 0026, 0031, 0037-0038 “I/O pad 152 is electrically coupled to one of the I/O pins 0-Y at 116 and to at least one other memory component 100, such as a master component or a slave component.” Fig. 2, test circuit 150 first set of switches 164, 188 is configured as described in previous claim mapping to decouple an I/O component which prevents signal propagation as shown in Fig. 9. Fig. 9 teaches each slave component is tested one at a time 276-286 with one slave component powered up and other slave components and master component are powered down. Thus, signal cannot propagate to other slave components [i.e. another I/O component] and in next loop of Fig. 9 flow chart paragraph 0063 teaches master memory component 100a is powered up and powered down, other slave components not being tested powered down and next slave component that is being tested is powered up);
wherein at least two I/O components of the plurality of I/O components are linked such that a signal can be transmitted between respective transceiver components of the at least two I/O components (Baker, Fig. 2, paragraph 0038, one I/O Component has Fig. 2 switch 158 connects 160 to 172 (“up”) and the receiver 154 and transmitter 156 (i.e. transceiver) couples to I/O pad 152 to form signal path that connects to slave Memory Component I/O pad 152 (second I/O component) that has switch 158 “up” so I/O components are linked and signal transmitted between transceivers 154, 156 of each I/O component).
Regarding dependent claim 3, Baker teaches wherein at least one of the plurality of linked I/O components comprises a respective second set of switches respectively coupled to a transmitter and a receiver (Baker, Fig. 2, switches 158 and 164), the respective second set of switches configured to selectively receive a signal for, or output a signal from, the at least one of the plurality of linked I/O components (Baker, Fig. 2, paragraphs 0036-0041).
Regarding dependent claim 4, Baker teaches the respective second set of switches is configured to, in an open position, decouple the at least one of the plurality of linked I/O components from a signal generator from which the signal is received (Baker, Fig. 1 Tester Driver 104 and 106 and Fig. 2, paragraph 0039 “I/O driver 156 receives data signals from the internal memory cells and I/O switch 158 [i.e. second set of switches 158 and 164] is controlled at 176 via a test mode control circuit (not shown) to direct the received internal data signals to I/O pin 152 or comparator circuit 166. The test mode control circuit is part of memory component 100 that includes test circuit 150.”); and
the respective second set of switches is configured to, in a closed position, couple the at least one of the plurality of linked I/O components to the signal generator (Baker, Fig. 1 Tester Driver 104 and 106, paragraph 0026 and Fig. 2, paragraph 0039).
Regarding dependent claim 6, Baker teaches wherein the at least two I/O components of the plurality of I/O components are linked in a daisy-chain configuration via the first respective set of switches of the at least two I/O components (Baker, Fig. 1, Test Drivers/Comparators 104 through link 118 shows daisy-chain or sequence or ring or series, see description in paragraphs 0025 and 0029, first respective set of switches 164 and 188 configured to couple at least two I/O components).
Regarding dependent claim 7, Baker teaches wherein:
the respective first set of switches is configured to, in an open position, decouple the at least one of the plurality of linked I/O components from the another I/O component of the plurality of linked I/O components (Baker, Fig. 1 Tester Driver 104 and 106, paragraph 0026 and Fig. 2, paragraph 0039); and
the respective first set of switches is configured to, in a closed position, couple the at least one of the plurality of linked I/O components to the another I/O component of the plurality of linked I/O components (Baker, Fig. 1 Tester Driver 104 and 106, paragraph 0026 and Fig. 2, paragraph 0039).
Regarding dependent claim 8, Baker teaches wherein the signal is a test signal (Baker, paragraph 0002 teaches memory test where signal is written to memory and read back), wherein the at least two I/O components of the plurality of I/O components are configured to be tested via the test signal provided to a first I/O component, and wherein the test signal is propagated from the first I/O component to a second I/O component (Baker, Fig. 1 Tester Driver 104 and 106, paragraph 0026 and Fig. 2, paragraph 0036-0043).
Regarding dependent claim 9, Baker teaches wherein the plurality of I/O components are configured to be tested via a test signal provided by a signal generator to an I/O pad of a first I/O component of the plurality of I/O components, and wherein the test signal is propagated to an I/O pad of a second I/O component of the plurality of I/O components (Baker, Fig. 2, paragraph 0038, I/O pin/pad 152 and Fig. 1 Tester Driver 104 and 106, paragraph 0026 and Fig. 2, paragraph 0036-0043).
Regarding claim 10, Baker teaches:
A system, comprising:
a test component (Baker, Fig. 1 Memory Component 100a-100x); and
a plurality of linked input/output (I/O) components coupled to one another and to the test component (Baker, Fig. 1, memory components 100a-100x each include I/O components of Fig. 2 that paragraphs 0036-0038 describe as test circuit 150 that paragraph 0038 teaches has I/O pins/pads), each I/O component of the plurality of linked I/O components comprises:
a respective first set of switches via which the respective I/O component is coupled to one or more I/O components of the plurality of linked I/O components (Baker, Fig. 2, switches 158 and 164, paragraphs 0036-0041); and
a respective second set of switches that are different from the respective first set of switches, the respective second set of switches via which the respective I/O component is coupled to one end of the respective I/O component (Baker, Fig. 2, first set of switches 164 and 158 connects to end with pin 152 and second set of switches is 188 and 158 which connects to end with pin 186. Switch 158 and 164 are different set of switches from set of switches 188 and 158 [i.e. second set of switches are “different” from first set of switches, different combination of the three switches into two sets]).
wherein the test component further comprises circuitry (Baker, Fig. 1 Memory Component 100a-100x, paragraph 0024 “the memory components 100 can be any suitable integrated circuit components.”) configured to:
transmit a test signal to a first I/O component of the plurality of linked I/O components to cause the test signal to be further transmitted to a second I/O component via one or more I/O components of the plurality of linked I/O components (Baker, Fig. 2, paragraph 0038);
receive the test signal from the second I/O component to determine whether the test signal transmitted to the first I/O component matches the test signal received from the second I/O component (Baker, paragraph 0034); and
reconfigure, in response to the test signal transmitted to the first I/O component not matching to the test signal received from the second I/O component (Baker, paragraph 0026 “Each of the slave components compares its own output signals against the master component output signals to obtain a test result that is read via test system 102.” Paragraph 0035 teaches “ If the test data received from a passing master memory component zero 100a does not match the test data of the slave memory component 100b-100x, the slave memory component 100b-100x fails the test indicating a defective memory component.”), the respective second set of switches of one or more I/O components of the plurality of linked I/O components to couple a subset of the plurality of linked I/O components to one another (Baker, paragraph 0033 teaches “In operation, test system controller 108 controls tester drivers 106 to program memory component zero 100a to operate in normal mode [master component]. Also, test system controller 108 controls tester drivers 106 to program memory components 100b-100x to operate in test mode [slave component].” Paragraph 0026 "To test memory components 100, the master component is put into normal mode and the slave components are put into test mode.” Fig. 3 shows configuration of switches in normal mode and Fig. 4 shows configuration of switches in test mode. Paragraphs 0061 and 0098 teach “slave memory components 100b-100x can be retested using a different master component.” Thus, one of the slave memory components 100b-100x is reconfigured as master component and that slave memory component switches from test mode to normal mode that requires reconfiguration of the set of switches to couple linked I/O components to each other (master is connected to each slave)).
Regarding dependent claim 12, Baker teaches wherein each I/O component of the plurality of linked I/O components comprises a respective I/O pad that is coupled to a different end than the one end (Baker, Fig. 2, I/O pad 152 and 186 is on two different ends of circuit 150).
Regarding dependent claim 13, Baker teaches wherein the circuitry is configured to:
enable at least one of the respective first set of switches of each I/O component to couple each I/O component to one another (Baker, Fig. 2 paragraphs 0036-0041); and
disable the respective second set of switches (Baker, Fig. 1 Tester Driver 104 and 106 and Fig. 2, paragraph 0039. Fig. 3, paragraph 0044 teaches normal mode in which switch 188 is disabled/up position to provide the impedance of result input receiver 190 at result pad 186, i.e. disable second set of switches).
Regarding dependent claim 15, Baker teaches wherein the circuitry is configured to:
transmit the test signal to a third I/O component of the subset of the plurality of linked I/O components that is located at a first end of the subset to cause the test signal to be further transmitted to a fourth I/O component located at a second end of the subset via one or more I/O components of the subset (Baker, Fig. 1 shows multiple memory component zero 100a to memory component x 100x connected through link 118 by tester driver/comparator 104 as described in paragraphs 0024-0035. Each memory component includes Fig. 2, test circuit 150 that are connected to each other); and
receive the test signal from the fourth I/O component to determine whether the test signal transmitted to the third I/O component of the subset matches the test signal received from the fourth I/O component (Baker, Figs 1-2, paragraphs 0024-0043).
Regarding claim 16, Baker teaches wherein the subset of the plurality of linked I/O components includes two I/O components (Baker, Fig. 1, Memory component zero to memory component one are linked and include I/O components of Fig. 2 [i.e. two I/O components where X is one]).
Regarding claim 17, Baker teaches:
A method, comprising:
transmitting, from a test component comprising circuitry (Baker, Fig. 1 Memory Component 100a-100x, paragraph 0024 “the memory components 100 can be any suitable integrated circuit components.”), a test signal to a first input/output (I/O) component of a plurality of linked I/O components to cause the test signal to be transmitted through the plurality of linked I/O components (Baker, Fig. 2, paragraph 0038);
receiving, at the test component, the test signal from a second I/O component of the plurality of linked I/O components to determine whether the test signal transmitted to the first I/O component matches the test signal received from the second I/O component (Baker, paragraph 0034); and
reconfiguring, by the test component and in response to the test signal transmitted to the first I/O component not matching to the test signal received from the second I/O component (Baker, paragraph 0026 “Each of the slave components compares its own output signals against the master component output signals to obtain a test result that is read via test system 102.” Paragraph 0035 teaches “ If the test data received from a passing master memory component zero 100a does not match the test data of the slave memory component 100b-100x, the slave memory component 100b-100x fails the test indicating a defective memory component.”), a topology of the plurality of linked I/O components to couple a subset of the plurality of I/O components to one another (Baker, paragraph 0033 teaches “In operation, test system controller 108 controls tester drivers 106 to program memory component zero 100a to operate in normal mode [master component]. Also, test system controller 108 controls tester drivers 106 to program memory components 100b-100x to operate in test mode [slave component].” Paragraph 0026 "To test memory components 100, the master component is put into normal mode and the slave components are put into test mode.” Fig. 3 shows configuration of switches in normal mode and Fig. 4 shows configuration of switches in test mode. Paragraphs 0061 and 0098 teach “slave memory components 100b-100x can be retested using a different master component.” Thus, one of the slave memory components 100b-100x is reconfigured as master component and that slave memory component switches from test mode to normal mode that is reconfiguring a topology of the plurality of linked I/O component to couple a subset of the plurality of I/O components to one another (master is connected to each slave), see also Fig. 9, testing of each slave component), which prevents a signal received at one I/O component of the subset from being propagated to a respective transceiver of each I/O component of a remaining subset of the plurality of I/O components (Baker, Fig. 1, Tester Driver 104 and 106, paragraphs 0026, 0031, 0037-0038 “I/O pad 152 is electrically coupled to one of the I/O pins 0-Y at 116 and to at least one other memory component 100, such as a master component or a slave component.” Fig. 2, test circuit 150 first set of switches 164, 188 is configured to decouple an I/O component which prevents signal propagation as shown in Fig. 9. Fig. 9 teaches each slave component is tested one at a time 276-286 with one slave component powered up and other slave components and master component are powered down. Thus, signal cannot propagate to other slave components [i.e. each I/O component] and in next loop of Fig. 9 flow chart paragraph 0063 teaches master memory component 100a is powered up and powered down, other slave components not being tested powered down and next slave component that is being tested is powered up).
Regarding dependent claim 18, Baker teaches further comprising, prior to transmitting the test signal to the first I/O component:
coupling the first I/O component to:
the test component via a first end of the first I/O component (Baker, Fig. 1, Memory component zero 100a, teaching a master component in paragraphs 0025-0038 that connects to test driver comparator 104 through link 118. Memory component 100 each include test circuit 150); and
one I/O component of the plurality of linked I/O components (Baker, Fig. 1, memory component zero 100a connects to memory component one 100b as taught in paragraphs 0025-0038. Memory component 100 each include test circuit 150); and
decoupling a second end of the first I/O component from the test component (Baker, paragraphs 0025-0038. Fig. 3, paragraph 0044 teaches normal mode in which switch 188 is disabled/up position to provide the impedance of result input receiver 190 at result pad 186, i.e. decouple second end 186 of the first I/O component).
Regarding dependent claim 19, Baker teaches further comprising, prior to transmitting the test signal to the first I/O component:
coupling the second I/O component to:
the test component via a first end of the second I/O component (Baker, Fig. 1, Memory component one 100b, teaching a slave component in paragraphs 0025-0038 that connects to test driver comparator 104 through link 118. Memory component 100 each include test circuit 150); and
one I/O component of the plurality of linked I/O components (Baker, Fig. 1, memory component one 100b connects to memory component two 100c as taught in paragraphs 0025-0038. Memory component 100 each include test circuit 150); and
decoupling a second end of the second I/O component from the test component (Baker, paragraphs 0025-0038).
Regarding dependent claim 20, Baker teaches further comprising decoupling the other I/O components of the plurality of linked I/O components from the test component to prevent the test signal from being transmitted to each one of the other I/O components (Baker, Fig. 1, Tester Driver 104 and 106, paragraph 0026, 0031, 0037 normal mode of operation).
Response to Arguments
Applicant’s arguments with respect to claims 1, 3-4, 6-10, 12-13, and 15-20 have been fully considered but are moot because of the new ground of rejection given in this office action for the amendments to the claims. Furthermore, Applicant's arguments filed 01/09/2026 with respect to claims 1, 10, and 17 have been fully considered but they are not persuasive.
Applicant recites in page 8, third paragraph “Applicant respectfully submits that drivers 156 and 190 are functionally irrelevant to receiving signals from the other memory components 100.” The Examiner respectfully disagrees that the other memory components do not transmit or receive signals through driver 156 and 190 as the claim mappings clearly describe this interaction and transfer of signals for the amended claims. Result pin 186 for each slave component sends a signal to the master component that uses this signal to determine how to proceed in Fig. 9, see paragraphs 0061-0063 of Baker. Thus, this argument is not persuasive and this rejection is respectfully maintained.
Applicant further argues on page 9, first paragraph “therefore, it [I/O driver 156] is not the structure that receives data/signals from other memory components …” However, signals are received and travel through this I/O driver 156 to I/O pin 152 and thus are “propagated” or “transmitted” as claimed in the independent claims and are taught by Baker as given in the claim mappings. Thus, this argument is not persuasive and this rejection is respectfully maintained.
Applicant recites and emphasizes the newly amended claim language in the remainder of pages 9 through 11 that the Examiner has fully considered and provided new claim mappings as given above. On page 10 Applicant argues that “In Baker, ‘I/O receiver 154’ still ‘sees’ signals from the other memory components 100 even when switches 158, 164, and 188 are in an open position.” However, the Examiner is respectfully unclear and puzzled as to why this is argued as it is not claimed and the claims do not use the word “see”, view or a similar pronoun? As described in the claim mappings with reference to Fig. 9, the switches are appropriately set and master and slave components are powered down so that no signal is received by receiver 154 with the exception of slave component under test. Thus, this argument is not persuasive and this rejection is respectfully maintained.
Applicant argues on page 11 that Baker does not teach “and a second set of switches that are different from the first set of switches, the second set of switches via which the respective I/O component is coupled to one end of the respective I/O component” as recited in independent claim 10…”. The Examiner’s interpretation under BRI of the claim 10 limitation “different from the first set of switches” is given in the corresponding claim mapping of claim 10. The Examiner under BRI interprets “different” from first set of switches as different combination of the three switches into two sets and claim 10 is rejected using this interpretation under BRI.
Applicant provides no other arguments for the remaining dependent claims and the Examiner respectfully maintains the rejections of these claims as given in the claim mappings above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicants’ disclosure. Applicants are required under 37 C.F.R. § 1.111(c) to consider these references fully when responding to this action.
Patil et al. (U.S. Patent Publn Num. 2012/0233504 A1) teaches a Test Access Mechanism (TAM) architecture for facilitating testing of IP blocks integrated on a System on a Chip (SoC). The TAM architecture includes a Test Controller and one or more Test Wrappers that are integrated on the SoC proximate to IP blocks. Test data and commands corresponding to input from an external tester are packaged by the Test Controller and sent to the Test Wrappers via an interconnect fabric. The Test Wrappers employ one or more test ports to provide test data, control, and/or stimulus signals to the IP block to facilitate circuit-level testing of the IP block. Test results for the circuit-level tests are returned to the Test Controller via the fabric. Test Wrappers may be configured to pass through interconnect signals, enabling functional testing of IP blocks to be facilitated via test packages and test results transmitted between the Test Controller and the IP blocks via the fabric.
It is noted that any citation to specific pages, columns, lines, or figures in the prior art references and any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck, 699 F.2d 1331, 1332-33, 216 U.S.P.Q. 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 U.S.P.Q. 275, 277 (C.C.P.A. 1968)).
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/INDRANIL CHOWDHURY/Examiner, Art Unit 2114
/ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114
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