DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is responsive to the claims dated 2/18/2024.
Claims 1-10 are presented for examination.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 2/18/2024 and 7/17/2024 have been considered by the examiner.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: the voltage designation "Vx", which first occurs in the description at as filed specification dated 2/18/2024 [0016] and occurs again at [0022]. [0016] states that the lower plate of the capacitor C1 will maintain the previous voltage level, identified as "Vx" shown in FIG. 3, and [0022] makes the same statement for the lower plate of the corresponding capacitor of the multiplication-accumulation circuit 400. FIG. 3 bears only the designations Vramp, x(t), y(t), t, T and t prime, together with the legends First phase, Second phase, Third phase and Time; the designation Vx does not appear in FIG. 3 or in any other figure. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either "Replacement Sheet" or "New Sheet" pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to under 37 CFR 1.83(a) because they fail to show the separate capacitors whose capacitances are 4C, 2C and 1C, and the transistor M1 and the transistor M2 associated with each of those capacitors, as described in the specification at [0018]. [0018] states that the switched-capacitor module of the multiplication-accumulation circuit 400 comprises a plurality of switches and a plurality of capacitors whose capacitances are 8C, 4C, 2C and 1C, and that the switch corresponding to the capacitor whose capacitance is 4C, 2C or 1C comprises a transistor M1 and a transistor M2. FIG. 4, however, shows a single capacitor symbol bearing the three reference characters 4C, 2C and 1C together with a single pair of transistors labeled M1 and M2, so that neither the three separate capacitors nor their respective switches are shown. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP Section 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as "amended." If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either "Replacement Sheet" or "New Sheet" pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
The drawings are objected to because FIG. 4 includes an element, depicted as a capacitor symbol in series with an open triangular symbol, that is connected to the node joining the transistor M4 and the upper plate of the capacitor whose capacitance is 8C. That element bears no reference character, carries no descriptive text label, has an unconnected terminal at the apex of the triangular symbol, and is not described anywhere in the specification, with the result that the element cannot be identified and the figure cannot be fully understood. Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as "amended." If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either "Replacement Sheet" or "New Sheet" pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: [0007] and [0009] each end without a period; [0007] and [0009] give word for word identical brief descriptions for FIG. 2 and for FIG. 4, each reciting a diagram illustrating a multiplication-accumulation circuit according to one embodiment of the present invention, so that the brief description of the several views does not distinguish the two views; [0016] and [0022] each recite "until the input signal x(t) does not the enabling state", which appears to omit a word; "does not have the enabling state" appears to be intended; [0017] and [0023] each recite "the charge accumulation at the at the upper plates", in which the words "at the" are duplicated; [0018] recites "the switched-capacitor module comprises plurality of switches", which appears to omit the article "a"; [0018] recites "a plurality of capacitors whose capacitance are 8C, 4C, 2C and 1C" and "the capacitor whose capacitance are 4C, 2C or 1C"; in each instance the subject and the verb do not agree; [0018] recites "corresponding weigh W[3]"; "weight" appears to be intended; [0019] recites "the transistor M5 is selectively connect the negative input terminal to the output terminal of the amplifier 412"; "is configured to selectively connect" appears to be intended; [0021] recites "to make the voltage levels the negative input terminal and the output terminal of the amplifier 412 be equal to the reference voltage", which appears to omit a word; [0022] recites "the capacitor whose capacitor is 8C"; "whose capacitance is 8C" appears to be intended; [0023] recites "causing the upper plates of the capacitors (i.e., the negative input terminal of the amplifier 412) is a charge conservation point"; the subject and the verb do not agree; [0023] refers to the charge accumulation at the upper plates of the capacitors C1 through CN, but [0023] describes the multiplication-accumulation circuit 400 of FIG. 4, whose capacitors are designated by the reference characters 8C, 4C, 2C and 1C; the reference characters C1 through CN designate the capacitors of the multiplication-accumulation circuit 200 of FIG. 2. [0024] recites "has smaller slope that the ramp signal Vramp"; "than" appears to be intended; [0002] and [0012] each recite that the processing of the node may suffer settling insensitive and interference issue, which is grammatically incomplete and is inconsistent with [0025], which refers to suppressing the settling and interference issue; the terms "switched capacitor module" ([0004] and [0022]) and "switched-capacitor module" ([0014] and [0018]) are used interchangeably for the same element.
Appropriate correction is required.
Claim Objections
Claims 2, 3 and 5 are objected to because of the following informalities:
Each of claims 2, 3 and 5 recites "selective connect" where the adverbial form "selectively connect" appears to be intended.
Appropriate correction is required.
Claim Rejections - 35 U.S.C. 112(a)
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 5 is rejected under 35 U.S.C. 112(a) as failing to comply with the written description requirement. The claim contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, at the time the application was filed, had possession of the claimed invention.
Claim 5 recites that when the multiplication-accumulation circuit operates in a second phase following the first phase, the first switched is disabled. The switch from which that limitation takes its antecedent basis is recited in claim 4 as a first switch, coupled between the input terminal and the output terminal of the amplifier. The only switch of that description anywhere in the disclosure is the transistor M5 of the buffer 410, which [0019] describes as selectively connecting the negative input terminal of the amplifier 412 to the output terminal of the amplifier 412 according to a reset signal RST.
The specification states the condition of that switch in each of the three recited phases, and in every instance it places the disabling of the switch in the third phase rather than the second. [0021] states that in the first phase the reset signal RST is enabled so that the transistor M5 connects the negative input terminal to the output terminal of the amplifier 412. [0022], which describes the second phase, states that the reset signal RST is also enabled so that the transistor M5 is enabled while the transistors M4 and M6 are disabled. [0023], which describes the third phase, states that the reset signal RST is disabled so that the transistor M5 is disabled while the transistors M4 and M6 are enabled. FIG. 4 agrees: the gate of the transistor M5 is driven by the reset signal RST, while the gates of the transistors M4 and M6 are driven by the inverted reset signal.
The disclosure therefore describes the first switch as remaining enabled throughout the second phase, which is the phase in which the bit-wise multiplication is performed, and as being disabled only upon entry into the third phase. No passage of the specification and no drawing describes the opposite arrangement. FIG. 3, the only timing diagram of record, shows the ramp signal Vramp, the input signal x(t) and the output delay signal y(t) across the first, second and third phases, and does not depict the reset signal or the condition of any switch of the buffer. The embodiment of FIG. 2 does not supply the missing description either: the buffer 210 of FIG. 2 is shown as a single amplifier symbol having no internal switch, and [0016] states only that in the first phase an input terminal and an output terminal of the buffer 210 are reset to have a reset voltage such as 0V, without describing any switch that performs the reset or the condition of such a switch during the second phase.
That claim 5 was presented as an original claim does not overcome the deficiency. There is a presumption that an adequate written description of the claimed invention is present when the application is filed, but an issue of adequate written description may arise even for an original claim where an aspect of the claimed invention has not been described with sufficient particularity such that one skilled in the art would recognize that the inventor had possession of the claimed invention at the time of filing (MPEP 2163, subsection II.A; MPEP 2163.03, subsection V; In re Wertheim, 541 F.2d 257, 263 (CCPA 1976)). The presumption is rebutted on this record because the specification does not merely omit the recited second-phase condition of the first switch, it describes the contrary condition, and it identifies the disabling of that switch as the event that, in the third phase, establishes the charge conservation point at the amplifier input ([0023]). One of ordinary skill in the art reading this disclosure would not recognize that the inventor had possession, at the time of filing, of a multiplication-accumulation circuit in which the first switch is disabled during the second phase (Ariad Pharmaceuticals, Inc. v. Eli Lilly and Co., 598 F.3d 1336, 1351 (Fed. Cir. 2010) (en banc); Vas-Cath Inc. v. Mahurkar, 935 F.2d 1555, 1563-64 (Fed. Cir. 1991)).
Applicant is invited to point out with particularity where the disclosure as originally filed conveys possession of the recited second-phase condition of the first switch, or to amend claim 5 so that it conforms to the operation the specification describes. No new matter may be added (35 U.S.C. 132(a)).
Claim Rejections - 35 U.S.C. 112(b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 1, the claim recites a switched capacitor module and then recites the switched capacitor as the element that is controlled by an input signal to receive a ramp signal to generate a voltage signal. This is a lack of antecedent basis and an ambiguous referent under MPEP Section 2173.05(e). Claim 1 introduces only "a switched capacitor module"; it never introduces a switched capacitor. A switched capacitor is itself a recognized structure in the art, namely a capacitor that is selectively connected through one or more switches, and claim 2 confirms that the recited module contains a plurality of capacitors, so the module and a switched capacitor within the module are two different things. It is therefore unclear whether the recitation refers to the switched capacitor module introduced immediately before it or to an individual switched capacitor inside that module that has not been positively recited. The two readings are not coextensive: under the first, the module as a whole must be controlled by the input signal to receive the ramp signal and generate the voltage signal, while under the second only a single capacitor within the module must do so, and the remainder of the module is left unconstrained. The claim set itself reflects the uncertainty, because claim 6 attributes receipt of the ramp signal to the switched capacitor module rather than to the switched capacitor, so two different expressions are used for what may or may not be the same element. Claim 1 recites the limitation "the switched capacitor" in the first recited element of the body of the claim, and there is insufficient antecedent basis for this limitation in the claim. See In re Packard, 751 F.3d 1307, 1314 (Fed. Cir. 2014); Nautilus, Inc. v. Biosig Instruments, Inc., 572 U.S. 898, 901 (2014). For examination purposes the limitation is interpreted as the switched capacitor module recited earlier in claim 1, that is, the module as a whole is controlled by the input signal to receive the ramp signal and to generate the voltage signal, which is how the specification describes the element at [0004] and [0014].
Regarding claims 3 and 5, each claim recites a limitation directed to what each switch is configured to do in connecting the ramp signal to the lower plate of the corresponding capacitor. The term is an ambiguous referent under. Claim 2, from which both claims descend, recites the counterpart limitation only "for at least a portion of the plurality of switches", whereas claims 3 and 5 drop that qualifier. It is therefore unclear whether each switch in claims 3 and 5 means every switch of the plurality of switches recited in claim 2 or only each switch of the at least a portion of that plurality, and those two readings define materially different scopes because the first requires the recited behavior of every switch in the module while the second requires it of an unquantified subset. In claim 5 the ambiguity is compounded, because claim 4 introduces a first switch coupled between the input terminal and the output terminal of the amplifier. Read literally, each switch in claim 5 would include that first switch, yet the same limitation of claim 5 states that the first switch is disabled during the second phase, so the claim would at once require the first switch to be disabled and to be connecting the ramp signal to the lower plate of a capacitor. A person of ordinary skill in the art is not informed with reasonable certainty which switches the limitation reaches. See Nautilus, Inc. v. Biosig Instruments, Inc., 572 U.S. 898, 910 (2014). For examination purposes the term is interpreted as each switch of the at least a portion of the plurality of switches recited in claim 2, and as excluding the first switch recited in claim 4, consistent with specification [0014], [0015] and [0022], which describe the switches of the switched-capacitor module as the elements that selectively connect the ramp signal to the lower plates of the capacitors and describe the amplifier reset switch separately.
Regarding claim 5, the claim recites that when the multiplication-accumulation circuit operates in a second phase following the first phase, the first switched is disabled. This is a lack of antecedent basis. No element called a first switched is recited in claim 5 or in any claim from which claim 5 depends, and the word switched is used as a noun without any recited referent. The nearest candidate antecedent is the first switch recited in claim 4, but the written description forecloses rather than confirms that reading. Specification [0019] identifies the switch coupled between the negative input terminal and the output terminal of the amplifier 412 as the transistor M5, which is controlled by the reset signal RST. Specification [0022] then states that in the second phase the reset signal RST is also enabled so that the transistor M5 is enabled, and specification [0023] states that the transistor M5 is disabled only in the third phase. Claim 5 places the disabling of the first switched in the second phase, so the disclosure describes the only candidate element as being enabled at precisely the point where the claim requires an element to be disabled. Reading the claim in light of the specification therefore does not resolve which element must be disabled during the second phase, and the scope of the claim is indeterminate. Claim 5 recites the limitation "the first switched" in the second-phase limitation, and there is insufficient antecedent basis for this limitation in the claim. For examination purposes the limitation is interpreted as the first switch recited in claim 4, and the second-phase limitation is interpreted as requiring that first switch to be open during the second phase, notwithstanding the contrary description of the transistor M5 at specification [0022].
Regarding claim 5, the claim recites that when the multiplication-accumulation circuit operates in a first phase, the first switch is enabled to make voltage levels input terminal and the output terminal of the amplifier be equal to the reference voltage. Words appear to have been omitted, and as written the limitation does not state what is made equal to the reference voltage. This is indefiniteness. The term voltage levels is recited with no antecedent basis and with no recited relationship to the terminals that follow it, and input terminal is recited without the definite article even though claim 4 introduced an input terminal of the amplifier. The limitation is open to at least three readings: that the voltage level at the input terminal and the voltage level at the output terminal are each made equal to the reference voltage; that only the output terminal is made equal to the reference voltage while voltage levels input terminal names some further element that has not been recited; or that some other unstated relationship among the voltage levels, the input terminal and the output terminal is required. The specification does not resolve the ambiguity, because specification [0021] carries the same omission, reciting an operation to make the voltage levels the negative input terminal and the output terminal of the amplifier 412 be equal to the reference voltage. A person of ordinary skill in the art would not be informed with reasonable certainty of the scope of the first-phase limitation. See Nautilus, Inc. v. Biosig Instruments, Inc., 572 U.S. 898, 901, 910 (2014); In re Packard, 751 F.3d 1307, 1314 (Fed. Cir. 2014). For examination purposes the limitation is interpreted as requiring that, in the first phase, the first switch be closed so that the voltage level at the input terminal of the amplifier and the voltage level at the output terminal of the amplifier are both equal to the reference voltage, which is the arrangement shown in FIG. 4, where the transistor M5 shorts the negative input terminal of the amplifier 412 to its output terminal, and which is the operation described at specification [0021].
Regarding claim 5, the claim recites that a charge accumulation occurs at upper plates of the capacitors to generate the voltage signal for the buffer. The recitation of the capacitors is an ambiguous referent. Claim 2 recites a plurality of capacitors within the switched capacitor module, and claim 4, from which claim 5 depends, recites a first capacitor coupled between the input terminal and the output terminal of the amplifier. It is unclear whether the capacitors means only the plurality of capacitors of the switched capacitor module or whether it also encompasses the first capacitor of claim 4. The distinction is not academic: the recited charge accumulation is what generates the voltage signal, so the two readings identify different structures as the site of the accumulation that produces the claimed signal. For examination purposes the limitation is interpreted as the upper plates of the plurality of capacitors of the switched capacitor module recited in claim 2, and as excluding the first capacitor recited in claim 4, consistent with specification [0017] and [0023], which locate the charge accumulation at the upper plates of the capacitors C1 through CN of the switched-capacitor module.
Claims 2, 6 and 10 depend from claim 1, claims 3 and 4 depend from claim 2, claim 5 depends from claim 4, claims 7 and 9 depend from claim 6, and claim 8 depends from claim 7. Each of claims 2-10 therefore incorporates the limitation of claim 1 addressed above and does not cure the defect in that limitation, and each is rejected under 35 U.S.C. 112(b) for the same reason.
Claim Rejections - 35 U.S.C. 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 4, 6-7, and 9-10 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Demasius et al. (hereinafter Demasius), US 2025/0247107 A1.
Regarding independent claim 1, Demasius discloses a multiplication-accumulation circuit, comprising (Demasius: Abstract, "An arrangement of a pulse-width controlled vector-matrix multiplication unit and a method for its operation are disclosed."; the vector-matrix unit multiplies input values by matrix weights and accumulates the results):
a switched capacitor module, wherein the switched capacitor module (interpreted per the 35 U.S.C. 112(b) rejection set forth above) is controlled by an input signal to receive a ramp signal to generate a voltage signal (Demasius: Abstract and Figs. 1-2, "A voltage ramp generator is coupled to the word lines via switches that are controlled by the input pulse width"; the input-block switches (11) and the adjustable matrix capacitors (10) are the switched capacitor module, and their totalized charge establishes the voltage at the input of the amplifier (7), [0045], “The word lines are provided which voltage ramps”);
a buffer, configured to receive the voltage signal to generate a buffered signal (Demasius: Abstract and Fig. 2, "The amplifier in the output block operates as a non-inverting amplifier in conjunction with the matrix capacitors"; the output-block amplifier (7), with its back-coupled capacitance (8) and the switch in parallel with that capacitance is a buffer that receives the matrix-capacitor voltage and generates its buffered output); and
a voltage-to-delay converter, configured to convert the buffered signal to an output delay signal having delay time information (Demasius: [0020] and Fig. 2 [0045], "means of a comparator, and corresponds to the output pulse length"; the comparator (9) at the output of the amplifier (7) is a voltage-to-delay converter that converts amplifier voltage to a time-coded output pulse).
Regarding dependent claim 2, Demasius further discloses the multiplication-accumulation circuit of claim 1, wherein the switched capacitor module comprises a plurality of switches and a plurality of capacitors (Demasius: Abstract and Figs. 1-2, "The system includes an input block connected to word lines of a matrix formed from non-volatile adjustable capacitors, and output blocks including amplifiers with inverting inputs and feedback capacitors with parallel switches"; the matrix has plural adjustable capacitors (10) and corresponding input-block switches (11), which are the same capacitors and switches identified as the switched capacitor module for claim 1); and for at least a portion of the plurality of switches, each switch is configured to [[selective]]selectively (interpreted per the Claim Objections set forth above) connect the ramp signal to a lower plate of the corresponding capacitor according to the input signal (Demasius: Abstract and Figs. 1-2, "A voltage ramp generator is coupled to the word lines via switches that are controlled by the input pulse width", [0045], “The word lines are provided which voltage ramps”; each word-line switch (11) selectively couples the ramp (12) to the word-line terminal of its corresponding capacitor (10), which is the terminal opposite the bit-line terminal that feeds the amplifier (7) and is therefore a lower plate of the corresponding capacitor according to the input signal).
Regarding dependent claim 4, Demasius further discloses the multiplication-accumulation circuit of claim 2, wherein the buffer comprises: an amplifier, configured to receive the voltage signal and a reference voltage to generate the buffered signal (Demasius: [0018] and [0034], "This means that the adjustable capacitors (Cm) are connected in parallel with the non-inverting input of the amplifier", and "the inverting amplifier is restored to its original voltage at different time points"; the output-block amplifier (7), with its back-coupled capacitance (8) and the switch in parallel with that capacitance comprises (wherein the buffer comprises) the amplifier (7) receives at its input the voltage totalized by the switched capacitor module and operates from and returns to its original voltage, which is a fixed reference level and not the reverse voltage ramp (14), and the output of the amplifier (7) is the buffered signal);
a first capacitor, coupled between an input terminal and an output terminal of the amplifier; and a first switch, coupled between the input terminal and the output terminal of the amplifier (Demasius: Abstract and Fig. 2, "The system includes an input block connected to word lines of a matrix formed from non-volatile adjustable capacitors, and output blocks including amplifiers with inverting inputs and feedback capacitors with parallel switches"; Fig. 2 shows feedback capacitor 8 and its parallel switch across the amplifier input and output).
Regarding dependent claim 6, Demasius further discloses the multiplication-accumulation circuit of claim 1, wherein the ramp signal received by the switched capacitor module is a first ramp signal (Demasius: Abstract, "A voltage ramp generator is coupled to the word lines via switches that are controlled by the input pulse width"; this input-side ramp is the first ramp); and the voltage-to-delay converter converts the buffered signal to the output delay signal having the delay time information according to a second ramp signal. (Demasius: Abstract, "A second phase of operation involves a reference capacitor and a reverse voltage ramp generator connected to the inverting input of the amplifier"; the comparator (9) at the output of the amplifier (7) (the voltage-to-delay converter) wherein the reverse ramp is the second ramp that times the comparator output pulse (converts the buffered signal to the output delay signal) to a time-coded output pulse (having the delay tie information) because of the reverse ramp signal (according to a second ramp signal)).
Regarding dependent claim 7, Demasius further discloses the multiplication-accumulation circuit of claim 6, wherein the second ramp signal is different from the first ramp signal (Demasius: Abstract and [0045], "A second phase of operation involves a reference capacitor and a reverse voltage ramp generator connected to the inverting input of the amplifier"; the second ramp is a reverse ramp applied in a different phase and through a different capacitor path than the input voltage ramp to the word lines).
Regarding dependent claim 9, Demasius further discloses the multiplication-accumulation circuit of claim 6, wherein the voltage-to-delay converter comprises a comparator, the comparator compares a combined signal with a reference voltage to generate the output delay signal, (Demasius: [0032]-[0034] and Fig. 2, "This time point is ascertained by means of the comparator, and is output in the form of a pulse length"; the comparator (9) at the output of the amplifier (7) (the voltage-to-delay converter) comprises a comparator 9 that detects restoration to the original reference level (compares a combined signal with a reference voltage) and produces the pulse-length output (to generate the output delay signal)), and the combined signal is generated by the second ramp signal and the buffered signal (Demasius: [0034] and Fig. 2, "the ramp of the second phase consistently remains constant, the inverting amplifier is restored to its original voltage at different time points."; the reverse second ramp acts through the reference capacitor on the existing amplifier output, forming the compared combined signal).
Regarding dependent claim 10, Demasius further discloses the multiplication-accumulation circuit of claim 1, wherein the multiplication-accumulation circuit is used in a node of an artificial neural network (Demasius: [0003], "The storage cells are arranged in matrix form, and represent coefficients, and input values are applied on the horizontal lines, which are word lines. The accumulation operation is generally executed according to Kirchhoff's law, wherein the output currents of storage cells are totalized", [0004], “Assemblies of this type are primarily applied in the calculation of artificial neural networks or the solution of differential equations”, [0022] and title, "The weights of a neural network are thus split into"; the neural-network weights are computed in the disclosed vector-matrix multiplication nodes).
Claim Rejections - 35 U.S.C. 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Demasius in view of Srivastava et al. (hereinafter Srivastava), US 2021/0240442 A1.
Regarding dependent claim 3, Demasius teaches the multiplication-accumulation circuit of claim 2, wherein the input signal is a delay signal (Demasius: Abstract, "A voltage ramp generator is coupled to the word lines via switches that are controlled by the input pulse width"; wherein the inputs to the word lines (wherein the input signal) are timed pulse width time-delay information (is a delay signal)).
Demasius does not expressly teach each switch of the at least a portion of the plurality of switches (interpreted per the 35 U.S.C. 112(b) rejection set forth above) is configured to [[selective]]selectively (interpreted per the Claim Objections set forth above) connect the ramp signal to the lower plate of the corresponding capacitor according to the input signal and a corresponding weight.
However, Srivastava teaches each switch of the at least a portion of the plurality of switches is configured to selectively connect the ramp signal to the lower plate of the corresponding capacitor according to the input signal and a corresponding weight (Srivastava: [0009] FIG. 2A illustrates a multiply-and-accumulate circuity including an array of compute-in-memory bitcells, [0021], "An active-low input vector bit on a pre-charge word line PCWL controls the gate of first pass transistor P1", [0023], "If the pre-charge word line is discharged due to the true value of the input vector bit and the stored bit is also true, pass transistor P1 will switch on to charge the second plate of the capacitor C to the power supply voltage VDD", [0018], "On the other hand, if the input vector bit and the stored bit have complementary values, neither the first pass transistor nor the second pass transistor is switched on during the calculation phase"; the drain of pass transistor P1 (each switch) of an array of compute-in-memory bitcells (of the at least a portion of the plurality of switches) is connected to the second plate of the capacitor C, that being the plate opposite the first plate commoned to the read bit line RBL at which the column result appears (is configured to selectively connect the ramp signal to the lower plate of the corresponding capacitor), the gate of that pass transistor is driven by the input vector bit carried on the pre-charge word line PCWL (according to the input signal) and its source is the true output node Q of the cross-coupled inverters 105 holding the stored bit that the array forms into a matrix multiplied with an input vector din 225 (and a corresponding weight), so the connection to that plate is made only where the input vector bit and the stored bit both call for it and is not made at all where the two have complementary values).
Because Demasius and Srivastava are analogous art and within the same field of endeavor, specifically capacitive multiply-and-accumulate hardware that multiplies input values by stored matrix weights, they address the same problem solving area of performing the weighted multiplication at the capacitor itself rather than in a separate multiplier, accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to combine Srivastava's joint input-bit and stored-bit gating of the capacitor plate connection with Demasius's input-block switches (11), which connect the voltage ramp (12) to the word-line terminal of the adjustable capacitor (10) under the input pulse length (2) alone, with a reasonable expectation of success, such that each such switch connects that ramp to that terminal only where the time-coded input and the stored weight both call for it, to teach and each switch of the at least a portion of the plurality of switches is configured to selectively connect the ramp signal to the lower plate of the corresponding capacitor according to the input signal and a corresponding weight. This modification would have been motivated by the desire to obtain advantageous full-rail capacitor charging (Srivastava: [0020]).
Regarding dependent claim 5, Demasius teaches the multiplication-accumulation circuit of claim 4, wherein when the multiplication-accumulation circuit operates in a second phase following the first phase, each switch of the at least a portion of the plurality of switches (interpreted per the 35 U.S.C. 112(b) rejection set forth above) is configured to [[selective]]selectively (interpreted per the Claim Objections set forth above) connect the ramp signal to the lower plate of the corresponding capacitor according to the input signal (Demasius: [0032], "According to a favorable embodiment, in a first phase, a voltage ramp is applied to the bit lines of the matrix, which is controlled by the input pulse length"; the input-block switches (11) connect the voltage ramp (12) to the word-line terminal of the adjustable capacitor (10) under the input pulse length (2), the phase numbering of Demasius being a label while the disclosed order and functions correspond to the claimed ramp-operation phase); the output delay signal having delay time information (Demasius: [0020], "The duration of this second phase is determined by means of a comparator, and corresponds to the output pulse length"; the comparator (9) at the output of the amplifier (7) converts that voltage into an output time pulse whose length carries the value).
Demasius does not expressly teach when the multiplication-accumulation circuit operates in a first phase, the first switch is enabled to make voltage levels of the (interpreted per the 35 U.S.C. 112(b) rejection set forth above) input terminal and the output terminal of the amplifier be equal to the reference voltage; and when the multiplication-accumulation circuit operates in a second phase following the first phase, the first [[switched]]switch is [[disabled]]enabled (interpreted per the 35 U.S.C. 112(a)/(b) rejections set forth above); and when the multiplication-accumulation circuit operates in a third phase following the second phase, a charge accumulation occurs at upper plates of the plurality of capacitors (interpreted per the 35 U.S.C. 112(b) rejection set forth above) to generate the voltage signal for the buffer to generate the buffered signal, and the voltage-to-delay converter converts the buffered signal to the output.
However, Srivastava teaches when the multiplication-accumulation circuit operates in a first phase, the first switch is enabled to make voltage levels of the input terminal and the output terminal of the amplifier be equal to the reference voltage (Srivastava: [0009] FIG. 2A illustrates a multiply-and-accumulate circuity including an array of compute-in-memory bitcells, [0022], "During the reset phase, a reset signal carried on a reset line is asserted to close a switch S1 connected between the read bit line and a node for the power supply voltage VDD"; asserting the reset signal in the reset phase of multiply-and-accumulate circuity (when the multiplication-accumulation circuit operates in a first phase) closes switch S1 and holds the read bit line RBL, the node commoned to the first plates of the capacitors C, at a fixed level (the first switch is enabled to make voltage levels of the input terminal and the output terminal of the amplifier be equal to the reference voltage)); and when the multiplication-accumulation circuit operates in a second phase following the first phase, the first switch is enabled (Srivastava: [0009] FIG. 2A illustrates a multiply-and-accumulate circuity including an array of compute-in-memory bitcells, [0018], "During a calculation phase following the reset phase, the read word line is discharged to switch off the reset transistor while the read bit line remains charged to the power supply voltage VDD", [0023], "In a calculation phase to calculate the binary multiplication of the stored bit and the input vector bit, pre-charge word line and the complement pre-charge word line are charged according to the value of the input vector bit while the reset signal is asserted to keep the read bit line charged to the power supply voltage VDD"; the calculation phase of multiply-and-accumulate circuity follows the reset phase and the reset signal remains asserted across that boundary, so switch S1 stays closed); and when the multiplication-accumulation circuit operates in a third phase following the second phase, a charge accumulation occurs at upper plates of the plurality of capacitors to generate the voltage signal for the buffer to generate the buffered signal, and the voltage-to-delay converter converts the buffered signal to the output (Srivastava: [0024], "An accumulation phase follows the calculation phase. In the accumulation phase, the read word line is asserted while the reset signal is de-asserted", [0025], "apply across a column of compute-in-memory bitcells in a multiply-and-accumulate circuit", [0026], "Each compute-in-memory bitcell 100 in column 230 either maintains the charge of its capacitor or discharges its capacitor depending upon the multiplication result and affects the voltage of the read bit line (RBL) during the accumulation phase accordingly"; the accumulation phase of multiply-and-accumulate circuity is the third of the reset, calculation and accumulation phases, and de-asserting the reset signal in it opens switch S1 and isolates the read bit line so that the charge retained on the capacitors C sets the voltage at their commoned first plates, which Srivastava denotes the accumulation voltage and identifies as the analog result output of the multiplication).
Because Demasius and Srivastava are analogous art and within the same field of endeavor, specifically phased capacitive multiply-and-accumulate circuits that preset a summing node, perform an input-dependent capacitor operation, and read an accumulated analog result, they address the same problem solving area of holding the summing node at a fixed level while the input-dependent operation proceeds and releasing it only when the accumulated result is to be read, accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to combine Srivastava's ordered reset, calculation, and accumulation sequence with Demasius's switch connected in parallel with the back-coupled capacitance (8) of the amplifier (7), with a reasonable expectation of success, such that that switch is closed through the first and second phases at the original voltage of the amplifier (7) and is released in the third phase, in which the bit-line terminals of the adjustable capacitors (10) become a charge conservation point and the amplifier (7) and the comparator (9) of Demasius then buffer that accumulated voltage and convert it to the output pulse length as mapped for claim 1, to teach when the multiplication-accumulation circuit operates in a first phase, the first switch is enabled to make voltage levels of the input terminal and the output terminal of the amplifier be equal to the reference voltage; and when the multiplication-accumulation circuit operates in a second phase following the first phase, the first switch is enabled; and when the multiplication-accumulation circuit operates in a third phase following the second phase, a charge accumulation occurs at upper plates of the plurality of capacitors to generate the voltage signal for the buffer to generate the buffered signal, and the voltage-to-delay converter converts the buffered signal to the output delay signal having delay time information. This modification would have been motivated by the desire to obtain a stable preset followed by an isolated accumulation from which the analog multiplication result is read (Srivastava: [0027]).
Claim 8 is rejected under 35 U.S.C. 103 as being unpatentable over Demasius, as applied in the rejection of claim 7, in view of Hashimoto et al. (hereinafter Hashimoto), (US 2017/0006247 A1).
Regarding dependent claim 8, Demasius teaches all the elements of claim 7.
Demasius does not expressly teach wherein a slope of the second ramp signal is smaller than a slope of the first ramp signal.
However, Hashimoto teaches wherein a slope of the second ramp signal is smaller than a slope of the first ramp signal (Hashimoto: [0032], "The second ramp signal has a smaller slope (time-dependent change rate) than the first ramp signal VH").
Because Demasius and Hashimoto are analogous art, Hashimoto being reasonably pertinent to the problem with which the inventor was concerned, specifically converting a voltage into a time interval by ramping a reference against it and detecting the crossing with a comparator, they address the same problem solving area of obtaining adequate resolution in that conversion, accordingly, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention, to combine Hashimoto's shallower reference ramp and its stated slope-to-resolution relationship with Demasius's reverse voltage ramp (14) applied through the reference capacitor (13) at the comparator (9), with a reasonable expectation of success, such that the ramp that fixes the time at which the amplifier (7) is restored to its original voltage, and hence the output pulse length (Demasius: [0034], "the ramp of the second phase consistently remains constant, the inverting amplifier is restored to its original voltage at different time points. This time point is ascertained by means of the comparator, and is output in the form of a pulse length"), is made shallower than the voltage ramp (12), whose length is instead set by the input pulse length (2) in performing the multiplication (Demasius: [0045], "The length of voltage ramps is controlled by means of switches (11) in the input block and by the input pulse length (2)"), to teach wherein a slope of the second ramp signal is smaller than a slope of the first ramp signal. This modification would have been motivated by the desire to increase the resolution of the time-coded output in the known proportion Hashimoto states, the slope ratio being selected to meet the resolution required (Hashimoto: [0030] and [0032]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Buchanan et al., US 2018/0095748 A1 (Apr. 5, 2018) (ABSTRACT An example device may include multiply-accumulate circuitry and voltage-tracking modulator circuitry. The multiply-accumulate circuitry may be to increase and decrease an accumulation voltage held by an accumulator based on a number of input signals. The voltage-tracking modulator circuitry may be to generate an output signal based on the accumulation voltage, wherein the output signal is a continuous-time binary signal that tracks changes of the accumulation voltage by varying pulse widths of the output signal. The example device may be used as a neuron in a neural network).
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/KC CHEN/Primary Patent Examiner, Art Unit 2143
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