DETAILED ACTION
The current Office Action is in response to the papers submitted 03/31/2026. Claims 1 – 11, 13 – 18, and 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 – 6, 9 – 11, 13, 15, 17 – 18, and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishiyama (Pub. No.: US 2018/0121136) referred to as Ishiyama in view of Chiu (Pub. No.: US 2018/0322041) referred to as Chiu.
Regarding claim 1, Ishiyama teaches an apparatus [1, Fig 1], comprising:
one or more memory devices [3, Fig 1]; and
a controller [4, Fig 1] coupled with the one or more memory devices [3, Fig 1] and configured to cause the apparatus [1, Fig 1] to:
receive, as part of a programming command sequence associated with a programming mode [Fig 13; Data from the host is programmed into the SSD making figure 13 a programming mode], a first command indicating a plurality of logical block address ranges [Fig 11; Color MANAGEMENT COMMAND, Fig 13; Paragraphs 0175 – 0181 and 0187 – 0190; The color management command from the host includes multiple LBA ranges and parameters for the LBA ranges] associated with the apparatus [1, Fig 1];
receive, as part of the programming command sequence associated with the programming mode [Fig 13; Data from the host is programmed into the SSD making figure 13 a programming mode], a plurality of second commands, each second command comprising respective data associated with a respective logical block address range of the plurality of logical block address ranges [WRITE COMMAND, Fig 13; S401 – S402; Paragraphs 0190 – 0192; Steps S302 – S306 are performed for any number of write commands after the Color Table is generated]; and
write, for each respective logical block address range, the respective data to physical addresses [Paragraph 0068; Data is written to physical addresses of memory] of the one or more memory devices [3, Fig 1] in accordance with the plurality of second commands [S305, Fig 13; S411, Fig 18; The data in write commands are written to physical locations based the logical block address range and associated color from the Color Table].
However, Ishiyama may not specifically disclose the limitation(s) of the programming mode comprises a pre-soldering activity programming mode or an in-system programming mode.
Chiu discloses the programming mode comprises a pre-soldering activity programming mode [Paragraph 0020; Data is programmed into memory before the memory is soldered making the mode of writing a pre-soldering mode] or an in-system programming mode.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Chiu in Ishiyama, because it provides a test to make sure the memory device is resistant to the soldering process which can introduce defects in the memory device [Paragraphs 0003 and 0023].
Regarding claim 2, Ishiyama teaches to receive the first command [Fig 11; Color MANAGEMENT COMMAND, Fig 13; Paragraphs 0175 – 0181 and 0187 – 0190], the controller [4, Fig 1] is configured to cause the apparatus [1, Fig 1] to:
receive an indication of a total quantity of logical block address ranges of the plurality of logical block address ranges, a total quantity of logical block addresses of the plurality of logical block address ranges, a respective starting logical block address for each logical block address range of the plurality of logical block address ranges, a respective total quantity of logical block addresses for each logical block address range of the plurality of logical block address ranges, or any combination thereof [Fig 11; Color MANAGEMENT COMMAND, Fig 13; Paragraphs 0175 – 0181 and 0187 – 0190; A range of LBA addresses would include an indication of a starting address for each range and an end range of LBA addresses to define the ranges. The starting and end addresses of a range is also an indication of number of addresses in a range].
Regarding claim 3, Ishiyama teaches the controller [4, Fig 1] is further configured to cause the apparatus [1, Fig 1] to:
determine whether the first command is part of the programming command sequence [Fig 13] based at least in part on a mode parameter included in the first command, the mode parameter of the first command associated with the programming mode of the apparatus [1, Fig 1; Figs 9, 11, and 13; S501, Fig 19; The system is able to determine the command received is a color management command based on a parameter defining it from a write command. The LBA range parameter differentiates the color management command from the write command. The information sent from the host is associated with the programming mode allowing the memory to store the data received from the host]; and
determine, for each second command of the plurality of second commands, whether each second command is part of the programming command sequence based at least in part on a mode parameter included in each second command, the mode parameter of each second command associated with the programming mode of the apparatus [1, Fig 1; Figs 9, 11, and 13; S401, Fig 18; The system is able to determine the command received is a write command based on a parameter defining it from a color management command. The starting LBA parameter differentiates the write command from the color management command].
Regarding claim 4, Ishiyama teaches to receive the plurality of second commands [WRITE COMMAND, Fig 13; S401 – S402; Paragraphs 0190 – 0192; Steps S302 – S306 are performed for any number of write commands after the Color Table is generated], the controller [4, Fig 1] is configured to cause the apparatus [1, Fig 1] to:
receive, via each second command of the plurality of second commands [WRITE COMMAND, Fig 13; S401 – S402; Paragraphs 0190 – 0192; Steps S302 – S306 are performed for any number of write commands after the Color Table is generated], a buffer offset indicating the respective logical block address range to which each second command corresponds, a size parameter indicating a total quantity of logical block addresses included in the respective logical block address range, or a combination thereof, wherein writing the respective data to the physical addresses [S305, Fig 13] of the one or more memory devices [3, Fig 1] is based at least in part on the buffer offset, the size parameter [S302, Fig 13], or the combination thereof [Fig 9; S302, Fig 13; The start LBA is an offset within a range of where to start writing data associated with the start LBA. Data length is a size parameter indicating a size of a range of LBAs desired to be written].
Regarding claim 5, Ishiyama teaches the controller [4, Fig 1] is further configured to cause the apparatus [1, Fig 1] to:
release one or more resources of a volatile memory device [6, Fig 1] of the apparatus [1, Fig 1] based at least in part on receiving the first command [S412, Fig 18, Updating the LUT releases a resource in the LUT from containing previous data. The mapping that is released and updated is based in part on the color management command which sets the parameters used in the decisions in figure 18 before the release and update in step S412]; and
update, using the one or more released resources and before writing the respective data to the physical addresses, logical-to-physical mapping information associated with the respective data based at least in part on the first command [Fig 13; S401 – S402; S412, Fig 18; Paragraphs 0190 – 0192; Steps S302 – S306 are performed for any number of write commands after the Color Table is generated. The LUT is logical-physical mapping information and a previous write would update the LUT before the writing the respective data of a second write command].
Regarding claim 6, Ishiyama teaches the controller [4, Fig 1] is further configured to cause the apparatus [1, Fig 1] to:
disable, in association with writing the respective data to the physical addresses [Paragraph 0068; S411, Fig 18], a change log manager of the apparatus, logical-to-physical table management [S412, Fig 18] by the apparatus [1, Fig 1], or both, based at least in part on updating the logical-to-physical mapping information [S412 and END, Fig 18; Once the data is written and the mapping information in the LUT is updated further mapping table management is disabled by the writing process ending until another write operation is received].
Regarding claim 9, Ishiyama teaches to write the respective data to the physical addresses [Paragraph 0068; Data is written to physical addresses of memory], the controller [4, Fig 1] is further configured to cause the apparatus [1, Fig 1] to:
determine a type of memory cell to which to write the respective data, one or more trim parameters associated with writing the respective data to the type of memory cell, or both, based at least in part on a quantity of the respective data, wherein writing the respective data to the physical addresses is in accordance with the determination [Fig 9; Fig 11; S302, Fig 13; Fig 16; S405, Fig 18; Paragraph 0222 - 0227; The length of data in a write indicates a LBA range which is used along with the table 33D determine a type of memory cell to write data based on the program erase counts of the memory cells].
Regarding claim 10, Ishiyama teaches the controller [4, Fig 1] is further configured to cause the apparatus [1, Fig 1] to:
refrain from performing, after writing the respective data to the physical addresses, one or more read checks on the respective data written to the physical addresses of the one or more memory devices [S411 – S412, Fig 18; After the data is written the LUT is updated without performing a read check on the written data].
Regarding claim 11, Ishiyama teaches the controller [4, Fig 1] is further configured to cause the apparatus [1, Fig 1] to:
update logical-to-physical mapping information associated with each of the respective data based at least in part on completing the plurality of second commands [S412, Fig 18; The LUT is mapping information that is associated with all data written and is updated after each write and after multiple writes are completed. A last write of multiple writes causes the LUT to update data associated with all the writes since the LUT contains mapping information for each write]; or
update, based at least in part on writing one of the respective data, logical-to- physical mapping information associated with the one of the respective data [S412, Fig 18; The LUT is mapping information that is associated with all data written and is updated after each write and after multiple writes are completed. A last write of multiple writes causes the LUT to update data associated with all the writes since the LUT contains mapping information for each write].
Regarding claim 13, Ishiyama teaches an apparatus [1, Fig 1], comprising:
one or more memory devices [3, Fig 1]; and
a controller [4, Fig 1] coupled with the one or more memory devices [3, Fig 1] and configured to cause the apparatus [1, Fig 1] to:
write, to a register of the apparatus operating in a programming mode [Fig 13; Data from the host is programmed into the SSD making figure 13 a programming mode], a value of a quantity of logical block addresses associated with writing data while operating in the programming mode [Fig 11; Paragraphs 0175 – 0181 and 0187 – 0190; The LBA ranges each represent a number of logical block addresses and are stored showing the use of a register or equivalent structure to store the LBA ranges];
receive a plurality of commands to write the data associated with the quantity of logical block addresses while operating in the programming mode [WRITE COMMAND, Fig 13; S401 – S402; Paragraphs 0190 – 0192; Data from the host is programmed into the SSD making figure 13 a programming mode. Steps S302 – S306 are performed for any number of write commands after the Color Table is generated];
write the data to physical addresses [Paragraph 0068; Data is written to physical addresses of memory] of the one or more memory devices [3, Fig 1] in accordance with the plurality of commands while operating in the programming mode [S305, Fig 13; S411, Fig 18; Data from the host is programmed into the SSD making figure 13 a programming mode. The data in write commands are written to physical locations based the logical block address range and associated color from the Color Table]; and
exit the programming mode based at least in part on the value and writing the data [Figs 13 and 18; The programming mode ends after the number of logical blocks indicated in the write have been written with data].
However, Ishiyama may not specifically disclose the limitation(s) of the programming mode comprises a pre-soldering activity programming mode or an in-system programming mode.
Chiu discloses the programming mode comprises a pre-soldering activity programming mode [Paragraph 0020; Data is programmed into memory before the memory is soldered making the mode of writing a pre-soldering mode] or an in-system programming mode.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Chiu in Ishiyama, because it provides a test to make sure the memory device is resistant to the soldering process which can introduce defects in the memory device [Paragraphs 0003 and 0023].
Regarding claim 15, Ishiyama teaches the controller [4, Fig 1] is further configured to cause the apparatus [1, Fig 1] to:
store, to a volatile memory device [6, Fig 1] of the apparatus [1, Fig 1], logical block addresses associated with each command of the plurality of commands based at least in part on the apparatus [1, Fig 1] operating in the programming mode [Fig 13; Data from the host is programmed into the SSD making figure 13 a programming mode]; and
update, after a completion of the plurality of commands, logical-to-physical mapping information associated with the data using the logical block addresses stored to the volatile memory device [6, Fig 1; S306, Fig 13; S412, Fig 18; The LUT, stored in volatile memory, stores logical address from write commands and is updated after write commands are completed].
Regarding claim 17, Ishiyama teaches to write the respective data to the physical addresses [Paragraph 0068; Data is written to physical addresses of memory], the controller [4, Fig 1] is further configured to cause the apparatus [1, Fig 1] to:
determine, based at least in part on the apparatus operating in the programming mode [Fig 13; Data from the host is programmed into the SSD making figure 13 a programming mode], a type of memory cell to which to write the data, one or more trim parameters associated with writing the data to the type of memory cell, or both, based at least in part on a quantity of the data, wherein writing the data to the physical addresses is in accordance with the determination [Fig 9; Fig 11; S302, Fig 13; Fig 16; S405, Fig 18; Paragraph 0222 - 0227; The length of data in a write indicates a LBA range which is used along with the table 33D determine a type of memory cell to write data based on the program erase counts of the memory cells].
Regarding claim 18, Ishiyama teaches the controller [4, Fig 1] is further configured to cause the apparatus [1, Fig 1] to:
refrain from performing, after writing the data to the physical addresses and based at least in part on the apparatus operating in the programming mode [Fig 13; Data from the host is programmed into the SSD making figure 13 a programming mode], one or more read checks on the data written to the physical addresses [S411 – S412, Fig 18; After the data is written the LUT is updated without performing a read check on the written data].
Claim 20 is medium corresponding to claim 1 and is rejected using the same prior art and similar reasoning. Ishiyama discloses a medium that stores instructions that are processed by a processor [Paragraph 0074 - 0075].
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishiyama (Pub. No.: US 2018/0121136) referred to as Ishiyama in view of Chiu (Pub. No.: US 2018/0322041) referred to as Chiu as applied to claim 5 above, and further in view of Palmer (Pub. No.: US 2021/0294752) referred to as Palmer.
Regarding claim 7, Ishiyama teaches the controller [4, Fig 1] is further configured to cause the apparatus [1, Fig 1] to:
updating logical-to-physical mapping information [S306, Fig 13; S412, Fig 18] of a range of logical block addresses [Fig 11; Color MANAGEMENT COMMAND, Fig 13; Paragraphs 0175 – 0181 and 0187 – 0190; The logical block addresses or organizes in ranges based on parameters].
However, Ishiyama in view of Chiu may not specifically disclose the limitations of compressing one or more sequential logical block address ranges of the plurality of logical block address ranges, wherein updating the logical-to-physical mapping information is based at least in part on compressing the one or more sequential logical block address ranges.
Palmer discloses compressing one or more sequential logical block address ranges of the plurality of logical block address ranges, wherein updating the logical-to-physical mapping information is based at least in part on compressing the one or more sequential logical block address ranges [Figs 3 – 6; Figures 5A – 6 show updated mapping tables as a result of compressing sequential logical block address ranges from the mapping tables in figures 3 – 4D].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Palmer in Ishiyama in view of Chiu, because it allows the size of the mapping table to be decreased since only the starting address of sequential locations need to be mapped [Paragraph 0025].
Claim(s) 8 and 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishiyama (Pub. No.: US 2018/0121136) referred to as Ishiyama in view of Chiu (Pub. No.: US 2018/0322041) referred to as Chiu as applied to claims 1 and 13 above, and further in view of Suh et al. (Pub. No.: US 2019/0324850) referred to as Suh.
Regarding claim 8, Ishiyama teaches the controller [4, Fig 1] is further configured to cause the apparatus [1, Fig 1] to:
controlling how writes are performed [Fig 18] based on the first command [Fig 11; Color MANAGEMENT COMMAND, Fig 13; Paragraphs 0175 – 0181 and 0187 – 0190; The color management command sets parameters that are used when a write is executed].
However, Ishiyama in view of Chiu may not specifically disclose the limitations of disabling one or more error correction procedures associated with writing the respective data based at least in part on receiving the first command, the one or more error correction procedures comprising generation of error correction code data, parity data, redundancy data, or any combination thereof.
Suh discloses disabling one or more error correction procedures associated with writing the respective data based at least in part on receiving the first command, the one or more error correction procedures comprising generation of error correction code data, parity data, redundancy data, or any combination thereof [Figs 2 – 4; Steps 410, 415, 420, and 425 are when the bits in figures 2 and 3 are set indicating if error correction is enabled or not. Step 430 and 435 perform write operations based on the bits enabling or disabling error correction].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Suh in Ishiyama in view of Chiu because it allows different levels of data protection to be applied as needed based on operating environment of the system to balance the cost and benefits of data protection [Paragraph 0025].
Regarding claim 16, Ishiyama teaches the controller [4, Fig 1] is further configured to cause the apparatus [1, Fig 1] to:
controlling how writes are performed [Fig 18] based on the command information before a write is received [Fig 11; Color MANAGEMENT COMMAND, Fig 13; Paragraphs 0175 – 0181 and 0187 – 0190; The color management command sets parameters that are used when a write is executed] while in a programming mode [Fig 13; Data from the host is programmed into the SSD making figure 13 a programming mode].
However, Ishiyama in view of Chiu may not specifically disclose the limitation(s) of disable, based at least in part on the apparatus operating in the programming mode, one or more error correction procedures associated with writing the data, the one or more error correction procedures comprising generation of error correction code data, parity data, redundancy data, or any combination thereof.
Suh discloses disable, based at least in part on the apparatus operating in the programming mode, one or more error correction procedures associated with writing the data, the one or more error correction procedures comprising generation of error correction code data, parity data, redundancy data, or any combination thereof [Figs 2 – 4; Steps 410, 415, 420, and 425 are when the bits in figures 2 and 3 are set indicating if error correction is enabled or not. Step 430 and 435 perform write operations based on the bits enabling or disabling error correction. Figure 4 is a programming mode].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Suh in Ishiyama in view of Chiu because it allows different levels of data protection to be applied as needed based on operating environment of the system to balance the cost and benefits of data protection [Paragraph 0025].
Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Ishiyama (Pub. No.: US 2018/0121136) referred to as Ishiyama in view of Chiu (Pub. No.: US 2018/0322041) referred to as Chiu.
Regarding claim 14, Ishiyama teaches the controller [4, Fig 1] is further configured to cause the apparatus [1, Fig 1] to:
exit the programming mode based at least in part on the value and writing the data [Figs 13 and 18; The programming mode ends after the number of logical blocks indicated in the write have been written with data].
However, Ishiyama in view of Chiu may not specifically disclose the limitation(s) of decrementing the value based at least in part on performing a command of the plurality of commands, wherein exiting the programming mode is based at least in part on decrementing the value to zero.
It would have been obvious to decrement the value based at least in part on performing a command of the plurality of commands, wherein exiting the programming mode is based at least in part on decrementing the value to zero. The decrementing would allow the system to know when all the data in the write command has been written. Going from step S411 to S412 shows a mechanism used to know that the write in S411 has been completed. To know when a write is completed is generally performed by two methods: counting the amount of data written or counting the number of addresses written or not written with regard to the write request. Decrementing the value of the number of logical block address is counting the number of logical blocks that need to be written.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the decrementing of the value of the number of logical block addresses and ending the write operation based in part on the value being zero because there is a limited number of ways to know when a write is completed. Decrementing the number of logical block addresses that need to be written is one of the limited number of ways and would have a high level of predictability by a person of ordinary skill in the art. It would also be reasonable to try decrementing the number of logical block addresses in the write command since one or ordinary skill in the art would readily know how to do the decrementing.
Response to Arguments
Applicant's arguments filed 03/31/2026 have been fully considered but they are not persuasive.
The applicant argues on pages 10 – 11 that claims 1, 13, and 20 are allowed since amendments to the claims add limitations from cancelled claim 12 that Ishiyama was indicated as not teaching. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The applicant’s arguments are moot in view of the new grounds of rejection. The amendments have changed the scope of the claims requiring further search and consideration of the prior art. The new grounds of rejection are a result of the further search and consideration of the prior art. The examiner suggests amending the claims to include further details defining the inventive concept from the specification to overcome the cited prior art and further advance prosecution.
The applicant argues on page 12 that claims 2 – 6, 9 – 11, 15, and 17 – 18 are allowed for being dependent on argued allowed claims 1 and 13. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The examiner has responded to the arguments regarding base claims 1 and 13 showing how the prior art teaches the limitations of the base claims 1 and 13. The rejections of the argued claims are maintained based in part on the rejections of base claims 1 and 13.
The applicant argues on pages 12 – 17 that base claims 1, 13, and 20 and dependent claims 7 – 8, 14, and 16 are allowable since the writing in Ishiyama is performed during normal write operations and not while operating a in a programming mode including that comprises a pre-soldering activity programming mode or an in-system programming mode. The applicant also argues the combination fails to teach how Chiu includes a first command indicating a plurality of logical block address ranges or a plurality of second commands where each second command comprising data associated with a respective logical block address range of the plurality of logical block address ranges. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The arguments against each reference identify limitations in the claims that the references are not used to teach. The programming mode containing certain programming modes is taught by Chiu not Ishiyama. Similarly, the argued limitations of a first command indicating a plurality of logical block address ranges or a plurality of second commands where each second command comprising data associated with a respective logical block address range of the plurality of logical block address ranges are taught by Ishiyama not Chiu. There is no requirement that every limitation need to be taught by each reference individually in a combination rejection. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986).
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER D BIRKHIMER whose telephone number is (571)270-1178. The examiner can normally be reached 8-5 Hoteling.
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/Christopher D Birkhimer/ Primary Examiner, Art Unit 2138
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