Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1, 5, 7-9 and 12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Sun et al. (cited by the applicant), hereafter referred to as "Sun".
Regarding claim 1, in the embodiment in of Figs. 21A, Sun discloses:
A nested floating inverter dynamic amplifier (FIDA) (Figs. 1, 20A, and 21A) comprising:
a first FIDA amplifier (Fig. 21A, two-stage floating-inverter amplifier 2102a) comprising a plurality of first inverters (2102A, comprises 2 inverters) switchably coupled to a first reservoir capacitor (floating reservoir capacitors 106a, column 23 lines13-15, 106a and 106b are selected as inputs to the floating inverter amplifier via switches); and
a second FIDA amplifier (Fig. 21A, two-stage floating-inverter amplifier 2102b) comprising a plurality of second inverters (2102b, comprises of 2 inverters) switchably coupled to a second reservoir capacitor (floating reservoir capacitors 106b),
wherein outputs of the plurality of first inverters are coupled to corresponding inputs of the plurality of second inverters (outputs of inverters of 2102a are coupled to 2102b inverters).
Regarding claim 5, in the embodiment in of Figs. 1 and 21A, Sun discloses:
a controller (column 3 lines 29-34, in some embodiments the apparatus is configured as a microcontroller circuit device) configured to:
during a charging phase, charge the first reservoir capacitor and the second reservoir capacitor to a first voltage (Fig. 1, column 16 lines 29-30, floating reservoir capacitor CRES is pre-charged to VDD); and
during an amplification phase, connect the first reservoir capacitor to the plurality of first inverters and connect the second reservoir capacitor to the plurality of second inverters, wherein the first FIDA amplifier and the second FIDA amplifier are configured to float during the amplification phase (Figs. 21A and 21B, column 23, lines 18-26, during dynamic amplification phase the two amplifiers (2102a, 2102b) are turned on by respectively connecting their respective supply rails to the floating reservoir capacitors (i.e. floating as known in the art).
Regarding claim 7, in the embodiment in of Fig. 21A, Sun discloses:
an input of each second inverter of the plurality of second inverters (Fig. 21A, 2102b inverters) is coupled to its corresponding output (as shown in Fig. 21A).
Regarding claim 8, in the embodiment in of Figs. 1, 20A and 21A, Sun discloses:
at least one output capacitor coupled to outputs of the plurality of first inverters (Figs. 1, 20A, and 21A, integration capacitors CX are connected to the outputs of CMOS input-pairs M1-M4, which function as inverters of inverter-based input 104).
Regarding claim 9, in the embodiment in of Fig. 21A, Sun discloses:
A method of operating a nested floating inverter dynamic amplifier (FIDA) (Fig. 21A) comprising
a first FIDA amplifier (floating-inverter amplifier 2102a) comprising a plurality of first inverters (top and bottom inverters of 2012a) switchably coupled to a first reservoir capacitor (106a),
a second FIDA amplifier (floating-inverter amplifier 2102b) comprising a plurality of second inverters (top and bottom inverters of 2102b) switchably coupled to a second reservoir capacitor (106b),
wherein outputs of the plurality of first inverters are coupled to corresponding inputs of the plurality of second inverters (as shown in Fig. 21A),
the method comprising:
during a charging phase, charging the first reservoir capacitor and the second reservoir capacitor to a first voltage (column 23, lines 10-17, during reset phase the two reservoir capacitors 106a and 106b are pre-charged to the supply voltages); and
during an amplification phase, connecting the first reservoir capacitor to the plurality of first inverters and connecting the second reservoir capacitor to the plurality of second inverters, wherein the first FIDA amplifier and the second FIDA amplifier are configured to float during the amplification phase (Figs. 21A and 21B, column 23, lines 18-26, during dynamic amplification phase the two amplifiers (2102a, 2102b) are turned on by respectively connecting their respective supply rails to the floating reservoir capacitors).
Regarding claim 12, Sun discloses:
amplifying an input voltage applied to inputs of the plurality of first inverters during the amplification phase (column 22, lines 38-41).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 13, 14, 15, 16, 19-21 are rejected under 35 U.S.C. 103 as being unpatentable over Sun et al. (cited by the applicant) in view of Albinet (US 8928406 B2), hereafter referred to as “Sun” and “Albinet”, respectively.
Regarding claim 13, in the embodiment of Fig. 21A, Sun discloses:
A circuit comprising:
a first inverter (Fig. 21A, floating-inverter amplifier 2102a, top inverter) having an input coupled to a first input node (integration node VXP);
a first load inverter (floating-inverter amplifier 2102b, top inverter) coupled to an output of the first inverter, wherein an input of the first load inverter is connected to an output of the first load inverter (as shown in Fig. 21A);
a second inverter (floating-inverter amplifier 2102a, bottom inverter) having an input coupled to a second input node (integration node VXN);
a second load inverter (floating-inverter amplifier 2102b, bottom inverter) coupled to an output of the first inverter (as shown in Fig. 21A);
a first reservoir capacitor (floating reservoir capacitor 106a) switchably coupled to power supply nodes of the first inverter and the second inverter (power source VDD1); and
a second reservoir capacitor (floating reservoir capacitor 106b) switchably coupled to power supply nodes of the first load inverter and the second load inverter (power source VDD2).
Sun is however silent in teaching an input of the second load inverter (Fig. 3, inverter 306, OUTM1 is inputted to the input of 306) is connected to an output of the second load inverter (inverter 306, Column 3, OUTM1 is connected to inverter output OUTP1);
Albinet teaches:
an input of the second load inverter is connected to an output of the second load inverter (Fig. 3, Column 3, lines 17-36).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the invention to configure the inverter as taught by Sun (Figs. 20A and 21A) to connect the input of the load inverter to the load inverter output as taught by Albinet (Fig. 3, inverter 306) to allow for rail-to-rail operation on the with each output signal (Column 3, lines 17-36), thereby suggesting the obviousness of such a combination.
Regarding claims 14-16 and 19-21, Sun teaches:
As an obvious consequence of the above modification the result of the modification includes:
Regarding claim 14, Sun teaches:
a ratio of a strength of the first inverter to a strength of the first load inverter is a first factor;
a ratio of a strength of the second inverter to a strength of the second load inverter is the first factor (Fig. 6, floating inverter amplifier 102, column 22 lines 57-60, since current flow through PMOS and NMOS are forced to be the same, the strengths of input transistors are equalized); and
a ratio of a capacitance of the first reservoir capacitor to a capacitance of the second reservoir capacitor is the first factor (column 23 lines 30-31, overall transfer function is set by capacitor ratio).
Regarding claim 15, Sun teaches:
the first inverter comprises a first NMOS transistor and a first PMOS transistor;
the first load inverter comprises a first NMOS load transistor and a first PMOS load transistor;
the second inverter comprises a second NMOS transistor and a second PMOS transistor; and
the second load inverter comprises a second NMOS load transistor and a second PMOS load transistor (column 3 lines 49-58, the floating inverter amplifier comprises a pair of inverters (e.g., dynamically-biased PMOS and a dynamically-biased NMOS) forming a bridge).
Regarding claim 16, Sun teaches:
during a reset phase:
disconnect the first reservoir capacitor from the power supply nodes of the first inverter and the second inverter and connect power supply terminals configured to provide a power supply voltage across terminals of the first reservoir capacitor, and
disconnect the second reservoir capacitor from the power supply nodes of the first load inverter and the second load inverter and connect the power supply terminals across terminals of the second reservoir capacitor (column 23 lines 12-18, During reset phase, floating reservoir capacitors 106a and 106b are selected as inputs to floating inverter amplifier via switches); and
during an amplification phase
disconnect the first reservoir capacitor from the power supply terminals and connect the terminals of the first reservoir capacitor to the power supply nodes of the first inverter and the second inverter , and
disconnect the second reservoir capacitor from the power supply terminals and connect the terminals of the second reservoir capacitor to the power supply nodes of the first load inverter and the second load inverter (Figs. 21A and 21B, column 23, lines 18-26, during dynamic amplification phase the two amplifiers (2102a, 2102b) are turned on by respectively connecting their respective supply rails to the floating reservoir capacitors).
Regarding claim 19, Sun teaches:
a first switch coupled between a first terminal of the first reservoir capacitor and a first power supply terminal (Fig. 21A, 106a top switch directly connected to VDD1);
a second switch coupled between a second terminal of the first reservoir capacitor and a second power supply terminal (Fig. 21A, 106a bottom switch directly connected to ground);
a third switch coupled between a first terminal of the second reservoir capacitor and the first power supply terminal (Fig. 21A, 106b top switch directly connected to VDD2);
a fourth switch coupled between a second terminal of the second reservoir capacitor and the second power supply terminal (Fig. 21A, 106b bottom switch directly connected to ground);
a fifth switch coupled between the first terminal of the first reservoir capacitor and first power supply nodes of the first inverter and the second inverter (106a top switch directly connected to top and bottom inverter);
a sixth switch coupled between the second terminal of the first reservoir capacitor and second power supply nodes of the first inverter and the second inverter (106a bottom switch directly connected to bottom inverter);
a seventh switch coupled between the first terminal of the second reservoir capacitor and first power supply nodes of the first load inverter and the second load inverter (106b top switch directly connected to top and bottom inverter);
an eighth switch coupled between the second terminal of the second reservoir capacitor and second power supply nodes of the first load inverter and the second load inverter (106b bottom switch directly connected to top and bottom inverter);
a ninth switch coupled between the output of the first inverter and a reference voltage node (106a top inverter output connected to V¬CM top switch); and
a tenth switch coupled between the output of the second inverter and the reference voltage node (106a bottom inverter output connected to V¬CM bottom switch).
Regarding claim 20, Sun teaches:
an eleventh switch coupled between the output of the first inverter and at least one output capacitor (106a top inverter output is coupled through inverter 106b top inverter to 2102b V¬CM top switch that outputs to load capacitor Cl); and
a twelfth switch coupled between the output of the second inverter and the at least one output capacitor (106b bottom inverter output is coupled through inverter 106b bottom inverter to 2102b V-CM bottom switch that outputs to load capacitor Cl).
Regarding claim 21, Sun teaches:
during a reset phase
turning on the first, second, third, fourth, ninth and tenth switches, and
turning off the fifth, sixth, seventh, and eighth switches (Fig. 21A, column 23 lines 10-18, In reset phase, floating reservoir capacitors 106a and 106b are selected as inputs, Inverters are both off and outputs rest to VCM, which would require the first, second, third, fourth, ninth and tenth switches to be on); and
during an amplification phase
turning on the fifth, sixth, seventh, and eighth switches, and
turning off the first, second, third, fourth, ninth and tenth switches (Figs. 21A and 21B, column 23 lines 18-30, amplifiers 2102a and 2102b are turned on in the dynamic amplification phase by connecting their respective supply rails to reservoir capacitors, which means that only fifth, sixth, seventh, and eighth switches are on).
Allowable Subject Matter
Claims 2-4, 6, 10, 11, 17, 18 and 22 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2:
the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, “a ratio of a transconductance of the first FIDA amplifier to the second FIDA amplifier is a first factor”.
Regarding claims 6 and 10:
the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, “the controller is further configured to, during a readout phase, disconnect at least one output capacitor from the outputs of the plurality of first inverters”.
Regarding claim 17:
the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, “during the reset phase, couple at least one output capacitor and the outputs of the first inverter and the second inverter to a reference voltage node configured to provide a reference voltage; and
during the amplification phase, disconnect the at least one output capacitor and the outputs of the first inverter and the second inverter from the reference voltage node, and”.
Regarding claim 22:
the cited prior art of record, either singly or in proper combination, does not teach or make obvious, along with the other claimed features, “the controller is further configured to turn off the eleventh and twelfth switch during a readout phase”.
Claims 3, 4, 11, and 18 are objected to due to dependence on objected claims 2, 10, and 17.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MALANE LIENG whose telephone number is (571)272-5739. The examiner can normally be reached Monday-Friday 6:30 - 4:00 CST.
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/MALANE LIENG/ Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/ Supervisory Patent Examiner, Art Unit 2843