Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/09/2023 is acknowledged. The submission is in compliance with the provisions of 37 CFR 1.97.
Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 – 5, 7, 8, and 12 – 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Blednov (US 20180034418 A1).
Regarding Independent Claim 1, Blednov teaches,
A power amplification circuit (Fig. 3, 300) comprising:
a splitter (Fig. 3, 320, 314, and 316) that includes at least one variable inductance element (Fig. 3, 304, 302, 204, 308, 214) and at least one variable capacitance element (Fig. 3, 202, 206, 208, 306,216, and 218) [See paragraphs [0028], “The input power splitter may also include either a constant or variable inductance, a constant or variable capacitance, or both.” and [0060] “It is noted that amplifier stages 104 and 108, inductances 302, 204, 308, 214 and capacitances 202, 206, 306, 216 are implemented as an integrated circuit (e.g., integrated into the silicon) of semiconductor die 318.”] and that is configured to split a first signal (Fig. 3, signal at 102) into a second signal (Fig. 3, signal at 104) having a first power level (Fig. 3, power level of signal at 104) and a third signal (Fig. 3, signal at 108) having a second power level (Fig. 3, power level of signal at 108) based on a value of inductance of each of the at least one variable inductance element (Fig. 3, 304, 302, 204, 308, 214) and a value of capacitance of each of the at least one variable capacitance element (Fig. 3, 202, 206, 208, 306,216, and 218) [See paragraphs [0043], “In order to divide the input power levels in a manner that corresponds to the gain of the main and peak amplifier stages 104 and 108, a resistive element 310 is coupled to node 312 of the input power splitter 320… Resistive element 310 implements a power division ratio that provides one power level to the input of main amplifier stage 104 and a greater power level to the input of peak amplifier stage 108 to compensate for the lower gain of the peak amplifier stage 108… The tuning can be based on one or more of the operating parameters that include but are not limited to the ratio of the gain of the peak amplifier stage 108 to the gain of the main amplifier stage 104, a present frequency of an input (RF carrier) signal received by the Doherty amplifier device, a present amplitude of the envelope modulation of the input (RF carrier) signal, a present operating power level of the Doherty amplifier device, and any combination thereof. In some embodiments, the resistive value can be adjusted quickly (e.g., resistive element 310 has variable resistance) by a controller based on the operating parameters of the Doherty amplifier device 300, such as for the gain ratio between peak and main amplifier stages, for different input signal frequencies, different envelope amplitudes, different operating power levels, and any combination thereof.”];
a first amplifier (Fig. 3, 104) that is connected to the splitter (Fig. 3, 320, 314, and 318) and that is configured to amplify the second signal (Fig. 3, signal input of 104) and output a fourth signal (Fig. 3, signal output of 104);
a second amplifier (Fig. 3, 108) that is connected to the splitter (Fig. 3, 320, 314, and 318) and that is configured to amplify the third signal (Fig. 3, signal input of 108) and output a fifth signal (Fig. 3, signal output of 108) when the second power level is greater than or equal to a predetermined power level [See paragraphs [0042], “The input power splitter provides a power level to the peak amplifier stage 108 that is greater than the power level provided to the main amplifier stage 104 in order to compensate for the gain difference and improve gain linearity of the Doherty amplifier device 300. The power level provided to the peak amplifier stage 108 is proportional to the gain difference. Stated another way, as the gain difference between the main and peak amplifier stages 104 and 108 increases, the power level provided to the peak amplifier stage 108 increases.”]; and
a combiner (Fig. 3, 236) configured to combine the fourth signal and the fifth signal (Fig. 3, 236 receives both signals from 104 and 108, respectively, combines said signals, and outputs a combined signal at 112).
Regarding claim 2,
The power amplification circuit (Fig. 3, 300) according to Claim 1,
wherein the splitter (Fig. 3, 320, 314, and 316) is configured to
control the at least one value of inductance and the at least one value of capacitance to cause the second power level to be lower than the first power level (Fig. 3, 320, 314, and 316 implement a power division ratio that controls the power levels distributed to 104 and 108, thereby compensating 108 a lower gain with a greater power level) when a peak to average power ratio of the first signal is larger than a predetermined value [See paragraph [0042], “The input power splitter provides a power level to the peak amplifier stage 108 that is greater than the power level provided to the main amplifier stage 104 in order to compensate for the gain difference and improve gain linearity of the Doherty amplifier device 300. The power level provided to the peak amplifier stage 108 is proportional to the gain difference. Stated another way, as the gain difference between the main and peak amplifier stages 104 and 108 increases, the power level provided to the peak amplifier stage 108 increases.”], and
control the at least one value of inductance and the at least one value of capacitance to cause the second power level to be higher than the first power level (Fig. 3, 320, 314, and 316 implement a power division ratio that controls the power levels distributed to 104 and 108, thereby compensating 108 a lower gain with a greater power level) when the peak to average power ratio of the first signal is smaller than the predetermined value [See paragraph [0042], “The input power splitter provides a power level to the peak amplifier stage 108 that is greater than the power level provided to the main amplifier stage 104 in order to compensate for the gain difference and improve gain linearity of the Doherty amplifier device 300. The power level provided to the peak amplifier stage 108 is proportional to the gain difference. Stated another way, as the gain difference between the main and peak amplifier stages 104 and 108 increases, the power level provided to the peak amplifier stage 108 increases.”].
Regarding claim 3,
The power amplification circuit (Fig. 3, 300) according to Claim 1,
wherein operational states of the power amplification circuit include a first amplification mode in which a first supply voltage is provided to the first amplifier and the second amplifier [See paragraph [0016], “In a first operational state of Doherty amplifier 100, the input signal power level is above a power threshold level of peak amplifier stage 108 and both amplifier stages 104 and 108 are in an “on” state, where the output signal power level of the Doherty amplifier is at its maximum.”] and a second amplification mode in which a second supply voltage lower than the first supply voltage is provided to the first amplifier and the second amplifier [See paragraphs [0017], “In a second operational state of Doherty amplifier 100, the input signal power level is at or below the power threshold level of peak amplifier stage 108 (i.e., below the Doherty amplifier back-off power level), where the gain of peak amplifier stage 108 is ideally zero.”], and
the splitter (Fig. 3, 320, 314, and 316) is configured to control the at least one value of inductance and the at least one value of capacitance to cause the second power level to be higher than the first power level in the second amplification mode [See paragraph [0042], “The input power splitter provides a power level to the peak amplifier stage 108 that is greater than the power level provided to the main amplifier stage 104 in order to compensate for the gain difference and improve gain linearity of the Doherty amplifier device 300. The power level provided to the peak amplifier stage 108 is proportional to the gain difference. Stated another way, as the gain difference between the main and peak amplifier stages 104 and 108 increases, the power level provided to the peak amplifier stage 108 increases.”].
Regarding claim 4,
The power amplification circuit (Fig. 3, 300) according to Claim 3, further comprising:
a variable attenuator (Fig. 3, 202 and 302) disposed between the splitter and the first amplifier [See paragraph [0041], “Capacitance 202 and inductance 302 also provide signal attenuation at the input of main amplifier stage 104”].
Regarding claim 5,
The power amplification circuit (Fig. 3, 300) according to Claim 1,
wherein the splitter (Fig. 3, 320, 314, and 316) is configured to control the at least one value of inductance and the at least one value of capacitance based on a frequency of the first signal [See paragraph [0042], “The input power splitter provides a power level to the peak amplifier stage 108 that is greater than the power level provided to the main amplifier stage 104 in order to compensate for the gain difference and improve gain linearity of the Doherty amplifier device 300. The power level provided to the peak amplifier stage 108 is proportional to the gain difference. Stated another way, as the gain difference between the main and peak amplifier stages 104 and 108 increases, the power level provided to the peak amplifier stage 108 increases.”], and
the combiner (Fig. 3, 236) includes a variable impedance element [See paragraph [0022], “Capacitance 220, inductance 226, and capacitance 228 also implement a low-pass C-L-C network, which is used as an output combiner (e.g., of a symmetrical Doherty amplifier). If properly built (i.e., the proper capacitance and inductance values are selected), this C-L-C network is equivalent to an impedance inverter and provides a 90-degree phase shift of the signal and implements the optimal characteristic impedance Z0 (e.g., providing the functionality of a quarter-wavelength transmission line).”] that is disposed between the first amplifier (Fig. 3, 104) and the second amplifier (Fig. 3, 108) and that is configured to control a value of impedance based on the frequency.
Regarding claim 7,
The power amplification circuit (Fig. 3, 300) according to Claim 1, further comprising:
an input end (Fig. 3, 102), wherein the splitter (Fig. 3, 320, 314, and 316) includes
a first variable inductance element (Fig. 3, 302) including a first terminal connected to the input end (Fig. 3, 102) and a second terminal connected to the first amplifier (Fig. 3, 104),
a first variable capacitance element (Fig. 3, 206) including a third terminal connected to the first terminal and a fourth terminal grounded,
a second variable capacitance element (Fig. 3, 202) including a fifth terminal connected to the second terminal and a sixth terminal grounded,
a second variable inductance element (Fig. 3, 308) including a seventh terminal connected to the second terminal and an eighth terminal connected to the second amplifier (Fig. 3, 108),
a third variable inductance element (Fig. 3, 214) including a ninth terminal grounded and a tenth terminal connected to the eighth terminal,
a third variable capacitance element (Fig. 3, 216) including an eleventh terminal connected to the ninth terminal and a twelfth terminal grounded,
a fourth variable capacitance element (Fig. 3, 218) including a thirteenth terminal connected to the tenth terminal and a fourteenth terminal grounded, and
a fourth variable inductance element (Fig. 3, 304) including a fifteenth terminal connected to the input end (Fig. 3, 102) and a sixteenth terminal connected to the ninth terminal.
Regarding claim 8,
The power amplification circuit (Fig. 3, 300) according to Claim 1, wherein the at least one variable capacitance element includes a digitally tunable capacitor [See paragraph [0047], “The integrated circuitry on the semiconductor die implements an integrated circuit (such as the integrated circuit on die 318 including amplifier stages 104 and 108 and pre-matching networks 314 and 316), where example components of integrated circuitry include but are not limited to dielectric materials with conductive structures, pads, interconnects, analog circuitry, digital logic, standalone discrete devices such as resistors, inductors, capacitors, diodes, power transistors, the like, and combinations thereof.”].
Regarding claim 12,
The power amplification circuit (Fig. 3, 300) according to Claim 2, wherein the predetermined value is 6.0 dB [See paragraph [0067], “FIG. 8C illustrates the power division produced by the input power splitter as power distribution curves to the main and peak amplifier stages over the operational frequency bandwidth, each pair of curves associated with a different resistive value. The curves show that the difference between the power levels delivered to the main and peak amplifier stages can be adjusted from roughly 1 dB shown by bold lines (e.g., −7.3 at m9 and −8.3 at m8) to around 6 dB (e.g., −6.5 dB versus 12.25 dB at central frequency 2.5 GHz), by adjusting the resistive value of resistive element 310. Accordingly, input power splitter provides a wide range for varying the power division between the main and peak amplifier stages over the entire range of the operational frequency bandwidth. It is also noted that the power distribution of the input power splitter tends to increase with frequency, providing more power to the inputs of the main and peak amplifier stages. As such, this increasing trend compensates for the natural loss of gain (or so called “gain roll-off”) of the active devices and Doherty amplifier stages that occurs as frequency increases, due to device characteristics of the amplifier stages.”].
Regarding claim 13,
The power amplification circuit (Fig. 3, 300) according to Claim 1, wherein the first amplifier is configured to operate in Class AB mode [See paragraph [0013], “One amplifying device, or main amplifier stage 104, is biased to operate in a class AB amplifier mode (e.g., has gate bias conditions that implement a power dependent conduction angle between 180 to 360 degrees), and the other amplifying device, or peak amplifier stage 108, is biased to operate in a class C amplifier mode (e.g., has gate bias conditions that implement a power dependent conduction angle between 90 to 180 degrees).”].
Regarding claim 14,
The power amplification circuit (Fig. 3, 300) according to Claim 1, wherein the second amplified is configured to operate in Class C mode [See paragraph [0013], “One amplifying device, or main amplifier stage 104, is biased to operate in a class AB amplifier mode (e.g., has gate bias conditions that implement a power dependent conduction angle between 180 to 360 degrees), and the other amplifying device, or peak amplifier stage 108, is biased to operate in a class C amplifier mode (e.g., has gate bias conditions that implement a power dependent conduction angle between 90 to 180 degrees).”].
Regarding claim 15,
The power amplification circuit (Fig. 3, 300) according to Claim 2, wherein operational states of the power amplification circuit include a first amplification mode [See paragraph [0016], “In a first operational state of Doherty amplifier 100, the input signal power level is above a power threshold level of peak amplifier stage 108 and both amplifier stages 104 and 108 are in an “on” state, where the output signal power level of the Doherty amplifier is at its maximum.”] in which a first supply voltage is provided to the first amplifier and the second amplifier and a second amplification mode [See paragraphs [0017], “In a second operational state of Doherty amplifier 100, the input signal power level is at or below the power threshold level of peak amplifier stage 108 (i.e., below the Doherty amplifier back-off power level), where the gain of peak amplifier stage 108 is ideally zero.”] in which a second supply voltage lower than the first supply voltage is provided to the first amplifier and the second amplifier.
Regarding claim 16,
The power amplification circuit (Fig. 3, 300) according to Claim 15, wherein the splitter (Fig. 3, 320, 314, and 316) is configured to control the at least one value of inductance and the at least one value of capacitance to cause the second power level to be higher than the first power level in the second amplification mode [See paragraph [0042], “The input power splitter provides a power level to the peak amplifier stage 108 that is greater than the power level provided to the main amplifier stage 104 in order to compensate for the gain difference and improve gain linearity of the Doherty amplifier device 300. The power level provided to the peak amplifier stage 108 is proportional to the gain difference. Stated another way, as the gain difference between the main and peak amplifier stages 104 and 108 increases, the power level provided to the peak amplifier stage 108 increases.”].
Regarding claim 17,
The power amplification circuit (Fig. 3, 300) according to Claim 2, wherein the splitter (Fig. 3, 320, 314, and 316) is configured to control the at least one value of inductance and the at least one value of capacitance based on a frequency of the first signal, and the combiner (Fig. 3, 236) includes a variable impedance element [See paragraph [0022], “Capacitance 220, inductance 226, and capacitance 228 also implement a low-pass C-L-C network, which is used as an output combiner (e.g., of a symmetrical Doherty amplifier). If properly built (i.e., the proper capacitance and inductance values are selected), this C-L-C network is equivalent to an impedance inverter and provides a 90-degree phase shift of the signal and implements the optimal characteristic impedance Z0 (e.g., providing the functionality of a quarter-wavelength transmission line).”] that is disposed between the first amplifier and the second amplifier and that is configured to control a value of impedance based on the frequency.
Regarding claim 18,
The power amplification circuit (Fig. 3, 300) according to Claim 3, wherein the splitter (Fig. 3, 320, 314, and 316) is configured to control the at least one value of inductance and the at least one value of capacitance based on a frequency of the first signal, and the combiner (Fig. 3, 236) includes a variable impedance element [See paragraph [0022], “Capacitance 220, inductance 226, and capacitance 228 also implement a low-pass C-L-C network, which is used as an output combiner (e.g., of a symmetrical Doherty amplifier). If properly built (i.e., the proper capacitance and inductance values are selected), this C-L-C network is equivalent to an impedance inverter and provides a 90-degree phase shift of the signal and implements the optimal characteristic impedance Z0 (e.g., providing the functionality of a quarter-wavelength transmission line).”] that is disposed between the first amplifier and the second amplifier and that is configured to control a value of impedance based on the frequency.
Regarding claim 19,
The power amplification circuit (Fig. 3, 300) according to Claim 4, wherein the splitter (Fig. 3, 320, 314, and 316) is configured to control the at least one value of inductance and the at least one value of capacitance based on a frequency of the first signal, and the combiner (Fig. 3, 236) includes a variable impedance element [See paragraph [0022], “Capacitance 220, inductance 226, and capacitance 228 also implement a low-pass C-L-C network, which is used as an output combiner (e.g., of a symmetrical Doherty amplifier). If properly built (i.e., the proper capacitance and inductance values are selected), this C-L-C network is equivalent to an impedance inverter and provides a 90-degree phase shift of the signal and implements the optimal characteristic impedance Z0 (e.g., providing the functionality of a quarter-wavelength transmission line).”]that is disposed between the first amplifier and the second amplifier and that is configured to control a value of impedance based on the frequency.
Regarding claim 20,
The power amplification circuit (Fig. 3, 300) according to Claim 1, wherein the first amplifier is a carrier amplifier and the second amplifier is a peaking amplifier [See paragraph [0013], “One amplifying device, or main amplifier stage 104, is biased to operate in a class AB amplifier mode (e.g., has gate bias conditions that implement a power dependent conduction angle between 180 to 360 degrees), and the other amplifying device, or peak amplifier stage 108, is biased to operate in a class C amplifier mode (e.g., has gate bias conditions that implement a power dependent conduction angle between 90 to 180 degrees).”].
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6 and 9 – 11 are rejected under 35 U.S.C. 103 as being unpatentable over Blednov in view of Schenk et al. (US 20160254792 A1), hereinafter Schenk.
Regarding claim 6, Blednov is silent regarding:
The power amplification circuit according to Claim 1,
wherein the at least one variable inductance element each includes a switch including a plurality of input terminals and a plurality of output terminals,
the plurality of input terminals include a first input terminal to which a first input signal is input and a second input terminal to which a second input signal is input,
the plurality of output terminals include a first output terminal from which a first output signal is output and a second output terminal from which a second output signal is output,
the switch is configured to form one or more internal connection paths each electrically connecting one of the plurality of input terminals and one of the plurality of output terminals, and
the at least one variable inductance element each further includes an external circuit that is disposed outside the switch and that is configured to electrically connect the second output terminal and the second input terminal to cause the second output signal, which is output from the second output terminal, to be input to the second input terminal as the second input signal.
Schenk discloses:
wherein the at least one variable inductance element (Fig. 2, 15) each includes a switch [See paragraph [0016], “Within the scope of this application, any arbitrary switching element, for example, comprising PIN diodes or transistors or, for example, also as a relay, can be understood as the switch.”] including a plurality of input terminals (Fig. 2, 10 and 11) and a plurality of output terminals (Fig. 2, outputs of 15),
the plurality of input terminals (Fig. 2, 10 and 11) include a first input terminal (Fig. 2, 10) to which a first input signal (Fig. 2, signal at 10) is input and a second input terminal (Fig. 2, 11) to which a second input signal (Fig. 2, signal at 11) is input,
the plurality of output terminals (Fig. 2, outputs of 15) include a first output terminal (Fig. 2, output from 15 to 16) from which a first output signal (Fig. 2, signal from 15 to 16) is output and a second output terminal (Fig. 2, output from 15 to 30) from which a second output signal (Fig. 2, signal from 15 to 30) is output,
the switch (Fig. 2, 15) is configured to form one or more internal connection paths each electrically connecting one of the plurality of input terminals (Fig. 2, 10 and 11) and one of the plurality of output terminals (Fig. 2, one of the outputs of 15), and
the at least one variable inductance element (Fig. 2, 15) each further includes an external circuit (Fig. 2, 30) that is disposed outside the switch (Fig. 2, 15) and that is configured to electrically connect the second output terminal (Fig. 2, output of 15 to 30) and the second input terminal (Fig. 2, 11) to cause the second output signal (Fig. 2, signal from 15 to 30), which is output from the second output terminal (Fig. 2, output of 15 to 30), to be input to the second input terminal (Fig. 2, 11) as the second input signal (Fig. 2, signal at 11).
Blednov and Schenk are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a switch in the splitter in Blednov‘s design in order to control the terminal connections in the splitter in accordance with Schenk‘s design.
Regarding claim 9, Blednov teaches,
The power amplification circuit (Fig. 3, 300) according to Claim 6, wherein the external circuit is mounted on a board made of liquid crystal polymer or low temperature co-fire ceramic (LTTCC) [See paragraph [0013], “Semiconductor die 318 is attached to an underlying carrier substrate, such as a printed circuit board (PCB) that includes electrically conductive features on a non-conductive substrate, and may be formed using polyimide or FR4 or BT resin”].
Regarding claim 10, Blednov is silent regarding:
The power amplification circuit according to Claim 6, wherein the switch includes a field effect transistor (FET).
Schenk discloses:
The power amplification circuit according to Claim 6, wherein the switch includes a field effect transistor (FET) [See paragraph [0016], “Within the scope of this application, any arbitrary switching element, for example, comprising PIN diodes or transistors or, for example, also as a relay, can be understood as the switch.”].
Blednov and Schenk are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a switch in the splitter in Blednov‘s design in order to control the terminal connections in the splitter in accordance with Schenk‘s design.
Regarding claim 11, Blednov is silent regarding:
The power amplification circuit according to Claim 6, wherein the switch includes a relay.
Schenk discloses:
The power amplification circuit according to Claim 6, wherein the switch includes a relay [See paragraph [0016], “Within the scope of this application, any arbitrary switching element, for example, comprising PIN diodes or transistors or, for example, also as a relay, can be understood as the switch.”].
Blednov and Schenk are both considered to be analogous to the claimed invention because they are in the same field of power amplifiers. It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a switch in the splitter in Blednov‘s design in order to control the terminal connections in the splitter in accordance with Schenk‘s design.
Conclusion
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/JOSE E PINERO/Examiner, Art Unit 2843
/ANDREA LINDGREN BALTZELL/Supervisory Patent Examiner, Art Unit 2843