DETAILED ACTION
The instant application having Application No. 18/446570 filed on 08/09/2003 is presented for examination by the examiner.
Claim 1-23 is/are pending in the application.
Claims 1 and 23 is/are independent claims.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Examiner Notes
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Drawings
The applicant’s drawings submitted are acceptable for examination purposes.
Information Disclosure Statement
As required by M.P.E.P. 609, the applicant’s submissions of the Information Disclosure Statement dated 01/13/2025 and 08/09/2023 are acknowledged by the examiner and the cited references have been considered in the examination of the claims now pending.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-23, the claims are within at least one of the four categories of patent eligible subject matter as it is directing to a system/method claims under Step 1. However, claim 1-23 are/is rejected under 35 USC 101 because the claims are/is directed to an abstract idea without being integrated into a practical application nor being significantly more.
Per claims 1 and 23, the limitations “a system privileged agent arranged to define a configuration of the data processing system”, and “the system privileged agent is configured to define a message channel for communication between the producer element and a consumer element”, as drafted, recite functions that, under its broadest reasonable interpretation, covers functions that could reasonably be performed in the mind, including with the aid of pen and paper, but for the recitation of generic computer components. That is, the limitation “a system privileged agent arranged to define a configuration of the data processing system”, and “the system privileged agent is configured to define a message channel for communication between the producer element and a consumer element as drafted, are functions that, under its broadest reasonable interpretation, recite the abstract idea of a mental process. The limitations encompass a human mind carrying out the functions through observation, evaluation, judgment and /or opinion, or even with the aid of pen and paper. Thus, these limitations recite and fall within the “Mental Processes” grouping of abstract ideas under Prong 1 Step 2A.
Under Prong 2 Step 2A, this judicial exception is not integrated into a practical application. The claim recites the following additional elements “interconnect circuitry”, “the producer element is configured to perform an atomic message store operation with respect to a block of message data targeting the consumer element” and “the interconnect circuitry is configured to convey the block of message data atomically to the non-cacheable target location associated with the consumer element” The “interconnect circuitry” are recited at a high-level of generality such that it amounts no more than mere instructions to apply the exception using a generic computer component, or merely a generic computer or generic computer components to perform the judicial exception. The addition element “the producer element is configured to perform an atomic message store operation with respect to a block of message data targeting the consumer element” amounts to data gathering which is considered to be insignificant extra solution activity (MPEP 2106.05(g); The addition element “the interconnect circuitry is configured to convey the block of message data atomically to the non-cacheable target location associated with the consumer element” is a mere generic transmission and presentation of collected and analyzed data which is considered to be insignificant extra solution activity (MPEP 2106.05(g). Accordingly, the additional elements do not integrate the recited judicial exception into a practical application, and the claim is therefore directed to the judicial exception. See MPEP 2106.05(f).
Under Step 2B, The claims do not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional elements are “interconnect circuitry”, “the producer element is configured to perform an atomic message store operation with respect to a block of message data targeting the consumer element” and “the interconnect circuitry is configured to convey the block of message data atomically to the non-cacheable target location associated with the consumer element” the mere use of generic computer to implement the abstract idea, as discussed above, which does not amount to significantly more, thus, not an inventive concept, and the courts have identified gathering data, storing data, and outputting the result is well-understood, routine and conventional activity (Berkheimer v. HP, Inc., 881 F.3d 1360, 1368, 125 USPQ2d 1649, 1654 (Fed. Cir. 2018)), thus, cannot amount to an inventive concept.. Accordingly, the claim does not appear to be patent eligible under 35 USC 101. See MPEP 2106.05(d).
Regarding claim 2, under prong 2, the “a router device coupled to the interconnect circuitry and comprising an input port and an output port”, “providing the producer element with a message channel router pointer indicative of the input port of the router device”, “storing message channel configuration data in the router, the message channel configuration data comprising the message channel identifier and the message channel target pointer”, “wherein the producer element is arranged to perform the atomic message store operation specifying the message channel router pointer”, and “wherein the router device is responsive to reception of the block of message data at the input port to forward the block of message data from the output port to the non-cacheable target location indicated by the message channel target pointer” limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
Regarding claim 3, under prong 2, the “wherein the multiple processing elements comprise multiple consumer elements, and wherein more than one consumer elements subscribe to the message channel, wherein the message channel is associated with multiple message channel target pointers, wherein each of the message channel target pointers indicates a non-cacheable target location associated with a respective consumer element of the multiple consumer elements, and wherein the message channel configuration data stored in the router device comprises the message channel identifier and the multiple message channel target pointers” limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
Regarding claim 4, under prong 2, the “wherein the router device is responsive to reception of the block of message data at the input port to select a recipient consumer element from the more than one consumer elements which subscribe to the message channel and to forward the block of message data from the output port to the non-cacheable target location indicated by the message channel target pointer associated with the recipient consumer element” limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
Regarding claim 5, under prong 2, the “wherein the router device is further responsive to the reception of the block of message data at the input port to re-forward the block of message data from the output port to each of the more than one consumer elements which subscribe to the message channel” limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
Regarding claim 6, under prong 2, the “wherein the consumer element is responsive to reception of the block of message data at the non-cacheable target location indicated by the message channel target pointer to return a success indicator to the router device, wherein the success indicator indicates whether or not the block of message data has been successfully received by the consumer element, and the router device is responsive to reception of the success indicator to forward the success indicator to the producer element” limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
Regarding claim 7, under prong 2, the “wherein the router device is responsive to the reception of the block of message data at the input port, when no consumer element is available for the message channel, to return a message failure indication to the producer element.” limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
Regarding claim 9, under prong 2, the “wherein the system privileged agent is configured to define a router-less message channel for communication between the producer element and a consumer element by providing the producer element with the message channel target pointer indicating the non-cacheable target location associated with the consumer element, wherein the producer element is arranged to perform the atomic message store operation specifying the message channel target pointer.” limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
Regarding claim 10, under prong 2, the “wherein the consumer element comprises a holding buffer accessible to user software executing on the consumer element, wherein the non-cacheable target location associated with the consumer element is configured as a data reception port of the consumer element, and wherein the data reception port is configured to forward the block of message data received atomically to the holding buffer.” limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
Regarding claim 11, under prong 2, the “wherein the holding buffer comprises at least one of: a set of system registers; vector registers; user software addressable memory buffer; and a plurality of sub-buffers, wherein each sub-buffer of the plurality of sub-buffers is allocated to a corresponding message channel to which the consumer element is subscribed.” limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
Regarding claim 12, under prong 2, the “wherein the consumer element is configured to reserve at least a portion of the holding buffer for at least one prioritised message channel to which the consumer element is subscribed.” limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
Regarding claim 13, under prong 2, the “wherein the user software executing on the consumer element is configured to test whether the holding buffer currently holds a user software targeted block of message data on a message channel to which the user software is subscribed.” limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
Regarding claim 14, under prong 2, the “wherein the consumer element is configured to support execution of multiple tasks on the consumer element, wherein each task has an individual set of consumer element state and the consumer element is configured to switch to a corresponding individual set of consumer element state when switching to a current task of the multiple tasks.” limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
Regarding claim 14, under prong 2, the “wherein the consumer element is configured to support execution of multiple tasks on the consumer element, wherein each task has an individual set of consumer element state and the consumer element is configured to switch to a corresponding individual set of consumer element state when switching to a current task of the multiple tasks.” limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
Regarding claim 15, under prong 2, the “wherein the consumer element is responsive to an attempt to deliver the block of message data at the data reception port, to receive or reject the block of message data in dependence on whether current task is subscribed to the message channel for the block of message data.” limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
Regarding claim 16, under prong 2, the “wherein the data reception port is responsive to an attempt to deliver the block of message data at the data reception port, when the current task is not subscribed to the message channel for the block of message data, to generate an interrupt signal for the consumer element.” limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
Regarding claim 17, under prong 2, the “wherein the consumer element comprises message channel handling circuitry comprising the non-cacheable target location, wherein the message channel handling circuitry is configured to reference message channels using message channel identifiers, wherein user software executing on the consumer element is configured to reference the message channel using a virtual message channel identifier, and the consumer element comprises message channel identifier translation circuitry configured to translate virtual message channel identifiers to message channel identifiers in dependence on user software currently executing on the consumer element.” limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
Regarding claim 18, under prong 2, the “wherein the system privileged agent comprises at least one of: an operating system; and a hypervisor.” limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
Regarding claim 19, under prong 2, the “wherein the system privileged agent is responsive to a message channel setup call for the message channel from a processing element of the multiple processing elements to: allocate the message channel identifier for the message channel; specify the message channel target pointer; wherein the processing element uses virtual addresses to reference memory locations, and allocate a virtual address for the processing element to use for the message channel, wherein the virtual address maps to a physical address given by the message channel target pointer.” limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
Regarding claim 20, the limitation “specify the message channel target pointer; specify the message channel router pointer; wherein the processing element uses virtual addresses to reference memory locations” is an additional metal process under prong 1. Under prong 2, the “allocate the message channel identifier for the message channel;” and “allocate a virtual address for the processing element to use for the message channel, wherein the virtual address maps to a physical address given by the message channel router pointer” limitations are additional elements that recite insignificant extra solution activity which do not amount to a practical application, nor amount to significantly more under step 2B as explained above.
Regarding claim 21, the limitation “wherein the system privileged agent is configured to define a virtual-to-physical address mapping scheme between a virtual address space and a physical address space in which a subset of bits of the physical address space are directly indicative of a set of message channel identifiers defined by the system privileged agent.” is an additional metal process under prong 1.
Regarding claim 22, the limitation “wherein at least one processing element of the multiple processing elements is configured to support execution of multiple tasks on the processing element, wherein each task has an individual set of processing element state, wherein the system privileged agent is configured to administer time-sliced use of the processing element by causing an exchange of the individual set of processing element state and by modifying at least one of the message channel identifier and the message channel target pointer.” is an additional metal process under prong 1.
Allowable Subject Matter
Claims 2-8, 14-17 and 19-22 would be allowable if rewritten to overcome the rejection(s) under 101, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims.
The prior art of record does not disclose and/or fairly suggest at least claimed limitations recited in such manners in dependent claims 2-8, 14-17, and 19-22.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1, 9 and 23 are rejected under 35 U.S.C. 103 as being unpatentable over US 2018/023169 to Beard et al. (hereafter “Beard” in further view of US 2003/0051100 to Patel and US 2006/0174040 to Check et al. (hereafter “Check”)
As per claim 1, Beard discloses a data processing system comprising:
a system privileged agent arranged to define a configuration of the data processing system (FIGs. 1-2; paragraphs 0032-0036 and 0030-0040: “a virtual link buffer between execution threads is implemented using one or more cache lines in caches 208 and 212. Control of the cache lines, used to implement a virtual link buffer, is provided by link controller 222. Link controller 222 may be implemented in interconnect structure 206. Link controller 222 is implemented in hardware and provides hardware acceleration for direct communication between producer and consumer device.” [Wingdings font/0xE0] link controller (privilege agent as claimed));
multiple processing elements arranged to perform data processing (FIGs. 1-2: “system 200 comprises first processing device 202 and second processing device 204 that are coupled by an interconnect structure 206. Devices 202 and 204 and interconnect structure 206 may be implemented on the same chip (as shown) or on separate chips. In general, system 200 may have any number of devices. First processing device 202 includes at least one cache 208 together with a cache controller 210. Similarly, second processing device 204 includes at least one cache 212 together with a cache controller 214. The at least one cache may be a hierarchy of caches, such as level one (L1) cache and a level two (L2) cache. Interconnect structure 206 includes a coherence controller 216 that controls data flow between the caches 208 and 212 and a main memory 218.”), wherein the multiple processing elements comprise a producer element and a consumer element (FIGs. 1-2 and 17; paragraphs 0032-0036 and 0030-0040: “a virtual link buffer between execution threads is implemented using one or more cache lines in caches 208 and 212. Control of the cache lines, used to implement a virtual link buffer, is provided by link controller 222. Link controller 222 may be implemented in interconnect structure 206. Link controller 222 is implemented in hardware and provides hardware acceleration for direct communication between producer and consumer device.”); and
interconnect circuitry arranged to couple the multiple processing elements with one another (FIGs. 1-2; paragraph 0034: “system 200 comprises first processing device 202 and second processing device 204 that are coupled by an interconnect structure 206. Devices 202 and 204 and interconnect structure 206 may be implemented on the same chip (as shown) or on separate chips. In general, system 200 may have any number of devices. First processing device 202 includes at least one cache 208 together with a cache controller 210. Similarly, second processing device 204 includes at least one cache 212 together with a cache controller 214. The at least one cache may be a hierarchy of caches, such as level one (L1) cache and a level two (L2) cache. Interconnect structure 206 includes a coherence controller 216 that controls data flow between the caches 208 and 212 and a main memory 218.” [Wingdings font/0xE0] on-chip interconnection), wherein the data processing system supports a message channel functionality (FIGs. 1-2 and 17) according to which:
the system privileged agent is configured to define a message channel for communication (FIGs. 1-2 and 17; paragraphs 0032-0036 and 0030-0040: “directed communication channel, implemented using caches and a link controller, for providing a data link between execution threads in a data processing system. The communication channel provides a virtual link buffer. For example, the caches may be used to implement ordered communication of data (such a first-in, first-out (FIFO) pattern, or a last-in, last-out (LIFO) pattern), or unordered communication.” [Wingdings font/0xE0] i.e. FIFO/queue implementing virtual link buffer [Wingdings font/0xE0] data/communication channel) between the producer element and a consumer element (FIGs. 1-2 and 17; paragraphs 0032-0036 and 0030-0040: “a virtual link buffer between execution threads is implemented using one or more cache lines in caches 208 and 212. Control of the cache lines, used to implement a virtual link buffer, is provided by link controller 222. Link controller 222 may be implemented in interconnect structure 206. Link controller 222 is implemented in hardware and provides hardware acceleration for direct communication between producer and consumer device.”), the message channel being defined by a message channel identifier (FIG. 9; paragraphs 0032, 0069, 0096 and 0101: “A shared identifier of the virtual link buffer is stored in column 1202. The identifier may be virtual memory address of the FIFO, for example. “ and “At block 912, a virtual address is issued for the virtual link buffer in the reserved address range, the FIFO is registered with that address in the link controller.” [Wingdings font/0xE0] shared identifier or the virtual link/FIFO address) and a message channel target pointer (paragraphs 0051 and 0105: “For each of the virtual link buffers listed in column 1302, buffer table 1300 stores a pointer to a corresponding buffer in memory in column 1304 and a tail offset in column 1306. These indicators identify the buffered lines that have been received from a producer device but not yet transferred to a consumer device.”), wherein the message channel target pointer indicates a target location associated with the consumer element (paragraphs 0051 and 0105: “For each of the virtual link buffers listed in column 1302, buffer table 1300 stores a pointer to a corresponding buffer in memory in column 1304 and a tail offset in column 1306. These indicators identify the buffered lines that have been received from a producer device but not yet transferred to a consumer device.”);
the producer element is configured to perform an atomic message store operation (paragraphs 0040-0045 and 0049: “The data elements may be produced in sequence, where each data element is stored at a location in the producer cache line indicated by a store position indicator, where the store position indicator is stored at a predetermined location in the producer cache line and where the first cache controller is configured to access the tail indicator. The store position indicator may be referred to herein as a tail indicator for a queue-like data buffer or as a top indicator for a stack-like data buffer.”) with respect to a block of message data targeting the consumer element (paragraphs 0040-0045, 0049 and 0091: “The link controller may be configured to buffer data elements transferred from the producer cache line to the consumer cache line in the memory and to maintain an order of buffered data elements”), wherein the producer element specifies the block of message data (paragraphs 0040-0045, 0049 and 0091); and
the interconnect circuitry is configured to convey the block of message data atomically to the target location associated with the consumer element (paragraphs 0040-0045, 0049 and 0091: data elements are transferred to consumer buffer).
Beard discloses wherein the message channel target pointer indicates a target location associated with the consumer element (paragraphs 0051 and 0105: “For each of the virtual link buffers listed in column 1302, buffer table 1300 stores a pointer to a corresponding buffer in memory in column 1304 and a tail offset in column 1306. These indicators identify the buffered lines that have been received from a producer device but not yet transferred to a consumer device.”), however the Beard does not explicitly disclose a non-cacheable target location associated with the consumer element; wherein the producer element specifies the message channel identifier.
Patel further discloses a non-cacheable target location associated with the consumer element (paragraphs 0032, 0034 and 0038: “The non-cacheable identifier buffer 308 tracks content that is non-cacheable. The buffer 308 may also be a bit-wise buffer implemented in hardware, a software-implemented buffer, or another type of buffer. The buffer 308 preferably tracks such content by identifiers, such as URL addresses at which the content is located.”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Patel into Beard’s teaching because it would provide for the purpose of by checking the buffer 308, the caching server 206 is able to determine whether the content requested by a client is non-cacheable (Patel, paragraph 0032).
Check further discloses wherein the producer element specifies the message channel identifier (paragraphs 0088-0089: “In a first form of routing determination, the sender (in this case, inbound I/O bus interface component 403) transmits the port ID and channel ID in the applicable fields of the command, and the router simply routes the packet to the specified port and channel.”)
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Check into Beard’s teaching and Patel’s teaching because it would provide for the purpose of determining a destination port (from among ports 501) and channel for packets received on port 0 and routes the packets accordingly (Check, paragraph 0088).
As per claim 9, Beard discloses wherein the system privileged agent is configured to define a router-less message channel for communication between the producer element and a consumer element (paragraphs 0051 and 0105: “For each of the virtual link buffers listed in column 1302, buffer table 1300 stores a pointer to a corresponding buffer in memory in column 1304 and a tail offset in column 1306. These indicators identify the buffered lines that have been received from a producer device but not yet transferred to a consumer device.” [Wingdings font/0xE0] using pointer for transferring data [Wingdings font/0xE0] router-less message channel) by providing the producer element with the message channel target pointer indicating the target location associated with the consumer element (paragraphs 0051 and 0105: “For each of the virtual link buffers listed in column 1302, buffer table 1300 stores a pointer to a corresponding buffer in memory in column 1304 and a tail offset in column 1306. These indicators identify the buffered lines that have been received from a producer device but not yet transferred to a consumer device.”),
wherein the producer element is arranged to perform the atomic message store operation specifying the message channel target pointer (paragraphs 0051 and 0105: “For each of the virtual link buffers listed in column 1302, buffer table 1300 stores a pointer to a corresponding buffer in memory in column 1304 and a tail offset in column 1306. These indicators identify the buffered lines that have been received from a producer device but not yet transferred to a consumer device.”).
Beard discloses wherein the message channel target pointer indicates a target location associated with the consumer element (paragraphs 0051 and 0105: “For each of the virtual link buffers listed in column 1302, buffer table 1300 stores a pointer to a corresponding buffer in memory in column 1304 and a tail offset in column 1306. These indicators identify the buffered lines that have been received from a producer device but not yet transferred to a consumer device.”), however the Beard does not explicitly disclose a non-cacheable target location associated with the consumer element.
Patel further discloses a non-cacheable target location associated with the consumer element (paragraphs 0032, 0034 and 0038: “The non-cacheable identifier buffer 308 tracks content that is non-cacheable. The buffer 308 may also be a bit-wise buffer implemented in hardware, a software-implemented buffer, or another type of buffer. The buffer 308 preferably tracks such content by identifiers, such as URL addresses at which the content is located.”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Patel into Beard’s teaching because it would provide for the purpose of by checking the buffer 308, the caching server 206 is able to determine whether the content requested by a client is non-cacheable (Patel, paragraph 0032).
As per claim 23, it is a method claim, which recite(s) the same limitations as those of claim 1. Accordingly, claim 23 is rejected for the same reasons as set forth in the rejection of claim 1.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Beard in view of Patel and Check, as applied to claim 1, and further in view of US 2003/0016686 to Wynne et al. (hereafter “Wynne”)
As per claim 10, Beard discloses wherein the consumer element comprises a holding buffer accessible to user software executing on the consumer element (FIGs. 1-2 and 17; paragraphs 0032-0036 and 0030-0040: “a virtual link buffer between execution threads is implemented using one or more cache lines in caches 208 and 212. Control of the cache lines, used to implement a virtual link buffer, is provided by link controller 222. Link controller 222 may be implemented in interconnect structure 206. Link controller 222 is implemented in hardware and provides hardware acceleration for direct communication between producer and consumer device.”).
Beard does not explicitly disclose wherein the non-cacheable target location associated with the consumer element is configured as a data reception port of the consumer element, and wherein the data reception port is configured to forward the block of message data received atomically to the holding buffer.
Patel further discloses wherein the non-cacheable target location associated with the consumer element is configured as a data reception port of the consumer element (paragraphs 0032, 0034 and 0038: “The non-cacheable identifier buffer 308 tracks content that is non-cacheable. The buffer 308 may also be a bit-wise buffer implemented in hardware, a software-implemented buffer, or another type of buffer. The buffer 308 preferably tracks such content by identifiers, such as URL addresses at which the content is located.”).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Patel into Beard’s teaching because it would provide for the purpose of by checking the buffer 308, the caching server 206 is able to determine whether the content requested by a client is non-cacheable (Patel, paragraph 0032).
Wynne further discloses wherein the data reception port is configured to forward the block of message data received atomically to the holding buffer (paragraph 0086).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Wynne into Beard’s teaching, Patel’s teaching and Check’s teaching because it would provide for the purpose of the traffic manager is able to separately control the rate at which the input or output port forwards cells of each flow queue and the rate at which each forwarding resource receives and forwards cells (Wynne, paragraph 0018).
As per claim 11, Beard discloses wherein the holding buffer comprises at least one of:
a set of system registers;
vector registers;
user software addressable memory buffer (paragraphs 0033 and 0036); and
a plurality of sub-buffers, wherein each sub-buffer of the plurality of sub-buffers is allocated to a corresponding message channel to which the consumer element is subscribed (paragraphs 0049, 0051-0052, 0069 and 0105).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Beard in view of Patel, Check and Wynne, as applied to claim 10, and further in view of US 2004/0109434 to Hwang.
As per claim 12, Beard does not explicitly disclose wherein the consumer element is configured to reserve at least a portion of the holding buffer for at least one prioritised message channel to which the consumer element is subscribed.
Hwang further discloses wherein the consumer element is configured to reserve at least a portion of the holding buffer for at least one prioritised message channel to which the consumer element is subscribed (paragraph 0013).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Hwang into Beard’s teaching, Patel’s teaching, Check’s teaching, and Wynne’s teaching because it would provide for the purpose of provide a data frame structure that allows easy determination of transmission system depending on characteristic and amount of data to be transmitted when numerous mobile stations require communication services almost at a time (Hwang, paragraph 0011).
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Beard in view of Patel, Check and Wynne, as applied to claim 10, and further in view of US 2003/0069973 to Ganesan et al. (hereafter “Ganesan”)
As per claim 13, Beard does not explicitly disclose wherein the user software executing on the consumer element is configured to test whether the holding buffer currently holds a user software targeted block of message data on a message channel to which the user software is subscribed.
Ganesan further discloses wherein the user software executing on the consumer element is configured to test whether the holding buffer currently holds a user software targeted block of message data on a message channel to which the user software is subscribed (paragraph 0111).
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Ganesan into Beard’s teaching, Patel’s teaching, Check’s teaching, and Wynne’s teaching because it would provide for the purpose of processing compute element communicating service set-up information with the management compute element in order to perform service specific operations on data packets (Ganesan, paragraph 0017).
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Beard in view of Patel and Check, as applied to claim 1, and further in view of US 2002/0071386 to Gronke.
As per claim 18, Beard does not explicitly disclose wherein the system privileged agent comprises at least one of:
an operating system; and
a hypervisor.
Gronke further discloses wherein the system privileged agent comprises at least one of:
an operating system (paragraph 0023); and
a hypervisor.
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to combine a teaching of Ganesan into Beard’s teaching, Patel’s teaching, and Check’s teaching, because it would provide for the purpose of performing the setup and resource management functions needed to maintain a virtual interface between VI consumers and VI NICs (Gronke, paragraph 0023).
Conclusion
The following prior art made of record and not relied upon is cited to establish the level of skill in the applicant’s art and those arts considered reasonably pertinent to applicant’s disclosure. See MPEP 707.05(c).
Prior arts:
US 2006/0098022 to Andrews
For such embodiments, at step 1510, the CPU module may update a head pointer on the GPU module. The CPU module may send update the head pointer via a non-cacheable memory unit down to the GPU module. In response, the GPU module may begin reading data from the L2 cache of the CPU module up to the address indicated by the head pointer.
US 2003/0187741 to Brown
The on-line queue manager 20 issues a query to the relational data base engine to retrieve all records from the subscriber queue table 254 and the temporary queue table 252 where the target id matches the forSubscriberID, and where the segment id identifies a segment of the correct ofMediaType and the correct forUseType.
US 2003/0121051 to Howe
The video service provider transmits to the set top box the identity of a network service (i.e., a network address) or a channel on which the requested program will be provided, and the set top box processor initiates a session with the indicated network service and/or causes the receiving set to tune to the channel.
US 2003/0086140 to Thomas
Premium subscribers can have their traffic assigned to the third highest priority queue or third party output buffer 570, while standard and value subscribers can be assigned to the lowest priority or fourth priority output buffer 572.
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/TUAN C DAO/ Primary Examiner, Art Unit 2198