DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendments filed on 3/23/2026 have been entered.
Response to Arguments
Applicant’s arguments regarding Claims 1-20 have been fully considered and are persuasive. Therefore, the prior art rejections of Claims 1-20 are withdrawn. However, a new ground of rejection, which was necessitated by Applicant’s amendments, has been found and now follows.
In the interest of compact prosecution, the examiner notes that further description of how the first circuit patterns within the active layer are connected and function, such as 120a/b (semi-circle shape) and 140 (cross-shape) as shown in Fig 2 of the instant application, and how they are related to the inventive concept would be helpful in overcoming the prior art of record. The examiner is available for an interview at Applicant’s convenience.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-3, 11-13, and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al (US 2021/0111140) in view of Hwang et al (US 2013/0037942), and in further view of Yang (KR 101088825).
Regarding Claim 1, Jang et al discloses a semiconductor package (semiconductor package [0006] Fig 1 as viewed from 180 degrees), comprising:
a substrate (first substrate 210 [0042] and second substrate 310 [0044]) comprising a first surface (shown in annotated Fig 1 viewed from 180 degrees) and a second surface (shown in annotated Fig 1 viewed from 180 degrees) opposite to the first surface (shown in annotated Fig 1 viewed from 180 degrees);
first circuit patterns (circuit patterns (not illustrated) may be provided in the first surface of the first substrate 210 [0037]);
a through electrode (through electrode 240 [0036]) penetrating the substrate (210 and 310), the through electrode (240) comprising a first end portion (shown in annotated Fig 1 viewed from 180 degrees) that is exposed at the first surface (shown in annotated Fig 1 viewed from 180 degrees) of the substrate (210 and 310); and
a redistribution wiring layer (redistribution wiring layer 100 [0034]) on the first surface (shown in annotated Fig 1 viewed from 180 degrees) of the substrate (210 and 310), the redistribution wiring layer (100) comprising a landing pad (shown in annotated Fig 1 viewed from 180 degrees) and redistribution wires (redistribution wiring line 150a, 150b [0050]);
wherein the landing pad (shown in annotated Fig 1 viewed from 180 degrees) is electrically connected to the first end portion (shown in annotated Fig 1 viewed from 180 degrees) of the through electrode (240), and wherein the redistribution wires (150a, 150b) are electrically connected to the landing pad (shown in annotated Fig 1 viewed from 180 degrees) and the first circuit patterns (circuit patterns (not illustrated) may be provided in the first surface of the first substrate 210).
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Jang et al does not directly disclose
a silicon substrate;
wherein an active layer is on the first surface; and
wherein the active layer comprises a through opening area and a first circuit pattern area surrounding the through opening area and in which first circuit patterns are located; and
a through electrode extending into the active layer; and
wherein the redistribution wires are electrically connected to the landing pad and the first circuit patterns, such that the through electrode is electrically connected to at least one of the first circuit patterns of the active layer through the redistribution wires.
Hwang et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
a silicon substrate (first substrate 211 and second substrate 221 may be a silicon substrate [0066]-[0067] Fig 15 as viewed from 180 degrees);
an active layer (active layer 112 [0048] Fig 15 as viewed from 180 degrees); and
wherein the active layer (112 Fig 15 as viewed from 180 degrees) comprises a through opening area (area where through electrodes 141 and 142 [0056] Fig 15).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jang et al to include a silicon substrate and an active layer as taught by Hwang et al in order to help incorporate active elements [0049] which would improve the electrical functioning of the device. Further, a person of ordinary skill in the art would have recognized that having a substrate that is a silicon substrate would also help improve the electrical functioning of the device (see MPEP 2143.I(D)) and would be a simple substitution of one element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
The combination of Jang et al and Hwang et al now discloses
wherein an active layer (active layer 112 [0048] Fig 15 as viewed from 180 degrees, Hwang et al) is on the first surface (shown in annotated Fig 1 viewed from 180 degrees, Jang et al); and
wherein the active layer (active layer 112 [0048] Fig 15 as viewed from 180 degrees, Hwang et al) comprises a first circuit pattern area (area where circuit patterns (not illustrated) may be provided in the first surface of the first substrate 21 [0037] Jang et al are located) surrounding the through opening area (area where through electrodes 240 are located, Jang et al) and in which first circuit patterns (circuit patterns (not illustrated) may be provided in the first surface of the first substrate 210 [0037] Jang et al) are located, and
a through electrode (240 Jang et al) extending into the active layer (112 Hwang et al).
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wherein the redistribution wires are electrically connected to the landing pad and the first circuit patterns, such that the through electrode is electrically connected to at least one of the first circuit patterns of the active layer through the redistribution wires.
Yang, in the related art of semiconductor devices that include semiconductor packaging, discloses
the through electrode (through electrodes 332 and 334 [page 3, lines 16-40] Fig 3) is electrically connected to at least one of the first circuit patterns (side electrodes 340 [page 3, lines 16-40] Fig 3) of the active layer (active layer 320 [page 3, lines 16-40] Fig 3).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jang et al and Hwang et al to include wherein the through electrode is electrically connected to at least one of the first circuit patterns of the active layer as taught by Yang in order to have an active layer formed of various elements including multilayered metal wires therein [page 3, lines 16-40] which would improve the electrical functioning capability of the device. Further, a person of ordinary skill in the art would have recognized that having improved electrical connections would optimize the electrical function while minimizing unwanted damage from undesirable electrical effects (see MPEP 2143.I(D)).
The combination of Jang et al, Hwang et al, and Yang now discloses
wherein the redistribution wires (150a, 150b Jang et al) are electrically connected to the landing pad (shown above in annotated Fig 1 viewed from 180 degrees Jang et al) and the first circuit patterns (circuit patterns (not illustrated) may be provided in the first surface of the first substrate 210 [0037] Jang et al/side electrodes 340 [page 3, lines 16-40] Fig 3 Yang), such that the through electrode (through electrodes 332 and 334 [page 3, lines 16-40] Fig 3 Yang) is electrically connected to at least one of the first circuit patterns (side electrodes 340 [page 3, lines 16-40] Fig 3 Yang) of the active layer (active layer 320 [page 3, lines 16-40] Fig 3 Yang) through the redistribution wires (150a, 150b Jang et al).
Regarding Claim 2, the combination of Jang et al, Hwang et al, and Yang discloses the limitations of claim 1 as explained above. The combination of Jang et al, Hwang et al, and Yang further discloses
wherein the through electrode (240 Jang et al) further comprises a second end portion (shown in annotated Fig 1 viewed from 180 degrees, Jang et al) that is opposite to the first end portion (shown in annotated Fig 1 viewed from 180 degrees, Jang et al), and
wherein the semiconductor package (semiconductor package [0006] Fig 1 as viewed from 180 degrees) further comprises a bonding pad (second chip pad 231[0038]) on the second end portion (shown in annotated Fig 1 viewed from 180 degrees, Jang et al) that is electrically connected to the redistribution wiring layer (100 Jang et al) through the through electrode (240 Jang et al).
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Regarding Claim 3, the combination of Jang et al, Hwang et al, and Yang discloses the limitations of claim 2 as explained above. The combination of Jang et al, Hwang et al, and Yang further discloses
wherein the redistribution wiring layer (100 Jang et al) further comprises redistribution pads (shown in annotated Fig 1 viewed from 180 degrees, Jang et al) that are electrically connected to the redistribution wires (150a, 150b, Jang et al) and that are exposed at a fourth surface (shown in annotated Fig 1 viewed from 180 degrees, Jang et al) of the redistribution wiring layer (100 Jang et al) that is opposite to a third surface (shown in annotated Fig 1 viewed from 180 degrees, Jang et al) of the redistribution wiring layer (100 Jang et al) that is in contact with the silicon substrate (210 and 310 Jang et al/first substrate 211 and second substrate 221 may be a silicon substrate [0066]-[0067] Fig 15 as viewed from 180 degrees, Hwang et al).
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Regarding Claim 11, Jang et al discloses a semiconductor package (semiconductor package [0006] Fig 1 as viewed from 180 degrees), comprising:
a substrate (first substrate 210 [0042] and second substrate 310 [0044]) comprising a front surface (shown in annotated Fig 1 viewed from 180 degrees) and a back surface (shown in annotated Fig 1 viewed from 180 degrees) opposite to the front surface (shown in annotated Fig 1 viewed from 180 degrees),
circuit patterns (circuit patterns (not illustrated) may be provided in the first surface of the first substrate 210 [0037]);
a circuit pattern area (area where circuit patterns (not illustrated) may be provided in the first surface of the first substrate 210 [0037]) surrounding the through opening area (area where through electrode 240 is located [0036]) and in which circuit patterns (circuit patterns (not illustrated) may be provided in the first surface of the first substrate 210 [0037]) are located;
a through electrode (through electrode 240 [0036]) penetrating at least a portion of the substrate (210 and 310), the through electrode (240) comprising a first end portion (shown in annotated Fig 1 viewed from 180 degrees) that is exposed at the front surface (shown in annotated Fig 1 viewed from 180 degrees) of the substrate (210 and 310); and
a redistribution wiring layer (redistribution wiring layer 100 [0034]) on the front surface of the substrate (210 and 310), the redistribution wiring layer (100) comprising a landing pad (shown in annotated Fig 1 viewed from 180 degrees) and redistribution wires (redistribution wiring line 150a, 150b [0050]), wherein the landing pad (shown in annotated Fig 1 viewed from 180 degrees) is electrically connected to the through electrode (240), and wherein the redistribution wires (redistribution wiring line 150a, 150b [0050]) are electrically connected to the landing pad (shown in annotated Fig 1 viewed from 180 degrees) and the circuit patterns (circuit patterns (not illustrated) may be provided in the first surface of the first substrate 210).
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Jang et al does not directly disclose
a silicon substrate;
wherein an active layer is on the front surface, and
wherein the active layer comprises a through opening area and a circuit pattern area surrounding the through opening area and in which circuit patterns are located;
a through electrode extending into the active layer; and
wherein the redistribution wires are electrically connected to the landing pad and the first circuit patterns, such that the through electrode is electrically connected to at least one of the first circuit patterns of the active layer through the redistribution wires.
Hwang et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
a silicon substrate (first substrate 211 and second substrate 221 may be a silicon substrate [0066]-[0067] Fig 15 as viewed from 180 degrees);
an active layer (active layer 112 [0048] Fig 15 as viewed from 180 degrees); and
wherein the active layer (112 Fig 15 as viewed from 180 degrees) comprises a through opening area (area where through electrodes 141 and 142 [0056] Fig 15).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jang et al to include a silicon substrate and an active layer as taught by Hwang et al in order to help incorporate active elements [0049] which would improve the electrical functioning of the device. Further, a person of ordinary skill in the art would have recognized that having a substrate that is a silicon substrate would also help improve the electrical functioning of the device (see MPEP 2143.I(D)) and would be a simple substitution of one element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
The combination of Jung et al and Hwang et al now further discloses
wherein an active layer (active layer 112 [0048] Fig 15 as viewed from 180 degrees, Hwang et al) is on the front surface (shown in annotated Fig 1 viewed from 180 degrees, Jang et al), and
wherein the active layer (112 Hwang et al) comprises a through opening area (area where through electrode 240 is present, Jang et al) and a circuit pattern area (area where circuit patterns (not illustrated) may be provided in the first surface of the first substrate 210 Jang et al) surrounding the through opening area (area where through electrode 240 is present, Jang et al) and in which circuit patterns (circuit patterns (not illustrated) may be provided in the first surface of the first substrate 210 Jang et al) are located.
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wherein the redistribution wires are electrically connected to the landing pad and the first circuit patterns, such that the through electrode is electrically connected to at least one of the first circuit patterns of the active layer through the redistribution wires.
Yang, in the related art of semiconductor devices that include semiconductor packaging, discloses
the through electrode (through electrodes 332 and 334 [page 3, lines 16-40] Fig 3) is electrically connected to at least one of the first circuit patterns (side electrodes 340 [page 3, lines 16-40] Fig 3) of the active layer (active layer 320 [page 3, lines 16-40] Fig 3).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jang et al and Hwang et al to include wherein the through electrode is electrically connected to at least one of the first circuit patterns of the active layer as taught by Yang in order to have an active layer formed of various elements including multilayered metal wires therein [page 3, lines 16-40] which would improve the electrical functioning capability of the device. Further, a person of ordinary skill in the art would have recognized that having improved electrical connections would optimize the electrical function while minimizing unwanted damage from undesirable electrical effects (see MPEP 2143.I(D)).
The combination of Jang et al, Hwang et al, and Yang now discloses
wherein the redistribution wires (150a, 150b Jang et al) are electrically connected to the landing pad (shown above in annotated Fig 1 viewed from 180 degrees Jang et al) and the first circuit patterns (circuit patterns (not illustrated) may be provided in the first surface of the first substrate 210 [0037] Jang et al/side electrodes 340 [page 3, lines 16-40] Fig 3 Yang), such that the through electrode (through electrodes 332 and 334 [page 3, lines 16-40] Fig 3 Yang) is electrically connected to at least one of the first circuit patterns (side electrodes 340 [page 3, lines 16-40] Fig 3 Yang) of the active layer (active layer 320 [page 3, lines 16-40] Fig 3 Yang) through the redistribution wires (150a, 150b Jang et al).
Regarding Claim 12, the combination of Jang et al, Hwang et al, and Yang discloses the limitations of claim 11 as explained above. The combination of Jang et al, Hwang et al, and Yang further discloses
wherein the through electrode (240 Jang et al) further comprises a second end portion (shown in annotated Fig 1 viewed from 180 degrees, Jang et al) that is opposite to the first end portion (shown in annotated Fig 1 viewed from 180 degrees, Jang et al), and
wherein the semiconductor package (semiconductor package [0006] Fig 1 as viewed from 180 degrees) further comprises a bonding pad (second chip pad 231[0038]) on the second end portion (shown in annotated Fig 1 viewed from 180 degrees, Jang et al) that is electrically connected to the redistribution wiring layer (100 Jang et al) through the through electrode (240 Jang et al).
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Regarding Claim 13, the combination of Jang et al, Hwang et al, and Yang discloses the limitations of claim 12 as explained above. The combination of Jang et al, Hwang et al, and Yang further discloses
wherein the redistribution wiring layer (100 Jang et al) further comprises redistribution pads (shown in annotated Fig 1 viewed from 180 degrees, Jang et al) that are electrically connected to the redistribution wires (150a, 150b, Jang et al) and that are exposed at a fourth surface (shown in annotated Fig 1 viewed from 180 degrees, Jang et al) of the redistribution wiring layer (100 Jang et al) that is opposite to a third surface (shown in annotated Fig 1 viewed from 180 degrees, Jang et al) of the redistribution wiring layer (100 Jang et al) that is in contact with the silicon substrate (210 and 310 Jang et al/first substrate 211 and second substrate 221 may be a silicon substrate [0066]-[0067] Fig 15 as viewed from 180 degrees, Hwang et al).
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Regarding Claim 20, Jang et al discloses a semiconductor package (semiconductor package [0006] Fig 1 as viewed from 180 degrees), comprising:
a substrate (first substrate 210 [0042] and second substrate 310 [0044]) comprising a first surface (shown in annotated Fig 1 viewed from 180 degrees) and a second surface (shown in annotated Fig 1 viewed from 180 degrees) opposite to the first surface (shown in annotated Fig 1 viewed from 180 degrees),
circuit patterns (circuit patterns (not illustrated) may be provided in the first surface of the first substrate 210 [0037]);
a through opening area (area where through electrode 240 is located [0036]), and a circuit pattern area (area where circuit patterns (not illustrated) may be provided in the first surface of the first substrate 210 [0037]) surrounding the through opening area (area where through electrode 240 is located [0036]) and in which the circuit patterns (circuit patterns (not illustrated) may be provided in the first surface of the first substrate 210) are located;
a through electrode (area where through electrode 240 is located [0036]) penetrating at least a portion of the substrate (210 and 310), the through electrode (240) comprising a first end portion (shown in annotated Fig 1 viewed from 180 degrees) that is exposed at the first surface (shown in annotated Fig 1 viewed from 180 degrees) of the substrate (210 and 310) and a second end portion (shown in annotated Fig 1 viewed from 180 degrees) that is opposite to the first end portion (shown in annotated Fig 1 viewed from 180 degrees);
a redistribution wiring layer (redistribution wiring layer 100 [0034]) on the first surface (shown in annotated Fig 1 viewed from 180 degrees) of the substrate (210 and 310), wherein the redistribution wiring layer (100) comprises a landing pad (shown in annotated Fig 1 viewed from 180 degrees) and redistribution wires (redistribution wiring line 150a, 150b [0050]), wherein the landing pad (shown in annotated Fig 1 viewed from 180 degrees) is electrically connected to the first end portion (shown in annotated Fig 1 viewed from 180 degrees) of the through electrode (240), and wherein the redistribution wires (150a, 150b) are electrically connected to the landing pad (shown in annotated Fig 1 viewed from 180 degrees) and the circuit patterns (circuit patterns (not illustrated) may be provided in the first surface (shown in annotated Fig 1 viewed from 180 degrees) of the first substrate 210 [0037]); and
a bonding pad (second chip pad 231[0038]) on a second end portion (shown in annotated Fig 1 viewed from 180 degrees) opposite to the first end portion (shown in annotated Fig 1 viewed from 180 degrees) of the through electrode (240), wherein the bonding pad (231) is electrically connected to the redistribution wiring layer (100) through the through electrode (240).
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a silicon substrate; and
wherein an active layer is on the first surface and comprises circuit patterns;
a through electrode extending into the active layer; and
wherein the redistribution wires are electrically connected to the landing pad and the first circuit patterns, such that the through electrode is electrically connected to at least one of the first circuit patterns of the active layer through the redistribution wires.
Hwang et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
a silicon substrate (first substrate 211 and second substrate 221 may be a silicon substrate [0066]-[0067] Fig 15 as viewed from 180 degrees);
an active layer (active layer 112 [0048] Fig 15 as viewed from 180 degrees); and
wherein the active layer (112 Fig 15 as viewed from 180 degrees) comprises a through opening area (area where through electrodes 141 and 142 [0056] Fig 15).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Jang et al to include a silicon substrate and an active layer as taught by Hwang et al in order to help incorporate active elements [0049] which would improve the electrical functioning of the device. Further, a person of ordinary skill in the art would have recognized that having a substrate that is a silicon substrate would also help improve the electrical functioning of the device (see MPEP 2143.I(D)) and would be a simple substitution of one element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
The combination of Jang et al and Hwang et al now further discloses
wherein an active layer (active layer 112 [0048] Fig 15 as viewed from 180 degrees, Hwang et al) is on the first surface (shown in annotated Fig 1 viewed from 180 degrees, Jang et al), and comprises circuit patterns (circuit patterns (not illustrated) may be provided in the first surface of the first substrate 210 Jang et al).
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wherein the redistribution wires are electrically connected to the landing pad and the first circuit patterns, such that the through electrode is electrically connected to at least one of the first circuit patterns of the active layer through the redistribution wires.
Yang, in the related art of semiconductor devices that include semiconductor packaging, discloses
the through electrode (through electrodes 332 and 334 [page 3, lines 16-40] Fig 3) is electrically connected to at least one of the first circuit patterns (side electrodes 340 [page 3, lines 16-40] Fig 3) of the active layer (active layer 320 [page 3, lines 16-40] Fig 3).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jang et al and Hwang et al to include wherein the through electrode is electrically connected to at least one of the first circuit patterns of the active layer as taught by Yang in order to have an active layer formed of various elements including multilayered metal wires therein [page 3, lines 16-40] which would improve the electrical functioning capability of the device. Further, a person of ordinary skill in the art would have recognized that having improved electrical connections would optimize the electrical function while minimizing unwanted damage from undesirable electrical effects (see MPEP 2143.I(D)).
The combination of Jang et al, Hwang et al, and Yang now discloses
wherein the redistribution wires (150a, 150b Jang et al) are electrically connected to the landing pad (shown above in annotated Fig 1 viewed from 180 degrees Jang et al) and the first circuit patterns (circuit patterns (not illustrated) may be provided in the first surface of the first substrate 210 [0037] Jang et al/side electrodes 340 [page 3, lines 16-40] Fig 3 Yang), such that the through electrode (through electrodes 332 and 334 [page 3, lines 16-40] Fig 3 Yang) is electrically connected to at least one of the first circuit patterns (side electrodes 340 [page 3, lines 16-40] Fig 3 Yang) of the active layer (active layer 320 [page 3, lines 16-40] Fig 3 Yang) through the redistribution wires (150a, 150b Jang et al).
Claims 4-5 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al (US 2021/0111140) in view of Hwang et al (US 2013/0037942) and (KR 101088825), and in further view of Racz et al (US 2018/0166350).
Regarding Claim 4, the combination of Jang et al, Hwang et al, and Yang discloses the limitations of claim 1 as explained above. The combination of Jang et al, Hwang et al, and Yang does not directly disclose
wherein the through opening area has a circular shape.
Racz et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein the through opening area (area where TSV 15 is present [0043] Fig 5) has a circular shape (may have a circular cross-section [0043]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jang et al, Hwang et al, and Yang to include wherein the through opening area has a circular shape as taught by Racz et al in order to have better mechanical stress handling, especially through thermal cycling, by distributing stress more evenly than sharp-cornered rectangular vias. Further, a person of ordinary skill in the art would have recognized that having TSVs with a circular cross section would lead to higher reliability and better electrical performance due to more uniform current distribution and less signal distortion (see MPEP 2143.I(D)) and because it would have been an obvious matter of design choice to optimize the shape of the TSV since such a modification would have involved a mere change in shape of the component. A change in shape is generally recognized as being within the level of ordinary skill in the art In Re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) MPEP 2144.04.IV(A).
Regarding Claim 5, the combination of Jang et al, Hwang et al, Yang, and Racz et al discloses the limitations of claim 4 as explained above. The combination of Jang et al, Hwang et al, Yang, and Racz et al further discloses
wherein a diameter of the through opening area is within a range of 40 µm to 60 µm (TSV 15 may be 50 micrometers, Racz et al).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jang et al, Hwang et al, Yang, and Racz et al to include wherein the diameter of the through opening area is within a range of 40 micrometers to 60 micrometers as taught by Racz et al in order to meet the small size parameters of the device and further optimize electrical performance while maintaining reliability and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05).
Regarding Claim 14, the combination of Jang et al, Hwang et al, and Yang discloses the limitations of claim 11 as explained above. The combination of Jang et al, Hwang et al, and Yang does not directly disclose
wherein the through opening area has a circular shape.
Racz et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein the through opening area (area where TSV 15 is present [0043] Fig 5) has a circular shape (may have a circular cross-section [0043]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jang et al, Hwang et al, and Yang to include wherein the through opening area has a circular shape as taught by Racz et al in order to have better mechanical stress handling, especially through thermal cycling, by distributing stress more evenly than sharp-cornered rectangular vias. Further, a person of ordinary skill in the art would have recognized that having TSVs with a circular cross section would lead to higher reliability and better electrical performance due to more uniform current distribution and less signal distortion (see MPEP 2143.I(D)) and because it would have been an obvious matter of design choice to optimize the shape of the TSV since such a modification would have involved a mere change in shape of the component. A change in shape is generally recognized as being within the level of ordinary skill in the art In Re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) MPEP 2144.04.IV(A).
Regarding Claim 15, the combination of Jang et al, Hwang et al, Yang, and Racz et al discloses the limitations of claim 14 as explained above. The combination of Jang et al, Hwang et al, Yang, and Racz et al further discloses
wherein a diameter of the through opening area is within a range of 40 µm to 60 µm (TSV 15 may be 50 micrometers, Racz et al).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jang et al, Hwang et al, Yang, and Racz et al to include wherein the diameter of the through opening area is within a range of 40 micrometers to 60 micrometers as taught by Racz et al in order to meet the small size parameters of the device and further optimize electrical performance while maintaining reliability and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05).
Claims 6, 8, and 16-17 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al (US 2021/0111140) in view of Hwang et al (US 2013/0037942) and Yang (KR 101088825), and in further view of Savic et al (US 2013/0122658).
Regarding Claim 6, the combination of Jang et al, Hwang et al, and Yang discloses the limitations of claim 1 as explained above. The combination of Jang et al, Hwang et al, and Yang does not directly disclose
wherein the first circuit pattern area has a rectangular shape, and wherein a length of the rectangular shape is within a range of 60µm to 100µm.
Savic et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein the first circuit pattern area (area where electrical circuit component 620 is located [0068] Fig 15) has a rectangular shape (shown in Fig 15), and wherein a length of the rectangular shape is within a range of 60µm to 100µm (the ends 622 and 624 of the circuit component 620 are a selected distance (e.g. from 0 micrometer or micron to about 75 microns) from a corresponding side 602, 604 of the structure 600 [0070], and macro via 714 has a depth of between 10 microns and about 50 microns [0081] Fig 13, which would indicated a length of the first circuit pattern area may be between 0 and 100 microns based on Fig 13 (although not drawn to scale)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jang et al, Hwang et al, and Yang to include wherein the first circuit pattern area has a rectangular shape, and wherein a length of the first circuit pattern area has a rectangular shape and wherein a length of the rectangular shape is within a range of 60µm to 100µm as taught by Savic et al in order to help provide electrical function to the device and to provide support such that the circuit pattern is prevented from falling through [0068], and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05), and further it would have been an obvious matter of design choice to optimize the diameter of the wire bond since such a modification would have involved a mere change in shape of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) MPEP 2144.04.IV(B).
Regarding Claim 8, the combination of Jang et al, Hwang et al, and Yang discloses the limitations of claim 1 as explained above. The combination of Jang et al, Hwang et al, and Yang does not directly disclose
wherein each of the first circuit patterns comprises at least one of a transistor, a diode and a capacitor.
Savic et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein the first circuit pattern (electrical circuit component 620 is located [0068] Fig 15) comprises at least one of a transistor, a diode and a capacitor (may be a capacitor [0068]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jang et al, Hwang et al, and Yang to include wherein each of the first circuit patterns as a capacitor as taught by Savic et al in order to help improve the electrical functioning of the device since electrical signals may flow within the component [0068]. Further, a person of ordinary skill in the art would have recognized that having a first circuit pattern as a capacitor would be a simple substitution of one know element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
Regarding Claim 16, the combination of Jang et al, Hwang et al, and Yang discloses the limitations of claim 11 as explained above. The combination of Jang et al, Hwang et al, and Yang does not directly disclose
wherein the circuit pattern area has a rectangular shape, and wherein a length of the rectangular shape is within a range of 60µm to 100µm.
Savic et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein the circuit pattern area (area where electrical circuit component 620 is located [0068] Fig 15) has a rectangular shape (shown in Fig 15), and wherein a length of the rectangular shape is within a range of 60µm to 100µm (the ends 622 and 624 of the circuit component 620 are a selected distance (e.g. from 0 micrometer or micron to about 75 microns) from a corresponding side 602, 604 of the structure 600 [0070], and macro via 714 has a depth of between 10 microns and about 50 microns [0081] Fig 13, which would indicated a length of the first circuit pattern area may be between 0 and 100 microns based on Fig 13 (although not drawn to scale)).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jang et al, Hwang et al, and Yang to include wherein the circuit pattern area has a rectangular shape, and wherein a length of the first circuit pattern area has a rectangular shape and wherein a length of the rectangular shape is within a range of 60µm to 100µm as taught by Savic et al in order to help provide electrical function to the device and to provide support such that the circuit pattern is prevented from falling through [0068], and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05), and further it would have been an obvious matter of design choice to optimize the diameter of the wire bond since such a modification would have involved a mere change in shape of the component. A change in size is generally recognized as being within the level of ordinary skill in the art In Re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966) MPEP 2144.04.IV(B).
Regarding Claim 17, the combination of Jang et al, Hwang et al, and Yang discloses the limitations of claim 11 as explained above. The combination of Jang et al, Hwang et al, and Yang does not directly disclose
wherein each of the circuit patterns comprises at least one of a transistor, a diode and a capacitor.
Savic et al, in the related art of semiconductor devices that include semiconductor packaging, discloses
wherein the circuit pattern (electrical circuit component 620 is located [0068] Fig 15) comprises at least one of a transistor, a diode and a capacitor (may be a capacitor [0068]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jang et al, Hwang et al, and Yang to include wherein each of the circuit patterns as a capacitor as taught by Savic et al in order to help improve the electrical functioning of the device since electrical signals may flow within the component [0068]. Further, a person of ordinary skill in the art would have recognized that having a circuit pattern as a capacitor would be a simple substitution of one know element for another to obtain predictable results (see MPEP 2143.I(B)) (suitable alternate).
Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Jang et al (US 2021/0111140) in view of Hwang et al (US 2013/0037942) and Yang (KR 101088825), and in further view of Yoon (US 2011/0084410).
Regarding Claim 7, the combination of Jang et al, Hwang et al, Yang discloses the limitations of claim 1 as explained above. The combination of Jang et al, Hwang et al, and Yang does not directly disclose
wherein the active layer further comprises a second circuit pattern area that is spaced apart from the first circuit pattern area and in which second circuit patterns are located,
wherein the second circuit pattern area has a circular shape or a rectangular shape.
Yoon, in the related art of semiconductor devices that include semiconductor packaging, discloses
a second circuit pattern area (area where second wiring layer 162 is located [0054] Fig 12) that is spaced apart from the first circuit pattern area (area where the first wiring layer 132 is located [0054] Fig 12), wherein the second circuit pattern area (area where second wiring layer 162 is located) has a rectangular shape.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jang et al, Hwang et al, and Yang to include a second pattern area as taught by Yoon in order to further improve the high-speed performance [0054]. Further, a person of ordinary skill in the art would have recognized that having a second circuit pattern area would further expanding the functioning capability of the device and improve electrical performance (see MPEP 2143.I(D)).
The combination of Jang et al, Hwang et al, Yang, and Yoon now further discloses
wherein the active layer (active layer 112 [0048] Fig 15 as viewed from 180 degrees, Hwang et al/shown in Fig 1 Jang et al as viewed from 180 degrees) further comprises a second circuit pattern area (area where second wiring layer 162 is located, Yoon) that is spaced apart from the first circuit pattern area (area where second wiring layer 132 is located, Yoon) and in which second circuit patterns (area where second wiring layer 162 is located, Yoon) are located.
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Claims 9-10 and 18-19 are rejected under 35 U.S.C. 103 as being unpatentable over Jang et al (US 2021/0111140) in view of Hwang et al (US 2013/0037942) and Yang (KR 101088825), and in further view of Park et al (US 2015/0108605).
Regarding Claim 9, the combination of Jang et al, Hwang et al, and Yang discloses the limitations of claim 1 as explained above. The combination of Jang et al, Hwang et al, and Yang does not disclose
wherein the through electrode comprises a conductive plug electrically connected to the landing pad, and an insulating thin film extending around an outer surface of the conductive plug.
Park et al, in the related art of semiconductor devices that include through silicon via structures, discloses
wherein the through electrode (TSV structure 180 [0078] Fig 2) comprises a conductive plug (conductive plug 182 [0078]) electrically connected to the landing pad (TSV landing pad 170 [0073]), and an insulating thin film (via insulating layer 186 [0079]) extending around an outer surface of the conductive plug (182).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jang et al, Hwang et al, and Yang to include a TSV with a conductive plug and an insulating thin film extending around an outer surface of the conductive plug as taught by Park et al in order to provide TSV structures that exhibit stable operational characteristics and high reliability [0003]. Further, a person of ordinary skill in the art would have recognized that having improved TSV structures would help improve the electrical performance and reliability of existing 3D packages (see MPEP 2143.I(D)).
Regarding Claim 10, the combination of Jang et al, Hwang et al, and Yang discloses the limitations of claim 1 as explained above. The combination of Jang et al, Hwang et al, and Yang does not directly disclose
wherein a diameter of the first end portion of the through electrode is within a range of 45 µm to 50 µm.
Park et al, in the related art of semiconductor devices that include through silicon via structures, discloses
wherein a diameter of the via insulating layer 186 is about 500 Å (50 nm/0.05 microns) to about 2500 Å (250 nm/.25 microns) [0080] and the contact plugs 192 and 194 may have a relatively large difference in depth, which is about several micrometers [0129] (the examiner notes that although Fig 2 is not drawn to scale, the diameter of the TSV first end portion would appear to be equivalent to several micrometers when matched to the depth differences in contact plugs).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jang et al, Hwang et al, and Yang to include wherein a diameter of the first end portion of the through electrode is within a range of 45 µm to 50 µm as taught by Park et al in order to have desired resistance characteristics [0088] and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05)
Regarding Claim 18, the combination of Jang et al, Hwang et al, and Yang discloses the limitations of claim 11 as explained above. The combination of Jang et al, Hwang et al, and Yang does not disclose
wherein the through electrode comprises a conductive plug electrically connected to the landing pad, and an insulating thin film extending around an outer surface of the conductive plug.
Park et al, in the related art of semiconductor devices that include through silicon via structures, discloses
wherein the through electrode (TSV structure 180 [0078] Fig 2) comprises a conductive plug (conductive plug 182 [0078]) electrically connected to the landing pad (TSV landing pad 170 [0073]), and an insulating thin film (via insulating layer 186 [0079]) extending around an outer surface of the conductive plug (182).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jang et al, Hwang et al, and Yang to include a TSV with a conductive plug and an insulating thin film extending around an outer surface of the conductive plug as taught by Park et al in order to provide TSV structures that exhibit stable operational characteristics and high reliability [0003]. Further, a person of ordinary skill in the art would have recognized that having improved TSV structures would help improve the electrical performance and reliability of existing 3D packages (see MPEP 2143.I(D)).
Regarding Claim 19, the combination of Jang et al, Hwang et al, and Yang discloses the limitations of claim 11 as explained above. The combination of Jang et al, Hwang et al, and Yang does not directly disclose
wherein a diameter of the first end portion of the through electrode is within a range of 45 µm to 50 µm.
Park et al, in the related art of semiconductor devices that include through silicon via structures, discloses
wherein a diameter of the via insulating layer 186 is about 500 Å (50 nm/0.05 microns) to about 2500 Å (250 nm/.25 microns) [0080] and the contact plugs 192 and 194 may have a relatively large difference in depth, which is about several micrometers [0129] (the examiner notes that although Fig 2 is not drawn to scale, the diameter of the TSV first end portion would appear to be equivalent to several micrometers when matched to the depth differences in contact plugs).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Jang et al, Hwang et al, and Yang to include wherein a diameter of the first end portion of the through electrode is within a range of 45 µm to 50 µm as taught by Park et al in order to have desired resistance characteristics [0088] and because it has been held that "[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation." In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955) (see MPEP 2144.05)
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Zeng et al (US 2012/0049366) which discloses a semiconductor package structure with an embedded TSV chip [0009], and GOTO (US 2011/0210432) which discloses a semiconductor package that includes a memory chip [0017].
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812