DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 08/10/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
Claims 16-20 are objected to because of the following informalities:
There is no claim 15 in the original presentation of claims. Claims must be numbered in consecutive order. Therefore, claims 16-20 should be renumbered as claims 15-19.
Appropriate correction is required.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 14 and 16-20 are rejected under 35 U.S.C. 101 because the claimed invention is directed to non-statutory subject matter. The claim(s) does/do not fall within at least one of the four categories of patent eligible subject matter because the claim is directed to software per se. Claim 1 recites “A program product, comprising a storage device; and program code stored in the storage device that, when executed by a processor of a data processing system”, but the claim only requires code that is executable by a processor, not the processor itself. Furthermore, a storage device can be interpreted as a transitory storage medium. To overcome this rejection, the Examiner recommends amending the claim to recite “A program product, comprising a storage device; a processor; and program code stored in the storage device that, when executed by the processor of a data processing system”.
Claims 16-20 are rejected under 35 U.S.C. 101 because they are dependent on rejected claim 14.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1, 7-8, 13-14, and 20 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Bates (US 2015/0205738).
Regarding claim 1, Bates teaches a method of data processing in a data processing system, the method comprising: a processor (Fig. 1, Processor 102; Paragraph 0020, Each processor 102 executes instructions stored in the memory 104) establishing a unified input/output (I/O) translation table (Fig. 1, Processor 102 runs operating system 122 that establishes at least a single TCE 129 (i.e. unified I/O translation table); Paragraph 0024, operating systems 122… execute on the processor 102… Paragraph 0035, operating system 122 creates and maintains the entries in the TCE tables 129… operating system 122 needs to create or modify an entry in a TCE table 129, it must issue a hypervisor call… Paragraph 0023, TCE tables 129… may be packaged together), wherein the unified I/O translation table includes a plurality of translation entries for translating between I/O addresses and memory addresses (Fig. 5, TCE 129 includes plurality of entries 500 that translate between virtual I/O address and a physical memory address; Paragraph 0032, Paragraph 0032, entry 500 in a TCE table 129… contain the translation of an I/O bus page address to a memory page address… Paragraph 0035, entries the TCE tables 129 are managed); translating I/O addresses specified by direct memory access (DMA) requests received from different I/O adapters (Fig. 3, I/O adapter 106A-E makes a DMA request to I/O MMU 132 which performs translation; Paragraph 0026, I/O MMU 132 translates virtual addresses visible to various I/O devices to physical addresses of the memory 104… Paragraph 0031, Data may be moved (read or written) between the system memory 104 and the I/O adapters 106 using DMA) each allocated to respective different logical partitions (LPARs) (Figs. 2 and 3, Each I/O adapter 106A-E is mapped to LPAR 1-3) by reference to translation entries in the unified I/O translation table (Fig. 3, Each DMA request is translated via TCE 129 entries; Paragraph 0031, I/O adapter uses virtual addresses when it makes a DMA transfer. The virtual addresses are translated into physical addresses using a translation control entry (TCE) table 129); and performing accesses to physical memory of the data processing system based on memory addresses determined by the translating (Fig. 3, Physical memory 104 is accessed via translating from I/O adapter 106A-E to TCE 129 to memory P1-P5; Paragraph 0031, Host bridge hardware, e.g., I/O MMU 132, uses a TCE table 129 to convert I/O bus logical addresses to physical real addresses… Paragraph 0032, authorizes an I/O adapter to read system memory, and a write access bit, which, if set, authorizes an I/O adapter to write to system memory).
Regarding claim 7, Bates teaches the method of claim 1. Bates teaches the method further comprising: after establishing, refraining from updating translation entries in the unified I/O translation table (Fig. 7, If the page has been mapped in step 710 (i.e. after establishing the page mapping in the table), then reject mapping request in step 714 (i.e. refrain from updating); Paragraph 0043, hypervisor 120 determines whether the page has previously been exclusively mapped to a requester, e.g., an I/O adapter 106 (operation 710). The hypervisor 120 may determine whether the page has been previously mapped from the target exclusive page (TEP) table 135. If the page exclusivity flag in the TEP 135 is set for the page, then the page is exclusively associated with a particular requester, e.g., an I/O adapter 106, and the hypervisor 120 rejects the mapping request (operation 714)).
Regarding claim 8, Bates teaches a data processing system, comprising: a processor core (Fig. 1, Processor 102 with cores; Paragraph 0020, Each processor 102 executes instructions stored in the memory 104); physical memory communicatively coupled to the processor core (Fig. 1, Memory 104 is coupled to processor 102 via bus 116), wherein the physical memory stores a unified input/output (I/O) translation table (Fig. 1, Processor 102 runs operating system 122 that establishes at least a single TCE 129 (i.e. unified I/O translation table) in physical memory 104; Paragraph 0024, operating systems 122… execute on the processor 102… Paragraph 0035, operating system 122 creates and maintains the entries in the TCE tables 129… operating system 122 needs to create or modify an entry in a TCE table 129, it must issue a hypervisor call… Paragraph 0023, TCE tables 129… may be packaged together) including a plurality of translation entries for translating between I/O addresses and memory addresses (Fig. 5, TCE 129 includes plurality of entries 500 that translate between virtual I/O address and a physical memory address; Paragraph 0032, Paragraph 0032, entry 500 in a TCE table 129… contain the translation of an I/O bus page address to a memory page address… Paragraph 0035, entries the TCE tables 129 are managed); one or more I/O host bridges communicatively coupled to the physical memory (Fig. 1, I/O bus interface 118 with I/O MMU 132 is coupled to memory 104), wherein the one or more I/O host bridges are configured to perform: translating I/O addresses specified by direct memory access (DMA) requests received from different I/O adapters (Fig. 3, I/O adapter 106A-E makes a DMA request that is sent to I/O MMU 132 which translates the request; Paragraph 0026, I/O MMU 132 translates virtual addresses visible to various I/O devices to physical addresses of the memory 104… Paragraph 0031, Data may be moved (read or written) between the system memory 104 and the I/O adapters 106 using DMA) each allocated to respective different logical partitions (LPARs) (Figs. 2 and 3, Each I/O adapter 106A-E is mapped to LPAR 1-3) by reference to translation entries in the unified I/O translation table (Fig. 3, Each DMA request is translated via TCE 129 entries; Paragraph 0031, I/O adapter uses virtual addresses when it makes a DMA transfer. The virtual addresses are translated into physical addresses using a translation control entry (TCE) table 129); and performing accesses to physical memory of the data processing system based on memory addresses determined by the translating (Fig. 3, Physical memory 104 is accessed via translating from I/O adapter 106A-E to TCE 129 to memory P1-P5 using I/O MMU 132 (i.e. I/O host bridge); Paragraph 0031, Host bridge hardware, e.g., I/O MMU 132, uses a TCE table 129 to convert I/O bus logical addresses to physical real addresses… Paragraph 0032, authorizes an I/O adapter to read system memory, and a write access bit, which, if set, authorizes an I/O adapter to write to system memory).
Regarding claim 13, Bates teaches the data processing system of claim 8. Bates teaches the data processing system comprising wherein the translation entries in the unified I/O translation table are static (Fig. 7, If the page has been mapped in step 710 (i.e. after establishing the page mapping in the table), then reject mapping request in step 714 (i.e. refrain from updating); Paragraph 0043, hypervisor 120 determines whether the page has previously been exclusively mapped to a requester, e.g., an I/O adapter 106 (operation 710). The hypervisor 120 may determine whether the page has been previously mapped from the target exclusive page (TEP) table 135. If the page exclusivity flag in the TEP 135 is set for the page, then the page is exclusively associated with a particular requester, e.g., an I/O adapter 106, and the hypervisor 120 rejects the mapping request (operation 714)).
Regarding claim 14, Bates teaches a program product (Fig. 1, Program product 100), comprising: a storage device (Fig. 1, Memory 104); and program code stored in the storage device that, when executed by a processor of the data processing system (Fig. 1, Processor 102; Paragraph 0020, Each processor 102 executes instructions stored in the memory 104), causes the data processing system to perform: establishing a unified input/output (I/O) translation table (Fig. 1, Processor 102 runs operating system 122 that establishes at least a single TCE 129 (i.e. unified I/O translation table); Paragraph 0024, operating systems 122… execute on the processor 102… Paragraph 0035, operating system 122 creates and maintains the entries in the TCE tables 129… operating system 122 needs to create or modify an entry in a TCE table 129, it must issue a hypervisor call… Paragraph 0023, TCE tables 129… may be packaged together), wherein the unified I/O translation table includes a plurality of translation entries for translating between I/O addresses and memory addresses (Fig. 5, TCE 129 includes plurality of entries 500 that translate between virtual I/O address and a physical memory address; Paragraph 0032, Paragraph 0032, entry 500 in a TCE table 129… contain the translation of an I/O bus page address to a memory page address… Paragraph 0035, entries the TCE tables 129 are managed); translating I/O addresses specified by direct memory access (DMA) requests received from different I/O adapters (Fig. 3, I/O adapter 106A-E makes a DMA request to I/O MMU 132 which performs translation; Paragraph 0026, I/O MMU 132 translates virtual addresses visible to various I/O devices to physical addresses of the memory 104… Paragraph 0031, Data may be moved (read or written) between the system memory 104 and the I/O adapters 106 using DMA) each allocated to respective different logical partitions (LPARs) (Figs. 2 and 3, Each I/O adapter 106A-E is mapped to LPAR 1-3) by reference to translation entries in the unified I/O translation table (Fig. 3, Each DMA request is translated via TCE 129 entries; Paragraph 0031, I/O adapter uses virtual addresses when it makes a DMA transfer. The virtual addresses are translated into physical addresses using a translation control entry (TCE) table 129); and performing accesses to physical memory of the data processing system based on memory addresses determined by the translating (Fig. 3, Physical memory 104 is accessed via translating from I/O adapter 106A-E to TCE 129 to memory P1-P5; Paragraph 0031, Host bridge hardware, e.g., I/O MMU 132, uses a TCE table 129 to convert I/O bus logical addresses to physical real addresses… Paragraph 0032, authorizes an I/O adapter to read system memory, and a write access bit, which, if set, authorizes an I/O adapter to write to system memory).
Regarding claim 20, Bates teaches the program product of claim 14. Bates teaches the program code causes the data processing system to further perform: after the establishing, refraining from updating translation entries in the unified I/O translation table (Fig. 7, If the page has been mapped in step 710 (i.e. after establishing the page mapping in the table), then reject mapping request in step 714 (i.e. refrain from updating); Paragraph 0043, hypervisor 120 determines whether the page has previously been exclusively mapped to a requester, e.g., an I/O adapter 106 (operation 710). The hypervisor 120 may determine whether the page has been previously mapped from the target exclusive page (TEP) table 135. If the page exclusivity flag in the TEP 135 is set for the page, then the page is exclusively associated with a particular requester, e.g., an I/O adapter 106, and the hypervisor 120 rejects the mapping request (operation 714)).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2, 9, and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Bates (US 2015/0205738) in view of Shanbhogue (US 2018/0067866).
Regarding claim 2, Bates teaches the method of claim 1. Bates does not teach the method comprising wherein: the establishing includes concurrently populating the unified I/O translation table with translation entries sufficient to translate all physical memory addresses in the data processing system.
Shanbhogue teaches the method comprising wherein: the establishing includes concurrently populating the unified I/O translation table with translation entries sufficient to translate all physical memory addresses in the data processing system (Fig. 6A, Step 604 populate table; Paragraph 0030, VMM may further populate a table stored in memory with the multiple logical addresses corresponding instructions to be emulated for the virtual machine. The VMM may also store, in the VMCS, an address of the table of multiple logical addresses that the virtualization support circuitry may access along with a count that specifies the number of logical addresses in the table that require translation).
Bates and Shanbhogue are analogous arts because they are in the same field of endeavor of providing logical-to-physical translation tables memory management unit.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bates’ method to incorporate the teachings of Shanbhogue and enable concurrently populating the TCE table of Bates.
One of ordinary skill in the art would be motivated to make the modifications in order to perform error checking during the mapping, thus reducing overhead over multiple translations (See Shanbhogue: Paragraph 0031).
Regarding claim 9, Bates teaches the data processing system of claim 8. Bates does not teach the data processing system comprising wherein the unified I/O translation table is concurrently populated with translation entries sufficient to translate all physical memory addresses in the data processing system.
Shanbhogue teaches the data processing system comprising wherein the unified I/O translation table is concurrently populated with translation entries sufficient to translate all physical memory addresses in the data processing system (Fig. 6A, Step 604 populate table; Paragraph 0030, VMM may further populate a table stored in memory with the multiple logical addresses corresponding instructions to be emulated for the virtual machine. The VMM may also store, in the VMCS, an address of the table of multiple logical addresses that the virtualization support circuitry may access along with a count that specifies the number of logical addresses in the table that require translation).
Bates and Shanbhogue are analogous arts because they are in the same field of endeavor of providing logical-to-physical translation tables memory management unit.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bates’ data processing system to incorporate the teachings of Shanbhogue and enable concurrently populating the TCE table of Bates.
One of ordinary skill in the art would be motivated to make the modifications in order to perform error checking during the mapping, thus reducing overhead over multiple translations (See Shanbhogue: Paragraph 0031).
Regarding claim 16, Bates teaches the program product of claim 14. Bates does not teach the program product comprising wherein: the establishing includes concurrently populating the unified I/O translation table with translation entries sufficient to translate all physical memory addresses in the data processing system.
Shanbhogue teaches the program product comprising wherein: the establishing includes concurrently populating the unified I/O translation table with translation entries sufficient to translate all physical memory addresses in the data processing system (Fig. 6A, Step 604 populate table; Paragraph 0030, VMM may further populate a table stored in memory with the multiple logical addresses corresponding instructions to be emulated for the virtual machine. The VMM may also store, in the VMCS, an address of the table of multiple logical addresses that the virtualization support circuitry may access along with a count that specifies the number of logical addresses in the table that require translation).
Bates and Shanbhogue are analogous arts because they are in the same field of endeavor of providing logical-to-physical translation tables memory management unit.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Bates’ program product to incorporate the teachings of Shanbhogue and enable concurrently populating the TCE table of Bates.
One of ordinary skill in the art would be motivated to make the modifications in order to perform error checking during the mapping, thus reducing overhead over multiple translations (See Shanbhogue: Paragraph 0031).
Allowable Subject Matter
Claims 3-6 and 10-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claims 17-19 would be allowable if rewritten to overcome the rejection(s) under 35 U.S.C. 101, set forth in this Office action and to include all of the limitations of the base claim and any intervening claims, and if the Claim Objections are overcome.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US PGPUB 2011/0320759 to Craddock discloses a PCIe switch coupled to a plurality of I/O adapters, wherein a PCIe request is mapped to a PCI base address which is further mapped to a plurality of address translation tables.
US PGPUB 2017/0060770 to Arroyo discloses a plurality of I/O adapters coupled to a plurality of bridges, wherein an I/O DMA request is sent from an endpoint and is translated to a physical address at a table.
US PGPUB 2012/0265916 to Nordstrom discloses a plurality of I/O adapters that transmit DMA requests to be translated at a memory storing a plurality of address translation tables.
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/H.Z.W./Examiner, Art Unit 2184
/HENRY TSAI/Supervisory Patent Examiner, Art Unit 2184
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