DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The Amendments, filed on 12/27/2025, have been received and made of record. In response to the most recent Office Action, dated 09/29/2025, claims 2-8, 12 and 15-17 have been amended. Claims 1-20 are current pending.
Response to Arguments
Applicant’s Amendments, filed on 12/27/2025, have been entered and fully considered. The Applicant has not amended independent claim 1 and has amended independent claim 15 to fix minor antecedent basis issues and has presented a set of arguments pointing out their rational of why they believe the prior art references made of record in the most recent Office Action do not teach the currently recited claim limitations in both of these independent claims. Applicant's arguments have been fully considered but they are not persuasive.
The Applicant in their submitted remarks presents the argument that Lu (CN 108319323 B – Translation Attached) in view of Chen (US 5796244) does not teach the limitation of “a current generator referenced to a first potential and configured to generate a first current i3 having a negative temperature-dependent voltage component and a positive temperature- dependent voltage component” recited in claim 1 and the limitation of “generating a first current referenced to a first potential, the first current having a negative temperature-dependent voltage component and a positive temperature-dependent voltage component” recited in claim 15. The argument presented by the Applicant has been reproduced below for purposes of clarity and is also found on pages 13-14 of the submitted remarks.
Lu fails to disclose "a current generator referenced to a first potential and configured to generate a first current i3 having a negative temperature-dependent voltage component and a positive temperature-dependent voltage component" as recited by claim 1. As disclosed in Lu, paragraph [0010], Lu teaches a CMOS high-temperature reference voltage source that uses MOSFET and resistor combinations through binary weighted combinations, but does not employ a BJT-based bandgap architecture. Lu's reference voltage VREF1 is characterized by "VREF1=K(- Vtn)+Vtx" as shown in Lu, paragraph [0077], where the temperature coefficient depends on threshold voltages of NMOS transistors. As explained in Lu, paragraph [0082], temperature compensation is achieved by adjusting the control coefficient K through switching different numbers of MOSFET devices.
The examiner's reliance on Chen to cure this deficiency is misplaced. Chen teaches "a bandgap voltage referenced generating means to generate a first referencing voltage having a first temperature coefficient" and "a compensating voltage generating means to generate a second referencing voltage having a second temperature coefficient, wherein the second temperature coefficient is approximately equal and of opposite sign to said first temperature coefficient." Chen, Column 8, Lines 7-15; Chen, Column 6, Lines 24-33. Chen explicitly uses separate and distinct generators for each temperature coefficient, not a single current generator that produces both coefficients as required by claim 1. Chen's bandgap voltage referenced generating means comprises separate constant current sources, resistors, and bipolar junction transistors to generate the first referencing voltage, as shown in Chen, Column 6, Lines 49-57 and Column 6, Lines 55-63, while the compensating voltage generating means comprises a separate third bipolar junction transistor and second resistor to generate the second referencing voltage, as disclosed in Chen, Columns 7-8, Lines 58-66. This architecture is fundamentally different from the claimed single current generator that produces both temperature-dependent voltage components.
The combination of Lu and Chen cannot teach the claimed limitation because Lu's temperature compensation mechanism relies on MOSFET threshold voltage variations and switching, while Chen's approach uses separate generators for opposite temperature coefficients. Neither reference teaches or suggests a single current generator that inherently produces both negative and positive temperature-dependent voltage components as required by "a current generator...configured to generate a first current i3 having a negative temperature-dependent voltage component and a positive temperature-dependent voltage component" recited in claim 1.
The Examiner respectfully disagrees and would like to start off by pointing out that one cannot show non-obviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Furthermore, the test for obviousness is not whether the features of a secondary reference may be bodily incorporated into the structure of the primary reference; nor is it that the claimed invention must be expressly suggested in any one or all of the references. Rather, the test is what the combined teachings of the references would have suggested to those of ordinary skill in the art. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981). Based on that the Examiner would like to highlight that the rejection made does not rely on Chen to disclose a single current generator, but rather for the teaching of generating a current having a PTAT and CTAT voltage component which would have been obvious to incorporate into the current generation scheme of Lu. Lu already discloses a temperature-dependent current generated using MOSFETs and it would have been within the level of one of ordinary skill in the art to modify Lu to incorporate both positive and negative temperature dependent components as disclosed by Chen to achieve a temperature independent voltage at the output to improve the system’s temperature stability. The substitution being made in this combination is not one of physically adding the circuit of Chen into Lu but rather the technique of Chen being modified into the circuit of Lu. Furthermore, Applicant’s argument that Chen teaches separate generators is not persuasive as the claims do not recite any structural limitation that would preclude multiple components being grouped together to be called “a current generator”.
An argument regarding claim 11 is also submitted by the Applicant as seen on Page 15 of the submitted remarks. This argument relies on the argument presented above and based on the above argument not being persuasive this argument is also found to be not persuasive.
Based on the reasoning provided above the Examiner the rejection under 35 U.S.C. 103 is maintained and made final.
Claim Rejections
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lu (CN 108319323 B – Translation Attached) in view of Chen (US 5796244).
Regarding claim 1, Lu teaches a bandgap reference circuit (Figure 4) comprising: a current generator (Figure 4 Components P1+P2+N1+N2+N3) referenced to a first potential (Figure 4 Component VSS; Translation Paragraph 43 “the source of N3 is grounded or power VSS, the source of P1 is connected to the power supply VDD”; This passage highlights that N3 can be grounded or connected to VSS so the Examiner has taken the interpretation that is connected to Component VSS) and configured to generate a first current i3 having a temperature-dependent voltage component (Figure 4 Component IB outputted by Component P2; Translation Paragraphs 32 and 70); a first current mirror referenced to the first potential (Figure 4 Components M2 and M2; Translation Paragraph 47 “M1 and M2 form a first current mirror”; Components M2 and M1 are connected to Component VSS) and configured to receive the first current i3 from the current generator and to generate a second current i5 equal to the first current i3 (Translation Paragraph 47); a second current mirror (Figure 4 Components M3 and M4; Translation Paragraph 47 “M3 and M4 in the reference core circuit form a second current mirror”) referenced to a second potential (Figure 4 Components M3 and M4 are connected to Component VDD which can be seen as the second potential) and configured to receive the second current i5 from the first current mirror (Translation Paragraph 47 “The bias current IB is calculated by dividing the difference between the gate-source voltages Vgs of M1 and M2 by the resistance of RB. Then, the bias current is transmitted to the reference core circuit through the second current mirror formed by M3 and M4”) and to generate a third current i7 from the second current i5 (Figure 4 Component IREF; Translation Paragraph 54); and a reference voltage generator (Figure 4 Components Mn2 and R2) referenced to a third potential (Paragraph 71 highlights that M4 can be connected to ground or VSS through Mn2 and R2 and for this instance the Examiner understands it to be connected to ground thus being a third potential) and configured to receive the third current i7 from the second current mirror and to generate a reference voltage Vref that is referenced to the third potential (Figure 4 Component VREF2).
Lu does not teach a current generator referenced to a first potential and configured to generate a first current i3 having a negative temperature-dependent voltage component and a positive temperature-dependent voltage component; and that the third current i7 is equal to the second current i5.
Chen teaches a bandgap voltage reference circuit (Figure 4), comprising: a current generator (Figure 4 Components Q135+Q134+OPAMP+P130) referenced to a first potential (Figure 4 Component VBB) and configured to generate a first current i3 (Figure 4 Component P130 output) having a negative temperature-dependent voltage component and a positive temperature-dependent voltage component (Col. 4 Lines 18-26 “a bandgap voltage referenced generator that will generate a first referencing voltage having a first temperature coefficient, and a compensating voltage generator that will generate a second referencing voltage having a second temperature coefficient. The second temperature coefficient is approximately equal and of opposite sign to the first temperature coefficient. A voltage summing means will sum the first referencing voltage and the second referencing voltage to create the temperature independent voltage”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Lu to incorporate having a negative temperature-dependent voltage component and a positive temperature-dependent voltage component as taught by Chen. The advantage of this design is that it will create a temperature independent voltage at the output enhancing the efficiency of the bandgap reference voltage circuit to provide a more accurate voltage reference while reducing the overall complexity of the system.
Lu and Chen in combination still do not teach that the third current i7 is equal to the second current i5. However, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. Iii re Boesch, Eli f.2d 272, 205 USPQ 215. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the currents equal to provide a more accurate voltage reference according to the temperature sensed.
Regarding claim 2, Lu and Chen teach all the limitations of claim 1. Lu further teaches wherein the first potential is a negative bias potential (Figure 4 Component VSS); the second potential is a positive supply potential (Figure 4 Component VCC); and the third potential is ground (Figure 4 Component Ground; Paragraph 71 highlights that M4 can be connected to ground or VSS through Mn2 and R2 and for this instance the Examiner understands it to be connected to ground thus being a third potential).
Lu does not teach wherein the first potential is a negative bias potential of a substrate of an integrated circuit on which the bandgap voltage reference circuit is formed.
Chen teaches a bandgap voltage reference circuit (Figure 4), comprising: a current generator (Figure 4 Components Q135+Q134+OPAMP+P130) referenced to a first potential (Figure 4 Component VBB) and configured to generate a first current i3 (Figure 4 Component P130 output) having a negative temperature-dependent voltage component and a positive temperature-dependent voltage component (Col. 4 Lines 18-26 “a bandgap voltage referenced generator that will generate a first referencing voltage having a first temperature coefficient, and a compensating voltage generator that will generate a second referencing voltage having a second temperature coefficient. The second temperature coefficient is approximately equal and of opposite sign to the first temperature coefficient. A voltage summing means will sum the first referencing voltage and the second referencing voltage to create the temperature independent voltage”), wherein the first potential is a negative bias potential (Figure 4 Component VBB; Figure 5 Component VBB; Col. 5 Lines 30-34) of a substrate of an integrated circuit on which the bandgap voltage reference circuit is formed (Figure 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Lu to incorporate having a negative temperature-dependent voltage component and a positive temperature-dependent voltage component as taught by Chen. The advantage of this design is that it will create a temperature independent voltage at the output enhancing the efficiency of the bandgap reference voltage circuit to provide a more accurate voltage reference while reducing the overall complexity of the system.
Regarding claim 15, Lu teaches a method (Figure 4) for generating a reference voltage (Figure 4 Component VREF2), the method comprising: generating a first current (Figure 4 Components P1+P2+N1+N2+N3; Figure 4 Component IB outputted by Component P2; Translation Paragraphs 32 and 70) referenced to a first potential (Figure 4 Component VSS; Translation Paragraph 43 “the source of N3 is grounded or power VSS, the source of P1 is connected to the power supply VDD”; This passage highlights that N3 can be grounded or connected to VSS so the Examiner has taken the interpretation that is connected to Component VSS), the first current having temperature-dependent voltage component (Translation Paragraphs 32 and 70); generating a second current that is equal to the first current and that is referenced to the first potential (Figure 4 Components M2 and M2; Translation Paragraph 47 “M1 and M2 form a first current mirror”; Components M2 and M1 are connected to Component VSS; Translation Paragraph 47); generating a third current from the second current and that is referenced to a second potential (Figure 4 Components M3 and M4 are connected to Component VDD which can be seen as the second potential; Translation Paragraph 47 “The bias current IB is calculated by dividing the difference between the gate-source voltages Vgs of M1 and M2 by the resistance of RB. Then, the bias current is transmitted to the reference core circuit through the second current mirror formed by M3 and M4”; Figure 4 Component IREF; Translation Paragraph 54); and generating a reference voltage from the third current that is referenced to a third potential (Figure 4 Components Mn2 and R2; Paragraph 71 highlights that M4 can be connected to ground or VSS through Mn2 and R2 and for this instance the Examiner understands it to be connected to ground thus being a third potential; Figure 4 Component VREF2).
Lu does not teach the first current having a negative temperature-dependent voltage component and a positive temperature-dependent voltage component; and wherein the third current is equal to the second current.
Chen teaches a bandgap voltage reference circuit (Figure 4), comprising: a current generator (Figure 4 Components Q135+Q134+OPAMP+P130) referenced to a first potential (Figure 4 Component VBB) and configured to generate a first current i3 (Figure 4 Component P130 output) having a negative temperature-dependent voltage component and a positive temperature-dependent voltage component (Col. 4 Lines 18-26 “a bandgap voltage referenced generator that will generate a first referencing voltage having a first temperature coefficient, and a compensating voltage generator that will generate a second referencing voltage having a second temperature coefficient. The second temperature coefficient is approximately equal and of opposite sign to the first temperature coefficient. A voltage summing means will sum the first referencing voltage and the second referencing voltage to create the temperature independent voltage”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Lu to incorporate having a negative temperature-dependent voltage component and a positive temperature-dependent voltage component as taught by Chen. The advantage of this design is that it will create a temperature independent voltage at the output enhancing the efficiency of the bandgap reference voltage circuit to provide a more accurate voltage reference while reducing the overall complexity of the system.
Lu and Chen in combination still do not teach that the third current i7 is equal to the second current i5. However, it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. Iii re Boesch, Eli f.2d 272, 205 USPQ 215. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the currents equal to provide a more accurate voltage reference according to the temperature sensed.
Regarding claim 16, Lu and Chen teach all the limitations of claim 15. Lu further teaches wherein the first potential is a negatively biased (Figure 4 Component VSS); the second potential is a positive supply potential (Figure 4 Component VCC); and the third potential is ground (Figure 4 Component Ground; Paragraph 71 highlights that M4 can be connected to ground or VSS through Mn2 and R2 and for this instance the Examiner understands it to be connected to ground thus being a third potential).
Lu does not teach wherein the first potential is a negatively biased substrate of an integrated circuit.
Chen teaches a bandgap voltage reference circuit (Figure 4), comprising: a current generator (Figure 4 Components Q135+Q134+OPAMP+P130) referenced to a first potential (Figure 4 Component VBB) and configured to generate a first current i3 (Figure 4 Component P130 output) having a negative temperature-dependent voltage component and a positive temperature-dependent voltage component (Col. 4 Lines 18-26 “a bandgap voltage referenced generator that will generate a first referencing voltage having a first temperature coefficient, and a compensating voltage generator that will generate a second referencing voltage having a second temperature coefficient. The second temperature coefficient is approximately equal and of opposite sign to the first temperature coefficient. A voltage summing means will sum the first referencing voltage and the second referencing voltage to create the temperature independent voltage”), wherein the first potential is a negative bias potential (Figure 4 Component VBB; Figure 5 Component VBB; Col. 5 Lines 30-34) of a substrate of an integrated circuit on which the bandgap voltage reference circuit is formed (Figure 5).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Lu to incorporate having a negative temperature-dependent voltage component and a positive temperature-dependent voltage component as taught by Chen. The advantage of this design is that it will create a temperature independent voltage at the output enhancing the efficiency of the bandgap reference voltage circuit to provide a more accurate voltage reference while reducing the overall complexity of the system.
Claim 11 is rejected under 35 U.S.C. 103 as being unpatentable over Lu (CN 108319323 B – Translation Attached) in view of Chen (US 5796244) and in further view of Mahmoodi (US 2024/0077903 A1).
Regarding claim 11, Lu and Chen teach all the limitations of claim 1. Lu does not teach a hard disk drive comprising the bandgap reference circuit of claim 1.
Mahmoodi teaches a bandgap reference circuit (Figure 3A) within a hard disk drive (Figure 15; Paragraphs 0102-0106).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Lu to incorporate the bandgap reference circuit within a hard disk system as taught by Mahmoodi. The advantage of this is for providing an accurate voltage reference to the Hard Disk Drive since it operate within a wide temperature range thus ensuring reliable operation during power supply variations.
Allowable Subject Matter
Claims 3-10 and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 3, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests wherein the current generator comprises a first P-channel Metal-Oxide-Semiconductor (PMOS) transistor having its source coupled to the third potential, its gate coupled to the output of the operational amplifier, and its drain coupled to the inverting input of the operational amplifier; a second PMOS transistor having its source coupled to the third potential, its gate coupled to the output of the operational amplifier, and its drain coupled to the non-inverting input of the operational amplifier; a third PMOS transistor having its source coupled to the third potential, its gate coupled to the output of the operational amplifier; and its drain coupled to the first current mirror; a first resistor R0 coupled between the drain of the first PMOS transistor and the first potential; a second resistor R1 coupled between the drain of the second PMOS transistor and the first potential; a first positive negative positive bipolar junction transistor (PNP BJT) having its emitter coupled to the drain of the first PMOS transistor, and its base and collector coupled to the first potential; a second PNP BJT having its emitter coupled to a third resistor R2, and its base and collector coupled to the first potential; and the third resistor R2 being coupled between the drain of the second PMOS transistor and the emitter of the second PNP BJT. Claims 4-10 depend upon claim 3.
Regarding claim 17, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests utilizing a current generator comprising: first, second and third P-channel Metal-Oxide-Semiconductor (PMOS) transistors, each with their sources grounded and their gates coupled to an output of the operational amplifier, wherein the first PMOS transistor has its drain coupled to an inverting input of the operational amplifier and the second PMOS transistor has its drain coupled to a non-inverting input of the operational amplifier; first and second resistors R0 and R1 respectively coupling the drains of the first and second PMOS transistors to the negatively biased substrate; first and second positive negative positive bipolar junction transistors (PNP BJTs), each with their bases and collectors coupled to the negatively biased substrate, wherein an emitter of the first PNP BJT is coupled to the drain of the first PMOS transistor; and a third resistor R2 coupled between the emitter of the second PNP BJT and the drain of the second PMOS transistor, wherein the first current flows through each of the first, second and third PMOS transistors in a direction from ground to the negatively biased substrate. Claims 18-20 depend upon claim 17
Claims 12-14 are allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding claim 12, none of the prior art, made of record, singularly or in combinations, teaches or fairly suggests first, second and third P-channel Metal-Oxide-Semiconductor (PMOS) transistors, each with their sources grounded and their gates coupled to an output of the operational amplifier, wherein the first PMOS transistor has its drain coupled to an inverting input of the operational amplifier and the second PMOS transistor has its drain coupled to a non-inverting input of the operational amplifier; first and second resistors R0 and R1, equal in resistance, coupling the drains of the first and second PMOS transistors to a negatively biased substrate; first and second positive negative positive bipolar junction transistors (PNP BJTs), each with their bases and collectors coupled to the negatively biased substrate, wherein an emitter of the first PNP BJT is coupled to the drain of the first PMOS transistor; a third resistor R2 coupled between the emitter of the second PNP BJT and the drain of the second PMOS transistor. Claims 13 and 14 depend upon claim 12.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Shahzeb K. Ahmad whose telephone number is (571)272-0978. The examiner can normally be reached Monday - Friday 8 A.M. to 5 P.M..
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/Shahzeb K Ahmad/Examiner, Art Unit 2838
/THIENVU V TRAN/Supervisory Patent Examiner, Art Unit 2838
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