Prosecution Insights
Last updated: October 04, 2026
Application No. 18/447,631

OPTOELECTRONIC SEMICONDUCTOR CHIP

Non-Final OA §103
Filed
Aug 10, 2023
Priority
Mar 15, 2018 — DE 102018106001.7 +4 more
Examiner
YEUNG LOPEZ, FEIFEI
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Osram GmbH
OA Round
3 (Non-Final)
81%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
79%
With Interview

Examiner Intelligence

Grants 81% — above average
81%
Career Allowance Rate
884 granted / 1088 resolved
+13.3% vs TC avg
Minimal -3% lift
Without
With
+-2.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 5m
Avg Prosecution
34 currently pending
Career history
1123
Total Applications
across all art units

Statute-Specific Performance

§101
0.4%
-39.6% vs TC avg
§103
55.2%
+15.2% vs TC avg
§102
24.1%
-15.9% vs TC avg
§112
17.3%
-22.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1088 resolved cases

Office Action

§103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Continued Examination Under 37 CFR 1.114 A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on June 16, 2026 has been entered. Claim Rejections - 35 USC § 103 The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action. Claim(s) 1-5 and 8-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki (US Patent 5,404,031), Kim et al (WO 2017/069372 A1), Sasaki (PG Pub 2015/0357525 A1, hereafter Sasaki525), Avramescu et al (PG Pub 2011/0051771 A1), and Kawase (US Patent 6,756,732 B1). Regarding claim 1, Sasaki teaches an optoelectronic semiconductor chip comprising: a semiconductor layer sequence (32’-34’, fig. 7) having an active zone (33’) for generating radiation with a wavelength of maximum intensity L (inherent), denoted as “L”, a mirror (reflector 41’, column 6, lines 10-21) for the radiation on a rear side opposite a light extraction side, the mirror is arranged on a p-doped (p-GaAlAs 32’, column 6, lines 10-21) side of the semiconductor layer sequence, least one electrode layer (38) and the at least one metal layer is configured to supply current (dotted lines, fig. 4B) to the p-doped side of the semiconductor layer sequence. Sasaki does not teach the mirror to comprise a cover layer. In the same field of endeavor, Kim teaches a mirror (41 and 43, paragraph [0070], figs. 4A and 5) for the radiation on a rear side opposite a light extraction side (upper side of fig. 4A, paragraph [0068]), wherein the mirror comprises a cover layer (41) located closest to the semiconductor layer sequence, the cover layer is formed with a material transparent (implied in the reference, since light passes through it to reach the reflector) to the radiation and has an optical thickness between 0.5 L and 5 L inclusive (400 nm thick, paragraph [0070], for light with wavelength of 554 nm, paragraphs [0077]), the cover layer is followed by between inclusive 2 and inclusive 10 intermediate layers (any two to ten layers in fig. 5) in a direction away from the semiconductor layer sequence, the intermediate layers have alternately high and low refractive indices (abstract) for the radiation and are each made of a material transparent to the radiation, for the known benefit of increasing light extraction. Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to include a mirror for the radiation on a rear side opposite a light extraction side, wherein the mirror comprised a cover layer located closest to the semiconductor layer sequence, the cover layer is formed with a material transparent to the radiation and has an optical thickness between 0.5 L and 5 L inclusive, the cover layer was followed by between inclusive 2 and inclusive 10 intermediate layers in a direction away from the semiconductor layer sequence, the intermediate layers have alternately high and low refractive indices for the radiation and are each made of a material transparent to the radiation, for the known benefit of increasing light extraction. Kim does not teach the intermediate layers are followed in the direction away from the semiconductor layer sequence by at least one metal layer as a reflection layer. In the same field of endeavor, Sasaki525 teaches the intermediate layers (107, fig. 12) are followed in the direction away from the semiconductor layer sequence (103) by at least one metal layer as a reflection layer (108, paragraph [0016]), for the benefit of increasing light extraction (paragraph [0016]). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to include at least one metal layer as a reflection layer following the intermediate layers in the direction away from the semiconductor layer sequence for the benefit of increasing light extraction. According to the amendment in claim 1, Applicant seems to intend to limit the number of the intermediate layers. Because the preamble uses an open-ended word “comprising,” the body is presumed to contain elements not recited. Thus, the added limitation “a total number of” does not exclude the number of layers between the cover layer and the metal layer to two to ten; Especially the claim does not require the metal to contact the any of the intermediate layers. MPEP 2111.03: The transitional term "comprising", which is synonymous with "including," "containing," or "characterized by," is inclusive or open-ended and does not exclude additional, unrecited elements or method steps. See, e.g., Mars Inc. v. H.J. Heinz Co., 377 F.3d 1369, 1376, 71 USPQ2d 1837, 1843 (Fed. Cir. 2004) ("[L]ike the term ‘comprising,’ the terms ‘containing’ and ‘mixture’ are open-ended."). Invitrogen Corp. v. Biocrest Manufacturing, L.P., 327 F.3d 1364, 1368, 66 USPQ2d 1631, 1634 (Fed. Cir. 2003) ("The transition ‘comprising’ in a method claim indicates that the claim is open-ended and allows for additional steps."); Genentech, Inc. v. Chiron Corp., 112 F.3d 495, 501, 42 USPQ2d 1608, 1613 (Fed. Cir. 1997) ("Comprising" is a term of art used in claim language which means that the named elements are essential, but other elements may be added and still form a construct within the scope of the claim.); Moleculon Research Corp. v. CBS, Inc., 793 F.2d 1261, 229 USPQ 805 (Fed. Cir. 1986); In re Baxter, 656 F.2d 679, 686, 210 USPQ 795, 803 (CCPA 1981); Ex parte Davis, 80 USPQ 448, 450 (Bd. App. 1948) ("comprising" leaves "the claim open for the inclusion of unspecified ingredients even in major amounts"). In Gillette Co. v. Energizer Holdings Inc., 405 F.3d 1367, 1371-73, 74 USPQ2d 1586, 1589-91 (Fed. Cir. 2005). Furthermore, it would have been obvious to the skilled in the art before the effective filing date of the invention to adjust the total number of reflective layers (DBR in the cited art or “intermediate layers” claimed) according to the intended use of the device to balance the cost and the reflectivity of the reflector. On one hand, as mentioned by Applicant, increasing the number of layers in the DBR enhances the reflectivity of the DBR. On the other hand, the higher the layer number the greater the manufacturing cost and time to make them (paragraph [0023] of Avramescu and column 3, lines 40-44 of Kawase). “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Regarding claim 2, Kim teaches the optoelectronic semiconductor chip according to claim 1, wherein a thickness of at least one of the intermediate layers is unequal to L/4 (fig. 5). Regarding claim 3, Kim teaches the optoelectronic semiconductor chip according to claim 1, wherein at least 50% (one layer) of the intermediate layers (two layers in fig. 5) have an optical thickness of L/3, with a tolerance of not more than L/15 (fig. 5). Regarding claim 4, Kim teaches the optoelectronic semiconductor chip according to claim 1, wherein the mirror comprises three (three SiO2 between 0.3 and 0.35) or four of the intermediate layers and the intermediate layers each have an optical thickness of L/3, with a tolerance of at most L/20. Regarding claim 5, Kim teaches the optoelectronic semiconductor chip according to claim 1, wherein the mirror comprises at most two intermediate layers (two layers between 0.2 and 0.3, fig. 5) with an optical thickness of (L/4+N/2)+/-L/20, wherein N is a natural number greater than or equal to zero (N equals zero). Regarding claim 8, Kim teaches the optoelectronic semiconductor chip according to claim 1, wherein an optical thickness of at least three of the intermediate layers increases in a direction away from the cover layer (see 1,2,3 labeled in fig. 5), wherein a difference in optical thickness between adjacent ones of the intermediate layers is between 0.03 L and 0.15 L, inclusive (fig. 5). PNG media_image1.png 542 786 media_image1.png Greyscale Regarding claim 9, Kim teaches the optoelectronic semiconductor chip according to claim 1, wherein the cover layer is of SiO2 (paragraphs [0078][0080]) and/or the intermediate layers are alternately of Nb205 and SiO2. Sasaki teaches wherein the metal layer is of gold, silver (paragraph [0015]) or aluminum. Regarding claim 10, Sasaki teaches the optoelectronic semiconductor chip according to claim 1, wherein the semiconductor layer sequence is based on AlInGaAs (column 6, lines 10-21) or on InGaAlP and/or the wavelength of maximum intensity L is between 570 nm and 950 nm inclusive. Regarding claim 11, Kim teaches the optoelectronic semiconductor chip according to claim 1, wherein each intermediate layer is of a separate material (fig. 5, paragraph [0080]). Regarding claim 12, Kim in view of Sasaki teaches the optoelectronic semiconductor chip according to claim 1, wherein the mirror together with the metal layer is made of three different materials (fig. 5 of Kim and paragraph [0015] of Sasaki). Regarding claim 13, Kim teaches the optoelectronic semiconductor chip according to claim 1, wherein the cover layer and the intermediate layers are congruent with each other (fig. 4A). Regarding claim 14, Kim in view of Sasaki teaches the optoelectronic semiconductor chip according to claim 1, wherein the cover layer, the intermediate layers and the metal layer are congruent with each other (fig. 4A of Kim and fig. 12 of Sasaki). Regarding claim 15, Kim teaches the optoelectronic semiconductor chip according to claim 1, wherein the cover layer and/or one of the intermediate layers (4, fig. 1B) protrude laterally beyond the metal layer (61). Claim(s) 16 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sasaki (US Patent 5,404,031), Kim et al (WO 2017/069372 A1), Sasaki (PG Pub 2015/0357525 A1, hereafter Sasaki525), Avramescu et al (PG Pub 2011/0051771 A1), and Kawase (US Patent 6,756,732 B1) as applied to claim 1 above, and further in view of Hadji et al (PG Pub 2004/0175901 A1). Regarding claim 16, the previous combination remains as applied in claim 1. The previous combination does not teach the total number of intermediate layers is between 3 and 8, inclusive. Kim teaches the total number of intermediate layers can be changed (paragraph [0103]). Furthermore, in the same field of endeavor, Hadji teaches the total number of intermediate layers may be adjusted depending on the reflection properties required (paragraph [0095]). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to adjust the total number of intermediate layers is between 3 and 8, inclusive, to optimize the reflection properties according to the intended use of the device. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Regarding claim 17, the previous combination remains as applied in claim 1. The previous combination does not teach the total number of intermediate layers is between 4 and 7, inclusive. Kim teaches the total number of intermediate layers can be changed (paragraph [0103]). Furthermore, in the same field of endeavor, Hadji teaches the total number of intermediate layers may be adjusted depending on the reflection properties required (paragraph [0095]). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to adjust the total number of intermediate layers is between 4 and 7, inclusive, to optimize the reflection properties according to the intended use of the device. “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Edmond et al (PG Pub 2009/0166659 A1), Kim et al (WO 2017/069372 A1), Sasaki (PG Pub 2015/0357525 A1, hereafter Sasaki525), Avramescu et al (PG Pub 2011/0051771 A1), and Kawase (US Patent 6,756,732 B1). Regarding claim 1, Edmond teaches an optoelectronic semiconductor chip comprising: a semiconductor layer sequence (26,22,27, fig. 12) having an active zone (22, paragraph [0074]) for generating radiation with a wavelength of maximum intensity L (inherent), denoted as “L”, a mirror (reflectors 61 and/or 65, paragraphs [0075][0077]) for the radiation on a rear side opposite a light extraction side, the optoelectronic semiconductor chip is free of a growth substrate (fig. 12), the mirror is arranged on a p-doped (26, paragraph [0074]) side of the semiconductor layer sequence, least one electrode layer (metal 61 and/or 65, paragraphs [0075][0077]) and the at least one metal layer is configured to supply current (fig. 12) to the p-doped side of the semiconductor layer sequence. Sasaki does not teach the mirror to comprise a cover layer. In the same field of endeavor, Kim teaches a mirror (41 and 43, paragraph [0070], figs. 4A and 5) for the radiation on a rear side opposite a light extraction side (upper side of fig. 4A, paragraph [0068]), wherein the mirror comprises a cover layer (41) located closest to the semiconductor layer sequence, the cover layer is formed with a material transparent (implied in the reference, since light passes through it to reach the reflector) to the radiation and has an optical thickness between 0.5 L and 5 L inclusive (400 nm thick, paragraph [0070], for light with wavelength of 554 nm, paragraphs [0077]), the cover layer is followed by between inclusive 2 and inclusive 10 intermediate layers (any two to ten layers in fig. 5) in a direction away from the semiconductor layer sequence, the intermediate layers have alternately high and low refractive indices (abstract) for the radiation and are each made of a material transparent to the radiation, for the known benefit of increasing light extraction. Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to include a mirror for the radiation on a rear side opposite a light extraction side, wherein the mirror comprised a cover layer located closest to the semiconductor layer sequence, the cover layer is formed with a material transparent to the radiation and has an optical thickness between 0.5 L and 5 L inclusive, the cover layer was followed by between inclusive 2 and inclusive 10 intermediate layers in a direction away from the semiconductor layer sequence, the intermediate layers have alternately high and low refractive indices for the radiation and are each made of a material transparent to the radiation, for the known benefit of increasing light extraction. Kim does not teach the intermediate layers are followed in the direction away from the semiconductor layer sequence by at least one metal layer as a reflection layer. In the same field of endeavor, Sasaki525 teaches the intermediate layers (107, fig. 12) are followed in the direction away from the semiconductor layer sequence (103) by at least one metal layer as a reflection layer (108, paragraph [0016]), for the benefit of increasing light extraction (paragraph [0016]). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to include at least one metal layer as a reflection layer following the intermediate layers in the direction away from the semiconductor layer sequence for the benefit of increasing light extraction. According to the amendment in claim 1, Applicant seems to intend to limit the number of the intermediate layers. Because the preamble uses an open-ended word “comprising,” the body is presumed to contain elements not recited. Thus, the added limitation “a total number of” does not exclude the number of layers between the cover layer and the metal layer to two to ten; Especially the claim does not require the metal to contact the any of the intermediate layers. MPEP 2111.03: The transitional term "comprising", which is synonymous with "including," "containing," or "characterized by," is inclusive or open-ended and does not exclude additional, unrecited elements or method steps. See, e.g., Mars Inc. v. H.J. Heinz Co., 377 F.3d 1369, 1376, 71 USPQ2d 1837, 1843 (Fed. Cir. 2004) ("[L]ike the term ‘comprising,’ the terms ‘containing’ and ‘mixture’ are open-ended."). Invitrogen Corp. v. Biocrest Manufacturing, L.P., 327 F.3d 1364, 1368, 66 USPQ2d 1631, 1634 (Fed. Cir. 2003) ("The transition ‘comprising’ in a method claim indicates that the claim is open-ended and allows for additional steps."); Genentech, Inc. v. Chiron Corp., 112 F.3d 495, 501, 42 USPQ2d 1608, 1613 (Fed. Cir. 1997) ("Comprising" is a term of art used in claim language which means that the named elements are essential, but other elements may be added and still form a construct within the scope of the claim.); Moleculon Research Corp. v. CBS, Inc., 793 F.2d 1261, 229 USPQ 805 (Fed. Cir. 1986); In re Baxter, 656 F.2d 679, 686, 210 USPQ 795, 803 (CCPA 1981); Ex parte Davis, 80 USPQ 448, 450 (Bd. App. 1948) ("comprising" leaves "the claim open for the inclusion of unspecified ingredients even in major amounts"). In Gillette Co. v. Energizer Holdings Inc., 405 F.3d 1367, 1371-73, 74 USPQ2d 1586, 1589-91 (Fed. Cir. 2005). Furthermore, it would have been obvious to the skilled in the art before the effective filing date of the invention to adjust the total number of reflective layers (DBR in the cited art or “intermediate layers” claimed) according to the intended use of the device to balance the cost and the reflectivity of the reflector. On one hand, as mentioned by Applicant, increasing the number of layers in the DBR enhances the reflectivity of the DBR. On the other hand, the higher the layer number the greater the manufacturing cost and time to make them (paragraph [0023] of Avramescu and column 3, lines 40-44 of Kawase). “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Claim(s) 1 and 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Edmond et al (PG Pub 2009/0166659 A1), Kim et al (PG Pub 2016/0351754 A1), Avramescu et al (PG Pub 2011/0051771 A1), and Kawase (US Patent 6,756,732 B1). Regarding claim 1, Edmond teaches an optoelectronic semiconductor chip comprising: a semiconductor layer sequence (26,22,27, fig. 12) having an active zone (22, paragraph [0074]) for generating radiation with a wavelength of maximum intensity L (inherent), denoted as “L”, a mirror (reflectors 61 and/or 65, paragraphs [0075][0077]) for the radiation on a rear side opposite a light extraction side, the optoelectronic semiconductor chip is free of a growth substrate (fig. 12), the mirror is arranged on a p-doped (26, paragraph [0074]) side of the semiconductor layer sequence, least one electrode layer (metal 61 and/or 65, paragraphs [0075][0077]) and the at least one metal layer is configured to supply current (fig. 12) to the p-doped side of the semiconductor layer sequence. Edmond does not teach the mirror to comprise a cover layer. In the same field of endeavor, Kim teaches an optoelectronic semiconductor chip comprising: a mirror comprises a cover layer (160) located closest to the semiconductor layer sequence, the cover layer is formed with a material transparent (implied in the reference, since light passes through it to reach the reflector 170) to the radiation and has an optical thickness between 0.5 L and 5 L inclusive (paragraph [0060]), the cover layer is followed by a total number of between inclusive 2 and inclusive 10 intermediate layers (any two to ten layers in 170) in a direction away from the semiconductor layer sequence, the intermediate layers have alternately high and low refractive indices (paragraph [0055]) for the radiation and are each made of a material transparent to the radiation (implied in the Bragg reflector, abstract), the intermediate layers are followed in the direction away from the semiconductor layer sequence by at least one metal layer as a reflection layer (190, paragraph [0064]), for the benefit of improving light extraction (abstract). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to include a mirror for the radiation on a rear side opposite a light extraction side, wherein the mirror comprised a cover layer located closest to the semiconductor layer sequence, the cover layer is formed with a material transparent to the radiation and has an optical thickness between 0.5 L and 5 L inclusive, the cover layer was followed by between inclusive 2 and inclusive 10 intermediate layers in a direction away from the semiconductor layer sequence, the intermediate layers have alternately high and low refractive indices for the radiation and are each made of a material transparent to the radiation, for the known benefit of increasing light extraction. According to the amendment in claim 1, Applicant seems to intend to limit the number of the intermediate layers. Because the preamble uses an open-ended word “comprising,” the body is presumed to contain elements not recited. Thus, the added limitation “a total number of” does not exclude the number of layers between the cover layer and the metal layer to two to ten; Especially the claim does not require the metal to contact the any of the intermediate layers. MPEP 2111.03: The transitional term "comprising", which is synonymous with "including," "containing," or "characterized by," is inclusive or open-ended and does not exclude additional, unrecited elements or method steps. See, e.g., Mars Inc. v. H.J. Heinz Co., 377 F.3d 1369, 1376, 71 USPQ2d 1837, 1843 (Fed. Cir. 2004) ("[L]ike the term ‘comprising,’ the terms ‘containing’ and ‘mixture’ are open-ended."). Invitrogen Corp. v. Biocrest Manufacturing, L.P., 327 F.3d 1364, 1368, 66 USPQ2d 1631, 1634 (Fed. Cir. 2003) ("The transition ‘comprising’ in a method claim indicates that the claim is open-ended and allows for additional steps."); Genentech, Inc. v. Chiron Corp., 112 F.3d 495, 501, 42 USPQ2d 1608, 1613 (Fed. Cir. 1997) ("Comprising" is a term of art used in claim language which means that the named elements are essential, but other elements may be added and still form a construct within the scope of the claim.); Moleculon Research Corp. v. CBS, Inc., 793 F.2d 1261, 229 USPQ 805 (Fed. Cir. 1986); In re Baxter, 656 F.2d 679, 686, 210 USPQ 795, 803 (CCPA 1981); Ex parte Davis, 80 USPQ 448, 450 (Bd. App. 1948) ("comprising" leaves "the claim open for the inclusion of unspecified ingredients even in major amounts"). In Gillette Co. v. Energizer Holdings Inc., 405 F.3d 1367, 1371-73, 74 USPQ2d 1586, 1589-91 (Fed. Cir. 2005). Furthermore, it would have been obvious to the skilled in the art before the effective filing date of the invention to adjust the total number of reflective layers (DBR in the cited art or “intermediate layers” claimed) according to the intended use of the device to balance the cost and the reflectivity of the reflector. On one hand, as mentioned by Applicant, increasing the number of layers in the DBR enhances the reflectivity of the DBR. On the other hand, the higher the layer number the greater the manufacturing cost and time to make them (paragraph [0023] of Avramescu and column 3, lines 40-44 of Kawase). “[W]here the general conditions of a claim are disclosed in the prior art, it is not inventive to discover the optimum or workable ranges by routine experimentation.” In re Aller, 220 F.2d 454, 456, 105 USPQ 233, 235 (CCPA 1955). Regarding claim 6, Kim teaches the optoelectronic semiconductor chip according to claim 1, wherein the cover layer has an optical thickness between 1.1 L and 1.6 L, inclusive. Claim(s) 1 and 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Edmond et al (PG Pub 2009/0166659 A1), Choi et al (PG Pub 2011/0260188 A1), Kim et al (WO 2017/069372 A1), and Sasaki (PG Pub 2015/0357525 A1). Regarding claim 1, Edmond teaches an optoelectronic semiconductor chip comprising: a semiconductor layer sequence (26,22,27, fig. 12) having an active zone (22, paragraph [0074]) for generating radiation with a wavelength of maximum intensity L (inherent), denoted as “L”, a mirror (reflectors 61 and/or 65, paragraphs [0075][0077]) for the radiation on a rear side opposite a light extraction side, the optoelectronic semiconductor chip is free of a growth substrate (fig. 12), the mirror is arranged on a p-doped (26, paragraph [0074]) side of the semiconductor layer sequence, least one electrode layer (metal 61 and/or 65, paragraphs [0075][0077]) and the at least one metal layer is configured to supply current (fig. 12) to the p-doped side of the semiconductor layer sequence. Edmond does not teach the mirror to comprise a cover layer. In the same field of endeavor, Choi teaches an optoelectronic semiconductor chip comprising: a mirror (120, paragraph [0044]) for the radiation on a rear side opposite a light extraction side (upper side of fig. 1), a total number of between 2 and inclusive 10 intermediate layers (six, figs. 1 and 2) in a direction away from the semiconductor layer sequence, the intermediate layers have alternately high and low refractive indices (paragraph [0051]) for the radiation and are each made of a material transparent to the radiation (implied in Bragg reflector), for the benefit of increasing light extraction efficiency (paragraph [0004]). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to include a mirror for the radiation on a rear side opposite a light extraction side, wherein the mirror comprised a cover layer located closest to the semiconductor layer sequence, the cover layer is formed with a material transparent to the radiation and has an optical thickness between 0.5 L and 5 L inclusive, the cover layer was followed by between inclusive 2 and inclusive 10 intermediate layers in a direction away from the semiconductor layer sequence, the intermediate layers have alternately high and low refractive indices for the radiation and are each made of a material transparent to the radiation, for the known benefit of increasing light extraction. Choi does not teach a cover layer. In the same field of endeavor, Kim teaches a cover layer (41) located closest to the semiconductor layer sequence, the cover layer is formed with a material transparent (implied in the reference, since light passes through it to reach the reflector) to the radiation and has an optical thickness between 0.5 L and 5 L inclusive (400 nm thick, paragraph [0070], for light with wavelength of 554 nm, paragraphs [0077]), for the benefit of preventing surface states at the mirror surface (paragraph [0070]). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to include a cover layer located closest to the semiconductor layer sequence, the cover layer was formed with a material transparent (implied in the reference, since light passes through it to reach the reflector) to the radiation and has an optical thickness between 0.5 L and 5 L inclusive, for the benefit of preventing surface states at the mirror surface Kim does not teach the intermediate layers are followed in the direction away from the semiconductor layer sequence by at least one metal layer as a reflection layer. In the same field of endeavor, Sasaki teaches the intermediate layers (107, fig. 12) are followed in the direction away from the semiconductor layer sequence (103) by at least one metal layer as a reflection layer (108, paragraph [0016]), for the benefit of increasing light extraction (paragraph [0016]). Thus, it would have been obvious to the skilled in the art before the effective filing date of the invention to include at least one metal layer as a reflection layer following the intermediate layers in the direction away from the semiconductor layer sequence for the benefit of increasing light extraction. Regarding claim 7, Choi teaches the optoelectronic semiconductor chip according to claim 1, wherein high refractive index layers each have an optical thickness between 0.3 L (Wλ/(4m) equals 0.3, when natural number m equals 1 and W equals 1.2, paragraphs [0049][0051]) and 0.4 L, inclusive and an intermediate low refractive index layer has an optical thickness between 0.26 L and 0.35 L (Wλ/(4m) equals 0.3, when natural number m equals 1 and W equals 1.2, paragraphs [0049][0051]), inclusive. Response to Arguments Applicant’s arguments with respect to claim(s) 1-15 have been considered but are moot because the new ground of rejection. See the rejection above. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FEIFEI YEUNG LOPEZ whose telephone number is (571)270-1882. The examiner can normally be reached M-F: 8am to 4pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571 270 7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FEIFEI YEUNG LOPEZ/Primary Examiner, Art Unit 2899
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Prosecution Timeline

Aug 10, 2023
Application Filed
Dec 08, 2025
Non-Final Rejection mailed — §103
Mar 06, 2026
Response Filed
Apr 09, 2026
Final Rejection mailed — §103
Jun 08, 2026
Response after Non-Final Action
Jun 16, 2026
Request for Continued Examination
Jun 22, 2026
Response after Non-Final Action
Jul 22, 2026
Non-Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
81%
Grant Probability
79%
With Interview (-2.7%)
2y 5m (~0m remaining)
Median Time to Grant
High
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