DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of the Application
Claims 1-20 remain pending in this application. Acknowledgement is made of the amendment received 09/08/2026. Claims 1-5 and 16-20 are amended. Finality of the previous office action dated 07/10/2026 is withdrawn.
Claim Objections
Claim16 and 20 are objected to because of the following informalities:
Regarding claim 16, the claim recites “the DTI”, it appears it should read “the first DTI”, or another appropriate correction.
Regarding claim 20, the claim recites “the DTI”, it appears it should read “the first DTI”, or another appropriate correction.
Claim Rejections - 35 USC § 112
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim 17 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claim 17, it recites the limitation "The second DTI" in line 2. There is insufficient antecedent basis for this limitation in the claim. The examiner interprets the claim to have intended to state “a second DTI”, in which case proper antecedent basis is established. The claim will be examined on the basis of this interpretation hereafter. Appropriate correction is required.
Double Patenting
The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg, 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman, 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi, 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum, 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel, 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington, 418 F.2d 528, 163 USPQ 644 (CCPA 1969).
A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA . A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b).
The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13.
The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA /25, or PTO/AIA /26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer.
Claims 1-20 are rejected on the ground of nonstatutory double patenting as being unpatentable over claims 9-11 and 20 of U.S. Patent No. 11,973,083 (Wu et al, US 11973083 B2, hereafter Wu). Although the claims at issue are not identical, they are not patentably distinct from each other because the examined claims recite the same subject matter with the limitation “the transistor comprises doping the semiconductor material to define a plurality of doped regions“ omitted.
Regarding claim 1, Wu, in claim 20, which depends on claims 16 and 17, of the above cited patent, discloses:
A method of making a semiconductor device, the method comprising (Wu claim 16):
manufacturing a bias layer over a buried oxide layer (Wu claim 16);
growing a layer of semiconductor material over the bias layer (Wu claim 16);
forming a transistor in the layer of semiconductor material (Wu claim 16), wherein the bias layer is between the transistor and a substrate (Wu claim 16);
forming a first deep trench isolation structure (DTI) extending through the layer of semiconductor material and contacting the substrate (Wu claim 16);
forming a contact extending through the DTI to contact the substrate, wherein the contact is separated from the bias layer (Wu claim 16); and
manufacturing a second bias layer over the buried oxide layer, wherein the second bias layer is between the bias layer and the DTI (Wu claim 20, “the second bias layer is between the bias layer and the contact”, which is an obvious variation to a person of ordinary skill in the art, in that the second bias layer as claimed by Wu and the Applicant occupies the same position relative to the DTI through which the contact extends and the bias layer, and therefore is not patentably distinct).
Regarding claims 2-5, the claims are rejected for being dependent on claim 1.
Regarding claim 6, Wu, in claim 9, which depends on claims 6 and 8, of the above cited patent, discloses:
A method of making a semiconductor device, the method comprising (Wu claim 6):
manufacturing a bias layer over a buried oxide layer (Wu claim 6);
growing a layer of semiconductor material over the bias layer (Wu claim 6);
forming a transistor in the layer of semiconductor material, wherein the bias layer is between the transistor and a substrate (Wu claim 6);
forming a first deep trench isolation structure (DTI) extending through the layer of semiconductor material and contacting the substrate (Wu claim 6);
forming a first bias contact extending through the layer of semiconductor material and electrically connecting to the bias layer (Wu claim 6);
manufacturing a second bias layer over the buried oxide layer, wherein the second bias layer is spaced from the bias layer in a direction parallel to a top surface of the substrate (Wu claim 8); and
forming a second bias contact extending through the layer of semiconductor material and electrically connecting to the second bias layer (Wu claim 9).
Regarding claims 7-15, the claims are rejected for being dependent on claim 6.
Regarding claim 16, Wu, in claim 20, which depends on claims 16 and 17, of the above cited patent, discloses:
A method of making a semiconductor device, the method comprising (Wu claim 16):
manufacturing a bias layer over a buried oxide layer (Wu claim 16);
growing a layer of semiconductor material over the bias layer (Wu claim 16);
forming a transistor in the layer of semiconductor material, wherein the bias layer is between the transistor and a substrate (Wu claim 16);
forming a first deep trench isolation structure (DTI) extending through the layer of semiconductor material and contacting the substrate (Wu claim 16);
forming a contact extending through the DTI to contact the substrate, wherein the contact is separated from the bias layer (Wu claim 16);
forming a bias contact extending through the layer of semiconductor material and electrically connecting to the bias layer (Wu claim 17); and
manufacturing a second bias layer over the buried oxide layer, wherein the second bias layer is between the bias layer and the contact (Wu claim 20).
Regarding claims 17-20, the claims are rejected for being dependent on claim 16.
Response to Arguments
Applicant’s arguments filed 09/08/2026, with respect to claims 1 and 16-19 have been fully considered and are persuasive. The 35 USC § 103 rejections of claims 1 and 16-19 have been withdrawn.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to NICHOLAS B. MICHAUD whose telephone number is (703)756-1796. The examiner can normally be reached Monday-Friday, 0800-1700 Eastern Time.
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/NICHOLAS B. MICHAUD/
EXAMINER
Art Unit 2818
/BRIAN TURNER/Primary Examiner, Art Unit 2818
