DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claims 1-13 and 15-30 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claims 1 and 20 are objected to because of the following informalities: the limitation “wherein the first source is different from the first source” has typographical error and it should be change to “wherein the first source is different from the second source”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-7, 12-13, 16, 18, 20-26 and 30 are rejected under 35 U.S.C. 103 as being unpatentable over Shibata (US Patent No. 10,601,572 B2) in view of NAGAHARA et al. (US 2008/0152916 A1).
In considering claim 1, Shibata discloses all the claimed subject matter, note 1) the claimed an image-signal processor (ISP) configured to process first image data of a data stream and to process second image data of the data stream is met by the data processing device 5 (Figs. 1-2, col. 3, line 16 to col. 5, line 24), and 2) the claimed a reset controller configured to, in response to a detected error related to the first image data, reset the first image data in a memory of the ISP while maintaining the second image data in the memory of the ISP is met by the error detecting unit 15 which determines the count value of the counter C1 and if the synchronization pulse is not detected in the synchronization signal until the count value reaches an uppermost value of the range corresponding to the predetermined fluctuation range, resets the counter C1 and discards the image data written into the line memory LM1 or LM2 in this pulse period (Figs. 1-2, col. 3, line 16 to col. 5, line 56).
However, Shibata explicitly does not disclose the newly added claimed wherein the first image data is from a first source, wherein the second image data is from a second source, wherein the first source is different from the first source.
NAGAHARA et al. teach that a recorder server 130 records video signals from plurality of cameras 110, 120, … and a recording server 130 (Fig. 1, page 3, paragraph #0036- #0037 and #0043).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the teaching of recording of plurality video signals from plurality of different sources into Shibata’s system in order to take advantage of reducing time in the editing job.
In considering claim 2, the claimed wherein the ISP is configured to: receive the first image data of the data stream; store the first image data at a first location in a memory of the ISP; process the first image data from the first location in the memory of the ISP; receive the second image data of the data stream; store the second image data at a second location in the memory of the ISP; and process the second image data from the second location in the memory of the ISP is met by the data processing device 5 which processes the image data and stores into the line memory LM1 and LM2 (Figs. 1-2, col. 3, line 16 to col. 5, line 56 of Shibata).
In considering claim 3, the claimed wherein the reset controller is configured to reset the first image data at the first location in the memory of the ISP while maintaining the second image data at the second location in the memory of the ISP is met by the error detecting unit 15 which determines the count value of the counter C1 and if the synchronization pulse is not detected in the synchronization signal until the count value reaches an uppermost value of the range corresponding to the predetermined fluctuation range, resets the counter C1 and discards the image data written into the line memory LM1 or LM2 in this pulse period (Figs. 1-2, col. 3, line 16 to col. 5, line 56 of Shibata).
In considering claim 4, the claimed wherein the ISP is configured to process the second image data stored at the second location in the memory of the ISP subsequent to the reset controller resetting the first image data in the memory of the ISP is met by resetting the counter C1 and discards the image data written into the line memory LM1 or LM2 in this pulse period if the error of the image is detected (Figs. 1-2, col. 3, line 16 to col. 5, line 56 of Shibata).
In considering claim 5, the claimed wherein, to reset the first image data in the memory of the ISP, the reset controller is configured to reset an offset corresponding to the first location is met by if the error detection signal is not asserted, then the data reception processing unit 12 and the line data reading unit 13 perform writing/reading the line data (i.e. the image data of a line) with changing the selection of the line memory LM1 or LM2 (Figs. 2-4, col. 5, line 27 to col. 7, line 38 of Shibata).
In considering claim 6, the claimed wherein the ISP is configured to process the second image data subsequent to the reset controller resetting the first image data in the memory of the ISP is met by if the error detection signal is not asserted, then the data reception processing unit 12 and the line data reading unit 13 perform writing/reading the line data (i.e. the image data of a line) with changing the selection of the line memory LM1 or LM2 (Figs. 2-4, col. 5, line 27 to col. 7, line 38 of Shibata).
In considering claim 7, the claimed wherein: to reset the first image data in the memory of the ISP, the reset controller is configured to reset the first image data at a first location in the memory of the ISP; and after the reset controller resets the first image data at the first location in the memory of the ISP, the ISP is configured to write third image data at the first location is met by if the error detection signal is not asserted, then the data reception processing unit 12 and the line data reading unit 13 perform writing/reading the line data (i.e. the image data of a line) with changing the selection of the line memory LM1 or LM2 (Figs. 2-4, col. 5, line 27 to col. 7, line 38 of Shibata).
In considering claim 12, the claimed wherein the ISP comprises an error detector configured to detect errors based on delays in processing image data is met by the error detecting unit 15 (Figs. 1-2, col. 3, line 16 to col. 5, line 56 of Shibata).
In considering claim 13, the claimed wherein the reset controller is configured to, responsive to a detected error related to the second image data, reset the second image data in memory of the ISP while maintaining the first image data in the memory of the ISP is met by the error detecting unit 15 which resets the counter C1 and discards the image data written into the line memory LM1 or LM2 in this pulse period if the error detected (Figs. 1-2, col. 3, line 16 to col. 5, line 56 of Shibata).
In considering claim 16, the claimed wherein: the apparatus further comprises a first camera decoder configured to generate the first image data based on first raw image data; and the reset controller is configured to, responsive to a detected error related to the first image data, reset the first image data at the first camera decoder is met by the error detecting unit 15 which determines the count value of the counter C1 and if the synchronization pulse is not detected in the synchronization signal until the count value reaches an uppermost value of the range corresponding to the predetermined fluctuation range, resets the counter C1 and discards the image data written into the line memory LM1 or LM2 in this pulse period (Figs. 1-2, col. 3, line 16 to col. 5, line 56 of Shibata).
In considering claim 18, the claimed wherein the reset controller is configured to, responsive to a reset command, at least one of: reset the first image data in memory of the ISP while maintaining the second image data in the memory of the ISP; reset the second image data in memory of the ISP while maintaining the first image data in the memory of the ISP; or reset the first image data and the second image data in the ISP is met by the error detecting unit 15 which determines the count value of the counter C1 and if the synchronization pulse is not detected in the synchronization signal until the count value reaches an uppermost value of the range corresponding to the predetermined fluctuation range, resets the counter C1 and discards the image data written into the line memory LM1 or LM2 in this pulse period (Figs. 1-2, col. 3, line 16 to col. 5, line 56 of Shibata).
Claims 20-24 are rejected for the same reason as discussed in claims 1-5, respectively.
Claim 25 is rejected for the same reason as discussed in claim 7.
Claim 26 is rejected for the same reason as discussed in claim 1.
In considering claim 30, the claimed further comprising: receiving raw image data; generating the first image data based on the raw image data; and detecting errors based on the raw image data is met by the data processing device 5 (Figs. 1-2, col. 2, line 37 to col. 4, line 67 of Shibata).
6. Claims 8-11 and 27-29 are rejected under 35 U.S.C. 103 as being unpatentable over Shibata (US Patent No. 10,601,572 B2) in view of NAGAHARA et al. (US 2008/0152916 A1) and further in view of OH et al. (US 2025/0117656 A1).
In considering claim 8, the combination of Shibata and NAGAHARA et al. disclose all the claimed limitations as discussed in claim 1 above, except for providing the claimed wherein the ISP comprises one or more ISP intellectual property (IP) blocks. OH et al. teach that the electronic system 10 may include various kinds of IP blocks. For example, the IP blocks may include a processing circuitry, a plurality of cores included in the processing circuitry, a multi-format codec (MFC), a video module (for example, a camera interface, a joint photographic experts group (JPEG) processor, a video processor, a mixer, or the like)…(Fig. 1, page 2, paragraph #0029 to paragraph #0031). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to incorporate the IP blocks as taught by OH et al. into the combination of Shibata and NAGAHARA et al.’s system in order to generate and process an information signal on the basis of a performing result and/or may retrain the neural network.
In considering claim 9, the claimed wherein, to reset the first image data in memory of the ISP, the reset controller is configured to reset the first image data stored by each of the one or more ISP IP blocks is met by the error detecting unit 15 which determines the count value of the counter C1 and if the synchronization pulse is not detected in the synchronization signal until the count value reaches an uppermost value of the range corresponding to the predetermined fluctuation range, resets the counter C1 and discards the image data written into the line memory LM1 or LM2 in this pulse period (Figs. 1-2, col. 3, line 16 to col. 5, line 56 of Shibata).
In considering claim 10, the claimed wherein the ISP comprises one or more error detectors and wherein each of the one or more error detectors is coupled to a corresponding one of the one or more ISP IP blocks is met by the error detecting unit 15 (Figs. 1-2, col. 3, line 16 to col. 5, line 56 of Shibata).
In considering claim 11, the claimed wherein each of the one or more error detectors is configured to detect a respective error based on a respective delay in processing image data at a respective one of the one or more ISP IP blocks is met by the error detecting unit 15 which resets the counter C1 and discards the image data written into the line memory LM1 or LM2 in this pulse period (Figs. 1-2, col. 3, line 16 to col. 5, line 56 of Shibata).
Claim 27 is rejected for the same reason as discussed in claim 9.
Claim 28 is rejected for the same reason as discussed in claim 9.
Claim 29 is rejected for the same reason as discussed in claim 11.
Allowable Subject Matter
7. Claim 15 is allowed.
8. Claims 17 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
9. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
10. Any inquiry concerning this communication or earlier communications from the examiner should be directed to TRANG U TRAN whose telephone number is (571)272-7358. The examiner can normally be reached M-F 10:00AM- 6:00PM.
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October 2, 2025
/TRANG U TRAN/Primary Examiner, Art Unit 2422