DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1, 8 and 15.
Pending: 1-20.
Response to Arguments
Applicant' s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Specification
The disclosure is objected to because of the following informalities:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: INTEGRATED CIRCUIT WITH GATE-ALL- AROUND AND OXIDE SEMICONDUCTOR CHANNELS.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4-17 and 19 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Gardner et al., US PG pub. 20210104522 A1.
Re: Independent Claim 1, Gardner discloses a semiconductor layer (110/112 and 114/116, fig. 2A-fig. 2B) substantially free of oxygen;
an oxide semiconductor layer (204 and 212, fig. 2A-fig. 2B) over and spaced apart from the semiconductor layer (110/112 and 114/116, fig. 2A-fig. 2B); and
a gate structure (118/120 and 122/124, fig. 2A-fig. 2B) wrapping around a channel region (110/112 region and 114/116 region, fig. 2A-fig. 2B) of the semiconductor layer (110/112 and 114/116, fig. 2A-fig. 2B) and a channel region (110/112 region and 114/116 region, fig. 2A-fig. 2B) of the oxide semiconductor layer (204 and 212, fig. 2A-fig. 2B), wherein the channel region (110/112 region and 114/116 region, fig. 2A-fig. 2B) of the semiconductor layer (110/112 and 114/116, fig. 2A-fig. 2B) substantially free of oxygen is a p-type channel for a p-type transistor (102B, fig. 2B).
Re: Claim 4, Gardner disclose(s) all the limitations of claim 1 on which this claim depends. Gardner further discloses: an isolation layer (152, fig. 1C) spacing a source/drain region (126 and 128, 130-138, fig. 1C) of the semiconductor layer (110/112 and 114/116, fig. 2A-fig. 2B) from a source/drain region (126 and 128, 130-138, fig. 1C) of the oxide semiconductor layer (204 and 212, fig. 2A-fig. 2B).
Re: Claim 5, Gardner disclose(s) all the limitations of claim 1 on which this claim depends. Gardner further discloses: a doped semiconductor layer (130-138 126 and 128, fig. 2A-fig. 2B) over and in contact with a source/drain region (126 and 128, 130-138, fig. 1C) of the semiconductor layer (110/112 and 114/116, fig. 2A-fig. 2B), wherein the doped semiconductor layer (130-138 126 and 128, fig. 2A-fig. 2B) comprises a semiconductor composition different from the semiconductor layer (110/112 and 114/116, fig. 2A-fig. 2B).
Re: Claim 6, Gardner disclose(s) all the limitations of claim 5 on which this claim depends. Gardner further discloses: an isolation layer (152, fig. 1C) spacing the doped semiconductor layer (130-138 126 and 128, fig. 2A-fig. 2B) from a source/drain region (126 and 128, 130-138, fig. 1C) of the oxide semiconductor layer (204 and 212, fig. 2A-fig. 2B).
Re: Claim 7, Gardner disclose(s) all the limitations of claim 1 on which this claim depends. Gardner further discloses: wherein the gate structure (118/120 and 122/124, fig. 2A-fig. 2B) comprises an interfacial layer (152, fig. 2A) in contact with the channel region (110/112 region and 114/116 region, fig. 2A-fig. 2B) of the semiconductor layer (110/112 and 114/116, fig. 2A-fig. 2B), a high-k dielectric layer (204, fig. 2A) over the interfacial layer (152, fig. 2A) and in contact with the channel region (110/112 region and 114/116 region, fig. 2A-fig. 2B) of the oxide semiconductor layer (204 and 212, fig. 2A-fig. 2B), and a gate metal layer (208, fig. 2a/2b) over the high-k dielectric layer (204, fig. 2A).
Re: Independent Claim 8, Gardner discloses a p-type transistor (102B, fig. 2B), wherein the p-type transistor (102B, fig. 2B) comprises at least one group-IV semiconductor layer (110/112 and 114/116, fig. 2A-fig. 2B) and a first gate structure (118/120 and 122/124, fig. 2A-fig. 2B) wrapping around the at least one group-IV semiconductor layer (110/112 and 114/116, fig. 2A-fig. 2B);
an isolation layer (152, fig. 1C) over the p-type transistor (102B, fig. 2B); and
a n-type transistor (102A, fig. 2B) vertically stacked over the p-type transistor (102B, fig. 2B) and over the isolation layer (152, fig. 1C), wherein the n-type transistor (102A, fig. 2B) comprises at least one oxide semiconductor layer (204 and 212, fig. 2A-fig. 2B) and a second gate structure (118/120 and 122/124, fig. 2A-fig. 2B) wrapping around the at least one oxide semiconductor layer (204 and 212, fig. 2A-fig. 2B), wherein the isolation layer (152, fig. 1C) has two separated portions separated by the second gate structure (118/120 and 122/124, fig. 2A-fig. 2B) of the n-type transistor (102A, fig. 2B).
Re: Claim 9, Gardner disclose(s) all the limitations of claim 8 on which this claim depends. Gardner further discloses: wherein the oxide semiconductor layer (204 and 212, fig. 2A-fig. 2B) of the n-type transistor (102A, fig. 2B) is in contact with the isolation layer (152, fig. 1C).
Re: Claim 10, Gardner disclose(s) all the limitations of claim 8 on which this claim depends. Gardner further discloses: wherein the first gate structure (118/120 and 122/124, fig. 2A-fig. 2B) is continuously connected with the second gate structure (118/120 and 122/124, fig. 2A-fig. 2B).
Re: Claim 11, Gardner disclose(s) all the limitations of claim 8 on which this claim depends. Gardner further discloses: a doped semiconductor layer (130-138 126 and 128, fig. 2A-fig. 2B) spacing the group-IV semiconductor layer (110/112 and 114/116, fig. 2A-fig. 2B) of the p-type transistor (102B, fig. 2B) from the isolation layer (152, fig. 1C).
Re: Claim 12, Gardner disclose(s) all the limitations of claim 8 on which this claim depends. Gardner further discloses: a metal layer (208, fig. 2a/2b) between the oxide semiconductor layer (204 and 212, fig. 2A-fig. 2B) of the n-type transistor (102A, fig. 2B) and the isolation layer (152, fig. 1C).
Re: Claim 13, Gardner disclose(s) all the limitations of claim 8 on which this claim depends. Gardner further discloses: wherein the first gate structure (118/120 and 122/124, fig. 2A-fig. 2B) wraps around a plurality of the group-IV semiconductor layer (110/112 and 114/116, fig. 2A-fig. 2B)s, and the group-IV semiconductor layer (110/112 and 114/116, fig. 2A-fig. 2B)s are vertically arranged and spaced apart from each other.
Re: Claim 14, Gardner disclose(s) all the limitations of claim 8 on which this claim depends. Gardner further discloses: wherein the second gate structure (118/120 and 122/124, fig. 2A-fig. 2B) wraps around a plurality of the oxide semiconductor layer (204 and 212, fig. 2A-fig. 2B)s, and the oxide semiconductor layer (204 and 212, fig. 2A-fig. 2B)s are vertically arranged and spaced apart from each other.
Re: Independent Claim 15, Gardner discloses depositing an epitaxial stack (300, fig. 3) over a substrate (302, fig. 3), wherein the epitaxial stack (300, fig. 3) comprises a semiconductor layer (110/112 and 114/116, fig. 2A-fig. 2B) and a sacrificial layer (304a, fig. 3; ¶0053) over the semiconductor layer (110/112 and 114/116, fig. 2A-fig. 2B), wherein the sacrificial layer (304a, fig. 3; ¶0053) comprises a semiconductor composition different from the semiconductor layer (110/112 and 114/116, fig. 2A-fig. 2B);
depositing an isolation layer (152, fig. 1C) over the epitaxial stack (300, fig. 3);
after depositing the isolation layer (152, fig. 1C) over the epitaxial stack (300, fig. 3), depositing an oxide semiconductor layer (204 and 212, fig. 2A-fig. 2B) over the isolation layer (152, fig. 1C); and
replacing a portion of the sacrificial layer (304a, fig. 3; ¶0053) and a portion of the isolation layer (152, fig. 1C) with a gate structure (118/120 and 122/124, fig. 2A-fig. 2B).
Re: Claim 16, Gardner disclose(s) all the limitations of claim 15 on which this claim depends. Gardner further discloses: wherein replacing the portion of the sacrificial layer (304a, fig. 3; ¶0053) and the portion of the isolation layer (152, fig. 1C) with the gate structure (118/120 and 122/124, fig. 2A-fig. 2B) comprises:
selectively etching (¶0053-¶0054) a portion of the sacrificial layer (304a, fig. 3; ¶0053) and a portion of the isolation layer (152, fig. 1C), while leaving a channel region (110/112 region and 114/116 region, fig. 2A-fig. 2B) of the semiconductor layer (110/112 and 114/116, fig. 2A-fig. 2B) and a channel region (110/112 region and 114/116 region, fig. 2A-fig. 2B) of the oxide semiconductor layer (204 and 212, fig. 2A-fig. 2B) exposed; and
forming the gate structure (118/120 and 122/124, fig. 2A-fig. 2B) around the exposed channel region (110/112 region and 114/116 region, fig. 2A-fig. 2B) of the semiconductor layer (110/112 and 114/116, fig. 2A-fig. 2B) and the exposed channel region (110/112 region and 114/116 region, fig. 2A-fig. 2B) of the oxide semiconductor layer (204 and 212, fig. 2A-fig. 2B).
Re: Claim 17, Gardner disclose(s) all the limitations of claim 16 on which this claim depends. Gardner further discloses: wherein selectively etching (¶0053-¶0054) the portion of the sacrificial layer (304a, fig. 3; ¶0053) and the portion of the isolation layer (152, fig. 1C) is performed using the same etch recipe.
Re: Claim 19, Gardner disclose(s) all the limitations of claim 15 on which this claim depends. Gardner further discloses: wherein depositing the oxide semiconductor layer (204 and 212, fig. 2A-fig. 2B) over the isolation layer (152, fig. 1C) is performed such that the oxide semiconductor layer (204 and 212, fig. 2A-fig. 2B) is in contact with the isolation layer (152, fig. 1C).
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2, 3 and 20 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Gardner et al., US PG pub. 20210104522 A1; in view of Mishra et al., US PG pub. 20210398977 A1.
Re: Claim 2, Gardner discloses all the limitations of claim 1 on which this claim depends. Gardner further discloses: wherein the semiconductor layer (110/112 and 114/116, fig. 2A-fig. 2B) is GeSn.
Gardner is silent regarding: the oxide semiconductor layer (204 and 212, fig. 2A-fig. 2B) is InGaZnO.
Mishra discloses oxide semiconductor layer is InGaZnO (115B, fig. 3A; ¶0045).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include a material such as InGaZnO since this material can improve high electron mobility.
Re: Claim 3, Gardner discloses all the limitations of claim 1 on which this claim depends. Gardner is silent regarding: wherein the oxide semiconductor layer (204 and 212, fig. 2A-fig. 2B) is amorphous.
Mishra discloses oxide semiconductor layer can be amorphous (¶0042).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include an amorphous material since amorphous material can improve by having extremely low leakage current, reduces power consumption and High Electron Mobility.
Re: Claim 20, Gardner discloses all the limitations of claim 1 on which this claim depends. Gardner is silent regarding: wherein depositing the oxide semiconductor layer (204 and 212, fig. 2A-fig. 2B) is performed such that the oxide semiconductor layer (204 and 212, fig. 2A-fig. 2B) is amorphous.
Mishra discloses oxide semiconductor layer can be amorphous (¶0042).
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include an amorphous material since amorphous material can improve by having extremely low leakage current, reduces power consumption and High Electron Mobility.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TSZ CHIU whose telephone number is 571-272-8656. The examiner can normally be reached on M-F, 9:00AM to 5:00PM (EST).
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898
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