DETAILED ACTION
General Remarks
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
When responding to this office action, applicants are advised to provide the examiner with line numbers and page numbers in the application and/or references cited to assist the examiner in locating appropriate paragraphs.
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
For Examiner’s Interview fill out the online Automated Interview Request (AIR) form (http://www.uspto.gov/patent/uspto-automated-interview-request-air-form.html).
Status of claim(s) to be treated in this office action:
Independent: 1, 8 and 15.
Pending: 1-20.
Specification
The disclosure is objected to because of the following informalities:
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: INTEGRATED CIRCUIT WITH GATE-ALL-AROUND AND OXIDE SEMICONDUCTOR CHANNELS.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 3-7, and 15-20 is/are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Mishra et al., US PG pub. 20210398977 A1.
Re: Independent Claim 1, Mishra discloses a semiconductor layer (315A, fig. 3A; ¶0051; Group IV semiconductor material in Group IV material does not include oxygen) substantially free of oxygen;
an oxide semiconductor layer (115B, fig. 3A; ¶0045 for example semiconductor metal oxides such as IGZO) over and spaced apart from the semiconductor layer (315A, fig. 3A; ¶0051; Group IV semiconductor material in Group IV material does not include oxygen); and
a gate structure (110 and 217, fig. 3A) wrapping around a channel region (LC region below gate structure 110 and 217, fig. 3A) of the semiconductor layer (315A, fig. 3A; ¶0051; Group IV semiconductor material in Group IV material does not include oxygen) and a channel region (LC region below gate structure 110 and 217, fig. 3A) of the oxide semiconductor layer (115B, fig. 3A; ¶0045 for example semiconductor metal oxides such as IGZO).
Re: Claim 3, Mishra disclose(s) all the limitations of claim 1 on which this claim depends. Mishra further discloses: wherein the oxide semiconductor layer (115B, fig. 3A; ¶0045 for example semiconductor metal oxides such as IGZO) is amorphous (¶0042; polycrystalline or amorphous embodiments may instead include semiconducting metal oxides).
Re: Claim 4, Mishra disclose(s) all the limitations of claim 1 on which this claim depends. Mishra further discloses: an isolation layer (111, fig. 3A) spacing a source/drain region (region 105, fig. 3A) of the semiconductor layer (315A, fig. 3A; ¶0051; Group IV semiconductor material in Group IV material does not include oxygen) from a source/drain region (region 105, fig. 3A) of the oxide semiconductor layer (115B, fig. 3A; ¶0045 for example semiconductor metal oxides such as IGZO).
Re: Claim 5, Mishra disclose(s) all the limitations of claim 1 on which this claim depends. Mishra further discloses: a doped semiconductor layer (315A, fig. 3A; ¶0051; Group IV semiconductor material in Group IV material does not include oxygen) over and in contact with a source/drain region (region 105, fig. 3A) of the semiconductor layer (315A, fig. 3A; ¶0051; Group IV semiconductor material in Group IV material does not include oxygen), wherein the doped semiconductor layer (315A, fig. 3A; ¶0051; Group IV semiconductor material in Group IV material does not include oxygen) comprises a semiconductor composition different from the semiconductor layer (315A, fig. 3A; ¶0051; Group IV semiconductor material in Group IV material does not include oxygen).
Re: Claim 6, Mishra disclose(s) all the limitations of claim 5 on which this claim depends. Mishra further discloses: an isolation layer (111, fig. 3A) spacing the doped semiconductor layer (315A, fig. 3A; ¶0051; Group IV semiconductor material in Group IV material does not include oxygen) from a source/drain region (region 105, fig. 3A) of the oxide semiconductor layer (115B, fig. 3A; ¶0045 for example semiconductor metal oxides such as IGZO).
Re: Claim 7, Mishra disclose(s) all the limitations of claim 1 on which this claim depends. Mishra further discloses: wherein the gate structure (110 and 217, fig. 3A) comprises an interfacial layer (115C, fig. 3A) in contact with the channel region (LC region below gate structure 110 and 217, fig. 3A) of the semiconductor layer (315A, fig. 3A; ¶0051; Group IV semiconductor material in Group IV material does not include oxygen), a high-k dielectric layer (217, fig. 3A; ¶0047) over the interfacial layer (115C, fig. 3A) and in contact with the channel region (LC region below gate structure 110 and 217, fig. 3A) of the oxide semiconductor layer (115B, fig. 3A; ¶0045 for example semiconductor metal oxides such as IGZO), and a gate metal layer over the high-k dielectric layer (217, fig. 3A; ¶0047).
Re: Independent Claim 15, Mishra discloses depositing an epitaxial stack (¶0034-¶0035) over a substrate, wherein the epitaxial stack (¶0034-¶0035) comprises a semiconductor layer (315A, fig. 3A; ¶0051; Group IV semiconductor material in Group IV material does not include oxygen) and a sacrificial layer (630, fig. 6) over the semiconductor layer (315A, fig. 3A; ¶0051; Group IV semiconductor material in Group IV material does not include oxygen), wherein the sacrificial layer (630, fig. 6) comprises a semiconductor composition different from the semiconductor layer (315A, fig. 3A; ¶0051; Group IV semiconductor material in Group IV material does not include oxygen);
depositing an isolation layer (111, fig. 3A) over the epitaxial stack (¶0034-¶0035);
depositing an oxide semiconductor layer (115B, fig. 3A; ¶0045 for example semiconductor metal oxides such as IGZO) over the isolation layer (111, fig. 3A); and
replacing a portion of the sacrificial layer (630, fig. 6) and a portion of the isolation layer (111, fig. 3A) with a gate structure (110 and 217, fig. 3A).
Re: Claim 16, Mishra disclose(s) all the limitations of claim 15 on which this claim depends. Mishra further discloses: wherein replacing the portion of the sacrificial layer (630, fig. 6) and the portion of the isolation layer (111, fig. 3A) with the gate structure (110 and 217, fig. 3A) comprises:
selectively etching (¶0066) a portion of the sacrificial layer (630, fig. 6) and a portion of the isolation layer (111, fig. 3A), while leaving a channel region (LC region below gate structure 110 and 217, fig. 3A) of the semiconductor layer (315A, fig. 3A; ¶0051; Group IV semiconductor material in Group IV material does not include oxygen) and a channel region (LC region below gate structure 110 and 217, fig. 3A) of the oxide semiconductor layer (115B, fig. 3A; ¶0045 for example semiconductor metal oxides such as IGZO) exposed; and
forming the gate structure (110 and 217, fig. 3A) around the exposed channel region (LC region below gate structure 110 and 217, fig. 3A) of the semiconductor layer (315A, fig. 3A; ¶0051; Group IV semiconductor material in Group IV material does not include oxygen) and the exposed channel region (LC region below gate structure 110 and 217, fig. 3A) of the oxide semiconductor layer (115B, fig. 3A; ¶0045 for example semiconductor metal oxides such as IGZO).
Re: Claim 17, Mishra disclose(s) all the limitations of claim 16 on which this claim depends. Mishra further discloses: wherein selectively etching (¶0066) the portion of the sacrificial layer (630, fig. 6) and the portion of the isolation layer (111, fig. 3A) is performed using the same etch recipe.
Re: Claim 18, Mishra disclose(s) all the limitations of claim 16 on which this claim depends. Mishra further discloses: wherein selectively etching (¶0066) the portion of the sacrificial layer (630, fig. 6) and the portion of the isolation layer (111, fig. 3A) is performed using a plasma (¶0064) without substrate bias.
Re: Claim 19, Mishra disclose(s) all the limitations of claim 15 on which this claim depends. Mishra further discloses: wherein depositing the oxide semiconductor layer (115B, fig. 3A; ¶0045 for example semiconductor metal oxides such as IGZO) over the isolation layer (111, fig. 3A) is performed such that the oxide semiconductor layer (115B, fig. 3A; ¶0045 for example semiconductor metal oxides such as IGZO) is in contact with the isolation layer (111, fig. 3A).
Re: Claim 20, Mishra disclose(s) all the limitations of claim 15 on which this claim depends. Mishra further discloses: wherein depositing the oxide semiconductor layer (115B, fig. 3A; ¶0045 for example semiconductor metal oxides such as IGZO) is performed such that the oxide semiconductor layer (115B, fig. 3A; ¶0045 for example semiconductor metal oxides such as IGZO) is amorphous.
Claim Rejections - 35 USC § 103
The following is a quotation of AIA 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Mishra et al., US PG pub. 20210398977 A1; in view of Zhang et al., US PG pub. 20150200288 A1.
Re: Claim 2, Mishra discloses all the limitations of claim 1 on which this claim depends. Mishra further discloses: wherein the semiconductor layer (315A, fig. 3A; ¶0051; Group IV semiconductor material in Group IV material does not include oxygen), and the oxide semiconductor layer (115B, fig. 3A; ¶0045 for example semiconductor metal oxides such as IGZO) is InGaZnO.
Mishra is silent regarding: the semiconductor layer is GeSn.
Zhang discloses a transistor the channel layer that is made of Group IV semiconductor material GeSn can be one of those material for Group IV semiconductor material.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include material such as GeSn as the channel region for Group IV semiconductor material since this can improving an operation of the FET device (¶0096).
Claim(s) 8-14 is/are rejected under AIA 35 U.S.C. 103 as being unpatentable over Mishra et al., US PG pub. 20210398977 A1; in view of Sharma et al., US PG pub. 20240006540 A1.
Re: Independent Claim 8, Mishra discloses a p-type transistor (301, fig. 3A), wherein the p-type transistor (301, fig. 3A) comprises at least one group-IV semiconductor layer (315A, fig. 3A; ¶0051; Group IV semiconductor material in Group IV material does not include oxygen) and a first gate structure (110 and 217, fig. 3A) wrapping around the at least one group-IV semiconductor layer (315A, fig. 3A; ¶0051; Group IV semiconductor material in Group IV material does not include oxygen);
an isolation layer (111, fig. 3A) over the p-type transistor (301, fig. 3A); and wherein the n-type transistor (202, fig. 3A) comprises at least one oxide semiconductor layer (115B, fig. 3A; ¶0045 for example semiconductor metal oxides such as IGZO) and a second gate structure (110 and 217, fig. 3A) wrapping around the at least one oxide semiconductor layer (115B, fig. 3A; ¶0045 for example semiconductor metal oxides such as IGZO).
Mishra is silent regarding: a n-type transistor (202, fig. 3A) vertically stacked over the p-type transistor (301, fig. 3A) and over the isolation layer (111, fig. 3A).
Sharma discloses in figure 1 a transistor 120 can form vertically stacked over another transistor 130 with a isolation layer 110 in between.
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to include transistor vertical form on top of another transistor since this can increase transistor density and enhanced performance and speed cause of the shorter interconnection between the transistors.
Re: Claim 9, Mishra and Sharma discloses all the limitations of claim 8 on which this claim depends. Mishra further discloses: wherein the oxide semiconductor layer (115B, fig. 3A; ¶0045 for example semiconductor metal oxides such as IGZO) of the n-type transistor (202, fig. 3A) is in contact with the isolation layer (111, fig. 3A).
Re: Claim 10, Mishra and Sharma discloses all the limitations of claim 8 on which this claim depends. Mishra further discloses: wherein the first gate structure (110 and 217, fig. 3A) is continuously connected with the second gate structure (110 and 217, fig. 3A).
Re: Claim 11, Mishra and Sharma discloses all the limitations of claim 8 on which this claim depends. Mishra further discloses: a doped semiconductor layer (315A, fig. 3A; ¶0051; Group IV semiconductor material in Group IV material does not include oxygen) spacing the group-IV semiconductor layer (315A, fig. 3A; ¶0051; Group IV semiconductor material in Group IV material does not include oxygen) of the p-type transistor (301, fig. 3A) from the isolation layer (111, fig. 3A).
Re: Claim 12, Mishra and Sharma discloses all the limitations of claim 8 on which this claim depends. Mishra further discloses: a metal layer (110 in region 202, fig. 3A) between the oxide semiconductor layer (115B, fig. 3A; ¶0045 for example semiconductor metal oxides such as IGZO) of the n-type transistor (202, fig. 3A) and the isolation layer (111, fig. 3A).
Re: Claim 13, Mishra and Sharma discloses all the limitations of claim 8 on which this claim depends. Mishra further discloses: wherein the first gate structure (110 and 217, fig. 3A) wraps around a plurality of the group-IV semiconductor layer (315A, fig. 3A; ¶0051; Group IV semiconductor material in Group IV material does not include oxygen)s, and the group-IV semiconductor layer (315A, fig. 3A; ¶0051; Group IV semiconductor material in Group IV material does not include oxygen)s are vertically arranged and spaced apart from each other.
Re: Claim 14, Mishra and Sharma discloses all the limitations of claim 8 on which this claim depends. Mishra further discloses: wherein the second gate structure (110 and 217, fig. 3A) wraps around a plurality of the oxide semiconductor layer (115B, fig. 3A; ¶0045 for example semiconductor metal oxides such as IGZO)s, and the oxide semiconductor layer (115B, fig. 3A; ¶0045 for example semiconductor metal oxides such as IGZO)s are vertically arranged and spaced apart from each other.
Prior art made of record and not relied upon are considered pertinent to current application disclosure.
* (“Jung et al., US PG pub. 20200381562 A1”) Discloses a semiconductor device, including a silicon on insulator (SOI) substrate is disclosed. The device may include gate structures formed on the SOI substrate and being spaced apart from each other in a horizontal direction, and a plurality of channels spaced apart from each other in a vertical direction. Each of the channels may extend through each of the gate structures in the horizontal direction. The device may include a seed layer and a source/drain region. The source/drain region may be connected to the channels, and each sidewall of the source/drain region in the horizontal direction may have a concave-convex shape. The device may include a protruding portion of the source/drain region formed between the gate structures that protrudes in the horizontal direction compared to a non-protruding portion of the source/drain region formed between the channels.
* (“Liu et al., US PG pub. 20160211276 A1”) discloses a semiconductor device includes a first fin field effect transistor (FinFET) disposed over a substrate, and a second FinFET device disposed over the first FinFET. A junction isolation material is disposed between a source of the first FinFET and a source of the second FinFET.
* (“Yang et al., US Patent 11164943 B2”) discloses semiconductor device and a fabricating method thereof are provided. The semiconductor device includes a substrate, a first nanowire spaced apart from a first region of the substrate, a first gate electrode surrounding a periphery of the first nanowire, a second nanowire spaced apart from a second region of the substrate and extending in a first direction and having a first width in a second direction intersecting the first direction, a supporting pattern contacting the second nanowire and positioned under the second nanowire, and a second gate electrode extending in the second direction and surrounding the second nanowire and the supporting pattern.
* (“Cheng et al., US Patent 10243054 B1”) discloses directed to fabrication operations for co-integrating standard-gate (SG) and extended-gate (EG) nanosheet/nanowire transistors on the same substrate. The SG and EG nanosheet/nanowire transistors share certain fabrication operations for certain features. For example, the processes to form the bottommost channel nanosheet, the bottommost sacrificial nanosheet, and the topmost channel nanosheet are the same for SG nanosheet transistors and the EG nanosheet transistors. Because the thickness of the sacrificial nanosheet needs to be thicker for EG nanosheet transistors, a thickness of the bottommost sacrificial nanosheet is selected to accommodate the design parameters of the EG nanosheet transistor. Because the thickness of the SG and the EG channel nanosheets do not need to be different, a thickness of the bottommost channel nanosheet and the topmost channel nanosheet can be selected to accommodate the design parameters of both the SG and the EG nanosheet transistors.
Conclusion
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/TSZ K CHIU/Examiner, Art Unit 2898 Tsz.Chiu@uspto.gov
/Leonard Chang/Supervisory Patent Examiner, Art Unit 2898