Prosecution Insights
Last updated: October 02, 2026
Application No. 18/447,799

INFORMATION PROCESSING APPARATUS AND NON-TRANSITORY COMPUTER READABLE MEDIUM

Final Rejection §103
Filed
Aug 10, 2023
Priority
Feb 17, 2023 — JP 2023-023137
Examiner
RUSIN, KAYO LISA
Art Unit
2114
Tech Center
2100 — Computer Architecture & Software
Assignee
Fujifilm Holdings Corporation
OA Round
2 (Final)
89%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 89% — above average
89%
Career Allowance Rate
24 granted / 27 resolved
+33.9% vs TC avg
Strong +18% interview lift
Without
With
+17.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
13 currently pending
Career history
45
Total Applications
across all art units

Statute-Specific Performance

§101
14.1%
-25.9% vs TC avg
§103
51.4%
+11.4% vs TC avg
§102
13.5%
-26.5% vs TC avg
§112
18.4%
-21.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 27 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Amendment Applicant’s arguments filed 07/13/2026 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Reeves (US 10628280 B1) and Thompson et al (US 20180246552 A1), wherein Reeves is a new prior art and wherein Thompson has been previously used to teach the claim limitations in a dependent claim. Specification The revised title – “Information Processing Apparatus and Non-transitory Computer Readable Medium for Improved Timing of Reset Request for Watchdog Module” – has been accepted. The corresponding objection has been withdrawn. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Reeves (US 10628280 B1) in view of Thompson et al (US 20180246552 A1). The reference paragraph numbers for Reeves can be found in the associated NPL. As per claim 1, Reeves (US 10628280 B1) teaches the following: An information processing apparatus comprising: a log memory (FIG 2, event log 142) A processor, configured to (FIG 2, processing unit 118) obtain log information indicating an operation status of a log obtaining target device, ([17] when event regarding “state change” of the application occurs, the information is sent to the event logger;) store the log information in the log memory ([15] the log is stored in the partition of the event log) set a flag indicating occurrence of an abnormality in operation of the log obtaining target device in accordance with absence of an initialization signal input from the monitored processor within a certain period of time or an abnormality signal indicating occurrence of an abnormality in operation of the peripheral device input from the monitored processor ([19] “if the event ID in the call to the event logger matches an ID in a set of stop IDs of the event logger, the event logger ceases further writing to the event log…. In this manner, data occurring at a time of, and prior to the error condition is captured.” The conditional statement of event ID in the call matching an ID, triggers the following operation to occur: prevent further logging. When these conditions are being evaluated, a technical level, a flag is set whether the condition has been met or not. [19] “stop IDs could be, for example, a set of error conditions, a reboot event, etc.” Thus, the stop ID teaches the abnormality in operation of the peripheral device input from the monitored processor) stop, on a basis of the flag, obtaining the log information and cause the log memory to maintain the log information obtained so far, before issuing a reset signal to reset the log obtaining target device ([19] when the flag is set by meeting the condition of the stop ID matching the ID of the set of stop IDs of the event logger; [18] the collected data are accessible by storing it either in the short-term event log or the long-term event log; [19] the event logger can be triggered because the system initiates a reboot event; the logging occurs before the system continues with the normal operation/reboot event). upon stopping the obtaining of the log information, issue the rest signal and perform, without resetting the log memory, a reset control for resetting the log obtaining target device ([21] once the logging has completed, the standard operation resumes; [19] the trigger for the logging can be a reboot event, so the resuming of the operation can be resuming of the reboot event; [41] the event log is stored in a log partition that is separate from the previously identified log obtaining target device, and because they are separate devices, the log obtaining target device can safely be rebooted without resetting the log memory). Reeves fails to teach which is at least a monitored processor or a peripheral device, and is a device in the information processing apparatus other than the first processor However, Thompson teaches which is at least a monitored processor or a peripheral device, and is a device in the information processing apparatus other than the first processor ([0006] a battery-powered programmable integrated circuit of a smart battery pack that is separate from the information handling system that can track the environmental conditions). It is obvious to a person of ordinary skill in the art to combine the teaching of Reeves with the teaching of Thompson because Reeves already teaches a sensor 120 (27] that can be “any sensor that receives input from environmental stimuli” and [38] can trigger a given interrupt service routine, [43] which is used as part of the logged data collected by the application. Thompson provides an implementation detail of a specific sensor and how it logs its monitored data. Per claim 2, Reeves in view of Thompson teaches: the information processing apparatus according to claim 1 (see above) wherein the processor is different from the monitored processor and starts to obtain the log information before power is supplied to the monitored processor (Thompson [0006]: “The disclosed systems and methods may be implemented in one embodiment using a battery-powered programmable integrated circuit of a smart battery pack to track the environmental conditions, operating conditions, and/or event information to which a battery pack and/or battery-powered information handling system is exposed, e.g., such as while a battery pack is not paired with any information handling system” – this part of the prior art excerpt teaches the part where the monitored processor is separate from the original processor since it is separate from any information handling system, which can include the monitoring component as well as the logging component. – “or while the remainder of the components of a paired information handling system have been powered OFF during system storage and/or transportation” – this part of the prior art excerpt teaches that the information is collected even while the monitored processor is turned off. The information handling system represents the monitored processor since it is the processor dealing monitoring. It should be noted that Thompson is only being relied upon to teach the monitored processor and its relationship with the battery-powered programmable integrated circuit; Reeves is relied upon for the logging component) Per claim 3, Reeves in view of Thompson teaches: the information processing apparatus according to claim 1 (see above) wherein the monitored processor reads, after the reset control is performed, the log information from the log memory and stores the log information in a nonvolatile memory ([19] after the logging is performed, the reset control is performed as part of the resumed reboot event; [55] the content of the log partition can be uploaded to the controller, [24] which is non-volatile memory) As per claim 4, it recites similar claim limitation as claim 1 and thus are rejected for similar reasons. It additionally recites the following (and Reeves in view of Thompson teaches this): A non-transitory computer readable medium storing a program causing a computer including a log memory to execute a process for processing information (Reeves [4]: “One example relates to a non-transitory machine-readable medium that includes machine executable instructions. The machine executable instructions include an application that executes a plurality of tasks and responds to interrupts. The application can include an event logger that writes data values to an event log stored in an assigned partition of memory in response to a call to the event logger” The excerpt teaches the presence of the non-transitory computer readable medium storing the program as well as the log memory) Per claim 5, Reeves teaches (Currently Amended) An information processing apparatus comprising: a first processor that achieves a function of a log obtaining module; (Reeves, FIG. 2, processing unit 118; as indicated in [17]-[19], the processing unit implements the log obtaining module) … a log memory (Reeves, FIG. 2, log partition 140) wherein the first processor obtains log information indicating an operation status of a log obtaining target device (Reeves, [17] when event regarding “state change” of the application occurs, the information is sent to the event logger),…, and stores the log information in the log memory (Reeves, [15] the log is stored in the partition of the event log), wherein the first processor stops, on a basis of the flag, obtaining the log information and causes the log memory to maintain the log information obtained so far, before issuing a reset signal to reset the log obtaining target device, and (Reeves, [19] when the flag is set by meeting the condition of the stop ID matching the ID of the set of stop IDs of the event logger; [18] the collected data are accessible by storing it either in the short-term event log or the long-term event log; [19] the event logger can be triggered because the system initiates a reboot event; the logging occurs before the system continues with the normal operation/reboot event; FIG. 2, processing unit 118; as indicated in [17]-[19], the processing unit implements the log obtaining function) wherein the … processor performs, upon the obtaining of the log information being stopped by the first processor, issuing the reset signal and, without resetting the log memory, executing a reset control for resetting the log obtaining target device (Reeves, [21] once the logging has completed, the standard operation resumes; [19] the trigger for the logging can be a reboot event, so the resuming of the operation can be resuming of the reboot event; [41] the event log is stored in a log partition that is separate from the previously identified log obtaining target device, and because they are separate devices, the log obtaining target device can safely be rebooted without resetting the log memory.) Reeves fails to teach which is at least a monitored processor or a peripheral device, and is a device in the information processing apparatus other than the first processor wherein the second processor sets a flag indicating occurrence of an abnormality in operation of the log obtaining target device in accordance with absence of an initialization signal input from the monitored processor within a certain period of time or an abnormality signal indicating occurrence of an abnormality in operation of the peripheral device input from the monitored processor a second processor that achieves a function of a timer module; a third processor that achieves a function of a reset control module; and However, Thompson teaches which is at least a monitored processor or a peripheral device, and is a device in the information processing apparatus other than the first processor ([0006] a battery-powered programmable integrated circuit of a smart battery pack that is separate from the information handling system that can track the environmental conditions). wherein the second processor sets a flag indicating occurrence of an abnormality in operation of the log obtaining target device in accordance with absence of an initialization signal input from the monitored processor within a certain period of time or an abnormality signal indicating occurrence of an abnormality in operation of the peripheral device input from the monitored processor ([0043] “pre-boot diagnostics may include… system board and motherboard operation (…timers…) testing…” (FIG. 4, step 406), if the exception event was detected during the diagnostics, system flags this or marks it in a special manner for further processing). a second processor that achieves a function of a timer module; a third processor that achieves a function of a reset control module; and ([0052] “one or more of the tasks, functions, or methodologies described herein for an information handling system or component thereof (e.g., including those described herein for components 205, 220, 266, 269, 283, etc.) may be implemented by circuitry …, in which the computer program comprising instructions are configured when executed (e.g., executed on a programmable integrated circuit such as CPU, controller, microcontroller, microprocessor, ASIC, etc. or executed on a programmable logic device “PLD” such as FPGA, complex programmable logic device “CPLD”, etc.) to perform one or more steps of the methodologies disclosed herein. In one embodiment, a group of such processors and PLDs may be programmable integrated circuits selected from the group consisting of CPU, controller, microcontroller, microprocessor, FPGA, CPLD and ASIC.” Therefore, a group of processors may be used to teach the above functionalities and tasks) It is obvious to a person of ordinary skill in the art to combine the teaching of Reeves with the teaching of Thompson because Reeves already teaches a sensor 120 (27] that can be “any sensor that receives input from environmental stimuli” and [38] can trigger a given interrupt service routine, [43] which is used as part of the logged data collected by the application. Thompson provides an implementation detail of a specific sensor and how it logs and processes its monitored data. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAYO LISA RUSIN whose telephone number is (703)756-1679. The examiner can normally be reached Monday-Friday 8:30 - 5:00 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached at 571-272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /K.L.R./Examiner, Art Unit 2114 /ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114
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Prosecution Timeline

Aug 10, 2023
Application Filed
Oct 18, 2023
Response after Non-Final Action
Apr 20, 2026
Non-Final Rejection mailed — §103
Jul 13, 2026
Response Filed
Aug 11, 2026
Final Rejection mailed — §103 (current)

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Prosecution Projections

3-4
Expected OA Rounds
89%
Grant Probability
99%
With Interview (+17.6%)
2y 2m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 27 resolved cases by this examiner. Grant probability derived from career allowance rate.

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