CTNF 18/447,799 CTNF 99226 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Specification 06-11 AIA The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-12-aia AIA (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. 07-15 AIA Claim s 1, 3-4 are rejected under 35 U.S.C. 102( a)(1) and 35 U.S.C. 102(a)(2 ) as being anticipated by Yamaguchi (US 20190278652 A1) . Yamaguchi teaches the following: Per claim 1, An information processing apparatus (FIG. 1) comprising: a log memory; and (FIG. 4, non-volatile memory 21, [0047] the power supply controller logs information such as input date and time of the watchdog reset request here) a processor configured to: ([0047] the power supply controller 9) obtain log information indicating an operation status of a log obtaining target device, which is at least a monitored processor or a peripheral device, which is a device in the information processing apparatus other than the monitored processor ([0046] the control circuit 10 is being monitored. [0047] receives the “date and time of the watchdog reset request” as log information) and store the log information in the log memory ([0047] the “date and time of the watchdog reset request” is logged in the non-volatile memory ) set a flag indicating occurrence of an abnormality in operation of the log obtaining target device in accordance with absence of an initialization signal input from the monitored processor within a certain period or an abnormality signal indicating occurrence of an abnormality in operation of the peripheral device input from the monitored processor; ([0045]-[0046] while monitoring the control circuit 10, when the watchdog timer does not receive an initialization signal during a period of time, it indicates an abnormality. The “flag” is the watchdog timer reset request because it is an indication to other components than an error has occurred) stop, on a basis of the flag, obtaining the log information ([0047] after the flag is set or the receipt of the “watchdog timer reset request,” the system ends the cycle of monitoring and thus stops obtaining the log information) and cause the log memory to maintain the log information obtained so far before the log obtaining target device in the operation of which the abnormality has occurred is reset; and ([0046]-[0047] log information is captured and stored in the non-volatile memory 21; [0051] the memory is not being reset so it is being maintained) perform, without resetting the log memory after stopping obtaining the log information, reset control for resetting the log obtaining target device in the operation of which the abnormality has occurred. ([0051] the power supply controller performs a partial reset which only resets the control circuit 10 and not the non-volatile memory 21. This is occurring right after the receipt of the watchdog timer reset request and thus no further log information is being obtained) Per claim 3, The information processing apparatus according to claim 1, wherein the monitored processor reads, after the reset control is performed, the log information from the log memory and stores the log information in a nonvolatile memory. ([0055] after a reset, the log stored in the non-volatile memory can be stored into a portable storage device, which is non-volatile memory) Per claim 4, recites similar claim limitation as claim 1. It additionally recites A non-transitory computer readable medium (FIG. 1, multifunction peripheral 100) storing a program (FIG. 1, controller 1) causing a computer including a log memory (FIG. 4, non-volatile memory 21) to execute a process for processing information Furthermore, “performing…” clause is further limited in scope by “ on a basis of the flag without resetting the log memory;” however, it does not change the teachings from the prior art and thus is rejected similarly as claim 1 . Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamaguchi in view of Thompson et al (US 20180246552 A1) . Per claim 2, Yamaguchi teaches The information processing apparatus according to claim 1, wherein the processor is different from the monitored processor (FIG. 4, power supply controller 9 is “the processor” and control circuit 10 is “the monitored processor”) Yamaguchi fails to teach starts to obtain the log information before power is supplied to the monitored processor. However, Thompson teaches the importance of “[tracking] the environmental conditions, operating conditions, and/or event information to which a battery pack and/or battery-powered information handling system is exposed, e.g., such as while a battery pack is not paired with any information handling system or while the remainder of the components of a paired information handling system have been powered OFF during system storage and/or transportation” ([0006]). It would have been obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teaching of Yamaguchi and the teaching of Thompson in order to teach “[obtaining] the log information before power is supplied to the monitored processor” because collecting the environmental data of the monitored device (even if the monitored device itself is powered off) can aid in an optimization of root cause analysis (Thompson, [0003]) . 07-21-aia AIA Claim (s) 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamaguchi in view of Tavallaei et al (US 6070253 A) . Per claim 5, Yamaguchi teach An information processing apparatus (FIG. 1) comprising: a first processor that achieves a function of a log obtaining module; ([0047] the power supply controller 9 makes the non-volatile memory store the input date and time of the watchdog reset request; the first processor is the power supply controller 9) a second processor that achieves a function of a timer module; ([0045] watchdog timer 8 in FIG. 1) … a log memory (FIG. 4, non-volatile memory 21) , wherein the first processor obtains log information indicating an operation status of a log obtaining target device, which is at least a monitored processor or a peripheral device, which is a device in the information processing apparatus other than the monitored processor ([0046] the control circuit 10 is being monitored. [0047] receives the “date and time of the watchdog reset request” as log information), and stores the log information in the log memory ([0047] the “date and time of the watchdog reset request” is logged in the non-volatile memory; the first processor is the power supply controller ) wherein the second processor sets a flag indicating occurrence of an abnormality in operation of the log obtaining target device in accordance with absence of an initialization signal input from the monitored processor within a certain period or an abnormality signal indicating occurrence of an abnormality in operation of the peripheral device input from the monitored processor, ([0045]-[0046] while monitoring the control circuit 10, when the watchdog timer does not receive an initialization signal during a period of time, it indicates an abnormality. The “flag” is the watchdog timer reset request because it is an indication to other components than an error has occurred; the second processor is the watchdog timer) wherein the first processor stops, on a basis of the flag, obtaining the log information ([0047] after the flag is set or the receipt of the “watchdog timer reset request,” the system ends the cycle of monitoring and thus stops obtaining the log information; first processor is the power supply controller) and causes the log memory to maintain the log information obtained so far before the log obtaining target device in the operation of which the abnormality has occurred is reset, and ([0046]-[0047] log information is captured and stored in the non-volatile memory 21; [0051] the memory is not being reset so it is being maintained; first processor is the power supply controller) wherein … performs, on a basis of the flag without resetting the log memory, reset control for resetting the log obtaining target device in the operation of which the abnormality has occurred. ([0051] the power supply controller performs a partial reset which only resets the control circuit 10 and not the non-volatile memory 21. This is occurring right after the receipt of the watchdog timer reset request and thus no further log information is being obtained) Yamaguchi fails to teach a third processor that achieves a function of a reset control module However, Tavallaei teaches a third processor that achieves a function of a reset control module (col 2 lines 53-67, a virtual terminal offers a remote method of reset control module) It is obvious to a person of ordinary skill in the art prior to the effective filing date of the claimed invention to combine the teaching of Yamaguchi with the teaching of Tavallaei in order to teach a separate remote processor that handles the reset control module because it aids in managing a network of distributed server from a single, remote site (col 2, lines 59-61). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAYO LISA RUSIN whose telephone number is (703)756-1679. The examiner can normally be reached Monday-Friday 8:30 - 5:00 EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Ashish Thomas can be reached at 571-272-0631. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /K.L.R./ Examiner, Art Unit 2114 /ASHISH THOMAS/Supervisory Patent Examiner, Art Unit 2114 Application/Control Number: 18/447,799 Page 2 Art Unit: 2114 Application/Control Number: 18/447,799 Page 3 Art Unit: 2114 Application/Control Number: 18/447,799 Page 4 Art Unit: 2114 Application/Control Number: 18/447,799 Page 5 Art Unit: 2114 Application/Control Number: 18/447,799 Page 6 Art Unit: 2114 Application/Control Number: 18/447,799 Page 7 Art Unit: 2114 Application/Control Number: 18/447,799 Page 8 Art Unit: 2114 Application/Control Number: 18/447,799 Page 9 Art Unit: 2114 Application/Control Number: 18/447,799 Page 10 Art Unit: 2114
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