DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The Examiner acknowledges the applicant's submission of the amendment dated 11/25/25, which has been entered.
1. REJECTIONS BASED ON PRIOR ART
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC ' 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Sity (US 20190341091) In view of Lokhandwala (US 20200186455).
With respect to claim 1, the Sity reference teaches a memory controller comprising:
a first chip configured to perform a first operation of the memory controller; (see fig. 6, processor element 640; paragraphs 102-103, where processor subunit 610 comprises a processing element 640 that may comprise a processor; and where processing element 640, which executes received or stored code, may comprise a generic processing element and, therefore, be flexible and capable of performing a wide variety of processing operations)
a plurality of second chips configured to perform a second operation of the memory controller; (see fig. 6, accelerators 650; paragraph 104, where the specific operations may be performed by one or more accelerators 650. Each accelerator may be dedicated and programmed to perform a specific calculation (such as multiplication, floating point vector operations, or the like). By using accelerator(s))
a plurality of data links configured to connect the first chip and each of the plurality of second chips on a one-to-one basis and provide data transmission between the first chip and each of the plurality of second chips; (see fig. 6; and where processor element 640 and the accelerators 650 are connected on a ‘one-to-one’ basis via a bus; and paragraph 104, where accelerator(s) 650 may be configured by processing element 640 and may operate in tandem therewith for lowering power consumption and accelerating calculations and computations)
a control link connected to the first chip and the plurality of second chips and configured to transmit a control code for performing the second operation of the plurality of second chips; (see fig. 6; and where processor element 640 and the accelerators 650 are connected via a bus; and paragraph 104, where accelerator(s) 650 may be configured by processing element 640 and may operate in tandem therewith for lowering power consumption and accelerating calculations and computations)
a memory connected to the first chip and configured to store the control code, wherein the first chip is configured to: obtain the control code from the memory; (see fig. 6, memory 620; and paragraph 100, where memory 620 may comprise a Randomly Accessible Memory (RAM) element that stores data and code for execution by processor subunit 610) and
transmit the control code to the plurality of second chips at a same time through the control link. (see fig. 6; and where processor element 640 and the accelerators 650 are connected via a bus; and paragraph 104, where accelerator(s) 650 may be configured by processing element 640 and may operate in tandem therewith for lowering power consumption and accelerating calculations and computations; and where each accelerator may be dedicated and programmed [analogous to the ‘control code’] to perform a specific calculation (such as multiplication, floating point vector operations, or the like); and paragraph 186, where the processor may assign tasks associated with the series of instructions to different ones of the processor subunits [such as the accelerators noted above]. For example, the series of instructions may be divided into subgroups, the subgroups to be executed in parallel across the processor subunits [analogous to “at a same time” as claimed])
However, the Sity reference does not explicitly teach wherein the transmitting of the control code is repeated until reception completion messages for the control code are received from all of the plurality of second chips.
The Lokhandwala reference teaches it is conventional to have wherein the transmitting of the control code is repeated until reception completion messages for the control code are received from all of the plurality of second chips. (paragraph 19, where if fault detector 108 determines that the communication latency within distributed system 100 has gone up during a polling round (by, e.g., noticing that some nodes are not able to respond to the poll message within a given timeout interval), fault detector 108 can resend the poll message, wait for a slightly longer timeout interval, and repeat these steps until either (1) all nodes are able to respond within the timeout interval)
It would have been obvious to a person of ordinary skill in the art before the claimed invention was effectively filed to modify the Sity reference to have wherein wherein the transmitting of the control code is repeated until reception completion messages for the control code are received from all of the plurality of second chips, as taught by the Lokhandwala reference.
The suggestion/motivation for doing so would have been to include a dynamic timeout-based approach, wherein the fault detectors 108(1)-(N) of distributed system 100 can carry out their duties while minimizing or avoiding the drawbacks associated with a static timeout interval. (Lokhandwala, paragraph 21)
Therefore it would have been obvious to combine the Sity and Lokhandwala references for the benefits shown above to obtain the invention as specified in the claim.
With respect to claim 2, the combination of the Sity and Lokhandwala references teaches the memory controller of claim 1, wherein the control link is formed in a way that the first chip and all the plurality of second chips are connected to at least one line in a bus form, and configured to support one-way transmission from the first chip to the plurality of second chips. (Sity, see fig. 6; and where processor element 640 and the accelerators 650 are connected via a bus; and paragraph 104, where accelerator(s) 650 may be configured by processing element 640 and may operate in tandem therewith for lowering power consumption and accelerating calculations and computations; and Lokhandwala, paragraph 25, where fault detector 108 can transmit a poll message to every other node within distributed system 100 and can wait for an ACK message from each recipient node over timeout interval T)
With respect to claim 3, the combination of the Sity and Lokhandwala references teaches the memory controller of claim 2, wherein each of the plurality of second chips is configured to transmit the reception completion message to the first chip through a corresponding data link connected to the first chip after a reception of the control code is completed. (Sity, see fig. 6; and where processor element 640 and the accelerators 650 are connected via a bus; and paragraph 104, where accelerator(s) 650 may be configured by processing element 640 and may operate in tandem therewith for lowering power consumption and accelerating calculations and computations; and Lokhandwala, paragraph 25, where fault detector 108 can transmit a poll message to every other node within distributed system 100 and can wait for an ACK message from each recipient node over timeout interval T)
With respect to claim 4, the combination of the Sity and Lokhandwala references teaches the memory controller of claim 1, wherein the first chip is further configured to transmit the control code at a random time without obtaining state information on each of the plurality of second chips and without exchanging, with the plurality of second chips, information indicating that the control code is to be transmitted. (Sity, see fig. 6; and where processor element 640 and the accelerators 650 are connected via a bus; and paragraph 104, where accelerator(s) 650 may be configured by processing element 640 and may operate in tandem therewith for lowering power consumption and accelerating calculations and computations; and paragraph 326, where the processing units or memory controller 2210 may randomly select an accelerator 2216 and create a test data access pattern, which may be modified as the task is executed)
With respect to claim 5, the combination of the Sity and Lokhandwala references teaches the memory controller of claim 1, wherein the control code includes a plurality of unit codes, each unit code including data and an index indicating a position in the control code. (Sity, paragraph 92, where processor subunit 430 may further include an address generator 450. An “address generator” may comprise a plurality of processing elements that are configured to determine addresses in one or more memory banks for performing reads and writes and may also perform operations on the data located at the determined addresses (e.g., addition, subtraction, multiplication, or the like))
With respect to claim 6, the combination of the Sity and Lokhandwala references teaches the memory controller of claim 5, wherein the second chip is configured to: set an index area of a control code to be used; when an index of a unit code included in the control code transmitted by the first chip is included in the index area, recognize the unit code as a control code to be used and store the unit code or data in the unit code at a position corresponding to the index in the unit code; and transmit the reception complete message to the first chip after data has been stored for all indexes included in the index area. (Sity, paragraph 92, where processor subunit 430 may further include an address generator 450. An “address generator” may comprise a plurality of processing elements that are configured to determine addresses in one or more memory banks for performing reads and writes and may also perform operations on the data located at the determined addresses (e.g., addition, subtraction, multiplication, or the like); and address generator 450 may determine addresses for any reads or writes to memory. In one example, address generator 450 may increase efficiency by overwriting a read value with a new value determined based on the command when the read value is no longer needed. Additionally or alternatively, address generator 450 may select available addresses for storage of results from execution of the command. This may allow for scheduling of result read-off for a later clock cycle, when it is more convenient for the external host.)
With respect to claim 7, the combination of the Sity and Lokhandwala references teaches the memory controller of claim 6, wherein the second chip is configured to execute the control code to perform the second operation. (Sity, paragraph 92, where processor subunit 430 may further include an address generator 450. An “address generator” may comprise a plurality of processing elements that are configured to determine addresses in one or more memory banks for performing reads and writes and may also perform operations on the data located at the determined addresses (e.g., addition, subtraction, multiplication, or the like); and see fig. 6; and where processor element 640 and the accelerators 650 are connected via a bus; and paragraph 104, where accelerator(s) 650 may be configured by processing element 640 and may operate in tandem therewith for lowering power consumption and accelerating calculations and computations))
With respect to claim 8, the combination of the Sity and Lokhandwala references teaches the memory controller of claim 1, wherein the first chip is configured to, in response to a reception of a message according to the second operation through a data link connected to the second chip, recognize the message as the reception complete message. (Sity, see fig. 6; and where processor element 640 and the accelerators 650 are connected via a bus; and paragraph 104, where accelerator(s) 650 may be configured by processing element 640 and may operate in tandem therewith for lowering power consumption and accelerating calculations and computations))
2. ARGUMENTS CONCERNING PRIOR ART REJECTIONS
Rejections - USC 102/103
Applicant's arguments (see pages 8-11 of the remarks) and amendments with respect to claims 1-8 have been considered, and are not persuasive. Specifically, the Applicant argues (see page 11) claim 1 with respect to the Sity and Lokhandwala references as to not explicitly teaching the limitations of “transmitting the control code to the plurality of second chips at a same time". As noted in the updated citations above, the Sity reference teaches (paragraph 186) “the processor may assign tasks associated with the series of instructions to different ones of the processor subunits [such as the accelerators noted above]. For example, the series of instructions may be divided into subgroups, the subgroups to be executed in parallel across the processor subunits [analogous to “at a same time” as claimed].” Thus, based on the citations above, the Sity reference discusses a processor (analogous to a first chip) transmitting tasks associated with the series of instructions across multiple processor subunits [i.e. “accelerators” noted above in the rejection] (analogous to second chips) in a parallel fashion [i.e. “at a same time” as claimed]. Therefore, the Examiner contends the prior art of record teaches the limitations above for the reasons set forth above. Further, the Examiner notes the arguments pertaining to dependent claims 2-8 are commensurate in scope with the arguments above, and thus the Examiner notes the response above.
3. CLOSING COMMENTS
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to PRASITH THAMMAVONG whose telephone number is (571) 270-1040. The examiner can normally be reached Monday - Friday 12-8 PM EST.
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/PRASITH THAMMAVONG/
Primary Examiner, Art Unit 2137