Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 3/5/2026 has been entered. Claims 1-20 remain pending in the present application.
Response to Arguments
Applicant argued that Kim does not teach or suggest “converting the update data into a plurality of continuous images; and using the plurality of continuous images to update the animation data in the memory”. The argument has been fully considered, but is moot in view of the new ground of rejection, necessitated by the present amendment.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In particular, independent claim 1 recites “writing the plurality of images into the OSD buffer sequentially; and outputting the plurality of images to the display circuit sequentially to form an OSD animation on the display circuit”. It’s not clear whether the “plurality of images” refers to the “plurality of continuous images” after the animation data has been updated, or is the “plurality of images” before the update occurs. Based on the order of the steps recited in the claim, it is understood that it refers to the “plurality of continuous images”. If this is the case, the examiner suggests that claim 1 should be amended to recite: “writing the plurality of continuous images from the memory into the OSD buffer sequentially; and outputting the plurality of continuous images from the OSD buffer to the display circuit sequentially to form an OSD animation on the display circuit”.
Independent claims 9 and 16 also have similar issues that need to be addressed.
Other dependent claims are also rejected under 35 U.S.C. 112(b) by virtue of their dependency.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 6, 8-11, 13, and 15-18 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (Pub. No. US 2011/0096090), in view of Reddy (Pub. No. US 2001/0040581), further in view of Maine et al. (Pat. No. 4,864,517), and still further in view of Neulander (Pub. No. US 2016/0328866).
Regarding claim 1, Lee discloses an operating method for a display control chip (See Fig. 1 and par. 23: “The microcontroller 13 and the image output unit 14 are usually integrated in an image-processing chip”), wherein the display control chip (See pars. 21-23. The second memory 12 could be viewed as an “OSD buffer” because it stores OSD image frames retrieved from first memory 11 to be outputted to image output unit 14), the operating method comprises:
in response to the display control chip being powered on (Fig. 7 and par. 51: “the first memory 11 stores a plurality of OSD frames 71, 72, 73, 74 and the original OSD menu frame 75”. In particular, OSD frames 71-74 comprise animation data. Since Lee does not disclose updating the animation data, it is understood that every time the image-processing chip is powered on, it would read the same animation data from the first memory 11) to a display circuit sequentially to form a previous OSD animation on the display circuit (Par. 52: “The microcontroller 13 is capable of accessing the first and second memories 11,12, for reading sequentially the OSD frames 71-74 and the original OSD frame 75 from the first memory 11 and outputting sequentially the OSD frames 71-74 and the original OSD menu frame 75 to the second memory 12 in response to the command for opening the OSD menu. The image output unit 14 reads sequentially and continuously the OSD frames 71-74 and the original OSD frame 75 from the second memory 12 and outputs the OSD menu frames 71-74 and the original OSD frame 75 to the display unit 10 for display, generating the visual effect of the man walking, perhaps walking from a center of a screen of the display unit 10 to the left or right, prior to displaying the original OSD menu frame 75, thus effecting animation of the OSD menu”), wherein the animation data is data stored in the memory when the display control chip is powered off at the last time (Par. 23: “the first memory 11 is a read-only memory, and includes a flash memory 15 for storing OSD animation program instructions i.e., firmware, and an electrically erasable programmable read-only memory (EEPROM) 16 for storing the original OSD menu frame”. In particular, a read-only memory (ROM) is a type of non-volatile memory, meaning it retains its stored information even when power is turned off);
writing a plurality of images into the OSD buffer sequentially (Par. 52: “The microcontroller 13 is capable of accessing the first and second memories 11, 12, for reading sequentially the OSD frames 71-74 and the original OSD frame 75 from the first memory 11 and outputting sequentially the OSD frames 71-74 and the original OSD menu frame 75 to the second memory 12 in response to the command for opening the OSD menu”); and
outputting the plurality of images to the display circuit sequentially to form an OSD animation on the display circuit (Par. 52: “The image output unit 14 reads sequentially and continuously the OSD frames 71-74 and the original OSD frame 75 from the second memory 12 and outputs the OSD menu frames 71-74 and the original OSD frame 75 to the display unit 10 for display, generating the visual effect of the man walking, perhaps walking from a center of a screen of the display unit 10 to the left or right, prior to displaying the original OSD menu frame 75, thus effecting animation of the OSD menu”).
Lee, however, does not disclose that: (1) the image-processing chip comprises the OSD buffer (the second memory), (2) using update data to update the animation data in the memory, wherein (3) the update data is converted into a plurality of continuous images.
Regarding (1), Reddy teaches an on-chip frame buffer memory that is integrated into the same chip as a graphics accelerator (See abstract and pars. 23-24).
In light of Reddy’s teaching, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to integrate the second memory 12 into the image-processing chip of Lee. The motivation would have been to increases the performance of the graphics display system because display data retrieved from an on-chip buffer memory is much faster than from an external buffer memory (Reddy, par. 16).
Regarding (2), Maine teaches a double-buffer memory F” that facilitates animation data update from an external data source J (See Fig. 3 and col. 1, ll. 5-13 and col. 6, ll. 34-48).
In light of Maine’s teaching, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to further modify Lee by replacing the second memory 12 with the frame buffer F” taught by Maine, wherein a plurality of continuous images stored in the frame buffer can be updated from an external data source. The motivation would have been to produce continuous variable and animated displays while at the same time allocating half of the total time to the external data source (Maine, col. 3, ll. 38-42). Note that with this modification, the first memory 11 of Lee would play the role of the pattern memory A taught by Maine, which is used for storing updated animation data from the external data source J.
Regarding (3), Neulander teaches converting vector data into a plurality of continuous image frames for animation (See pars. 26-27).
In light of Neulander’s teaching, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to further modify Maine by configuring the external data source J (e.g. a mobile device installed with the program taught by Neulander) to convert animation data (e.g. vector data) into a plurality of continuous image frames that can be used for updating the content of the frame buffer F”. The motivation would have been to provide a means for updating animation data based on simple brush strokes.
Regarding claim 2, Lee in view of Reddy, Maine and Neulander teaches the operating method of claim 1, wherein the OSD buffer comprises a plurality of sub-buffers (Fig. 3 of Maine shows frame buffers I and II, each of which could be viewed as a sub-buffer of buffer F”), and writing the plurality of images into the OSD buffer sequentially comprises:
writing the plurality of images into the OSD buffer sequentially, wherein the plurality of sub-buffers are configured to sequentially receive the plurality of images written into the OSD buffer (See Maine, Fig. 4 and col. 6, line 49 through col. 7, line 5).
Regarding claim 3, Lee in view of Reddy, Maine and Neulander teaches the operating method of claim 1, wherein the OSD buffer comprises a sub-buffer configured to store the plurality of images sequentially (Fig. 3 of Maine shows frame buffers I and II, each of which could be viewed as a sub-buffer of buffer F”. Each of these sub-buffers is configured to store a plurality of images sequentially, as illustrated in Fig. 4).
Regarding claim 6, Lee in view of Reddy, Maine and Neulander teaches the operating method of claim 1, wherein outputting the plurality of images to the display circuit sequentially comprises:
overlaying a first image of the plurality of images to a background image to generate display data, wherein the background image is stored in the display control chip; and outputting the display data to the display circuit (See the abstract and par. 9 of Lee. In particular, the original OSD menu screen corresponds to the claimed “background image”, which is stored in the second memory. In another embodiment, the original OSD menu screen is overlaid by N covering frames that have progressively reduced covering areas during the animation of the OSD menu screen).
Regarding claim 8, Lee in view of Reddy, Maine and Neulander teaches the operating method of claim 1, further comprising:
in response to receiving the update data, outputting a default image of the display control chip to the display circuit (Fig. 4 of Maine shows during time slot 2, the pattern memory is updated by the external data source while the content of frame buffer II is being displayed. This content corresponds to the claimed “default image”).
Claims 9-11, 13 and 15 recite similar limitations as respective claims 1-3, 6 and 8, but are directed to a display control chip. Since Lee also discloses such a control chip, these claims could be rejected under the same rationales set forth in the rejection of their respective claims.
Claims 16-18 could also be rejected using similar rationales as set forth in the rejection of respective claims 1-3. Note that the combination of Lee, Reddy and Maine also teaches the following limitations that are not recited in claim 1: “an input device configured to generate update data,” (The external memory 144 in Fig. 2 of Maine could be viewed as an input device configured to generate update data).
Claims 4, 12 and 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Reddy, Maine and Neulander, and further in view of Hirohara (Pub. No. US 2009/0015581).
Regarding claim 4, Lee in view of Reddy, Maine and Neulander teaches the operating method of claim 1,
In the same field of image processing, Hirohara teaches associating an update time interval to each display object in a virtual scene (See Fig. 7 and par. 41).
In light of Hirohara’s teaching, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to further modify Lee by associating a playback time to each of the plurality of images, and writing the plurality of images into the OSD buffer sequentially by writing the plurality of playback times respectively with the plurality of images into the OSD buffer sequentially. The motivation would have been to create a one-to-one correspondence between images and their playback times.
Claim 12 recites similar limitations as claim 4, but is directed to a display control chip. Since Lee in view of Reddy and Maine also teaches a display control chip (See the rejection of claim 9), claim 12 could be rejected under the same rationale set forth in the rejection of claim 4.
Claim 19 recites similar limitations as claim 4, but is directed to a display system. Since Lee in view of Reddy and Maine also teaches such a display system (See the rejection of claim 16), claim 19 could be rejected under the same rationale set forth in the rejection of claim 4.
Regarding claim 20, Lee in view of Reddy, Maine, Neulander and Hirohara teaches the operating method of claim 19, wherein the display circuit is configured to:
receive a first image of the plurality of images and a first playback time of the plurality of playback times corresponding to the first image from the OSD buffer; and display the first image for the first playback time (As shown in Fig. 4 of Maine, during time slots 1 and 2, a first image frame received in frame buffer II is displayed. When modified by Hirohara, the first image frame would be associated with a first playback time, as explained in the rejection of claim 4);
during the time that the first image is displayed, receive a second image of the plurality of images and a second playback time of the plurality of playback times corresponding to the second image from the OSD buffer; and display the second image for the second playback time (Refer to Fig. 4 of Maine again. During time slot 2, a second image frame is received from the external data source (along with its associated second playback time, as modified by Hirohara) while the first image frame is still being displayed. The second image frame stored in frame buffer I is then displayed during time slots 3 and 4).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Reddy, Maine and Neulander, and further in view of Aswadhati (Pat. No. US 9,250,687).
Regarding claim 5, Lee in view of Reddy, Maine and Neulander teaches the operating method of claim 1,
In the same field of data storage technology, Aswadhati teaches a pluggable flash memory (Col. 4, ll. 25-31: “Flash pluggable modules are preferably hot-swappable and hot-pluggable. The CPU blades can choose to take a worn out or defective flash pluggable module out of service. Maintenance personnel can then replace such modules with fresh modules, without bringing down the system or the affected flash blade. Status LEDs can be provided to indicate when it is safe to remove a module”).
In light of Aswadhati’s teaching, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to further modify Lee by replacing the first memory 11 (comprising a flash memory 15) with a flash pluggable module. The motivation would have been to facilitate replacing a defective module with a new one without bringing down the system.
Claims 7 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Reddy, Maine and Neulander, and further in view of Chung et al. (Pat. No. US 7,047,552).
Regarding claim 7, Lee in view of Reddy, Maine and Neulander teaches the operating method of claim 1, wherein outputting the plurality of images to the display circuit sequentially comprises:
overlaying a first image of the plurality of images to the background image to generate display data; and outputting the display data to the display circuit (See the rejection of claim 6 above).
In the same field of OSD images, Chung teaches receiving an OSD image from an external video source (See the abstract and col. 3, ll. 42-65).
In light of Chung’s teaching, it would have been obvious to one skilled in the art before the effective filing date of the claimed invention to further modify Lee by configuring the display device to receive a background image from an external video source. The motivation would have been to enable a user to alter OSD display data without having to store a large number of different types of OSD display data (Chung, abstract).
Claim 14 recites similar limitations as claim 7, but is directed to a display control chip. Since Lee in view of Reddy and Li also teaches a display control chip (See the rejection of claim 9), claim 14 could be rejected under the same rationale set forth in the rejection of claim 7.
Conclusion
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/PHONG X NGUYEN/ Primary Patent Examiner, Art Unit 2617