DETAILED ACTION
1. Claims 1-20 are pending in the application.
Notice of Pre-AIA or AIA Status
2. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
3. Applicant’s election without traverse of claims 1-6 and 18-20 in the reply filed on 06/15/2026 is acknowledged.
Claims 7-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made in the reply filed on 06/15/2026.
Claim Rejections - 35 USC § 103
4. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
5. Claim(s) 1-2, 4-6 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nurvitadhi et al (hereafter Nurvitadhi)(US Pub. 20190205746) in view of Rubanovich et al (hereafter Rubanovich)(US Pub. 20200310756).
6. As to claim 1, Nurvitadhi discloses an apparatus for processing tiles ([0320 tiles) in deep learning models ([0197] deep learing), the apparatus comprising:
a parallel processing unit, wherein the parallel processing unit comprises a plurality of processing threads ([0003] and [0056] parallel processing components and processing threads) comprised of a plurality of processing elements, wherein the plurality of processing elements include at least two single instruction multiple data lanes ([0109]-[0112] SIMD processing), the plurality of single instruction multiple data lanes each comprising a multiply and accumulate unit configured to process a data structure ([0277]-[0281] multiply accumulate).
7. Nurvitadhi does not disclose zero-tiles and a zero-tile format data structure. However, Rubanovich discloses zero-tiles and a zero-tile format data structure ([0074]-[0077] and [0158] zero tiles.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the teachings of Nurvitadhi by implementing the zero-tiles as in Rubanovich, for the benefit of improving power and performance of processor hardware in a machine learning context, as this would reduce the power consumption of the instructions (Rubanovich [0005]).
8. As to claim 2, the combination of Nurvitadhi and Rubanovich discloses clock gate logic components configured to receive a zero tile, wherein a logic function of the clock gate logic components gates the clock to the multiply and accumulate unit, only passing a sum from a previous operation through as output across the plurality of single instruction multiple data lanes (Rubanovich, [0086] outgoing sum is passed).
9. As to claim 4, the combination of Nurvitadhi and Rubanovich discloses read gate logic components configured to receive a zero tile, wherein a logic function of the read gate logic components causes the read logic component to prevent a read operation from a register file corresponding to a single instruction multiple data lane of the plurality of single instruction multiple data lanes (Nurvitadhi [0335]-[0337]).
10. As to claim 5, the combination of Nurvitadhi and Rubanovich discloses pipeline skip logic components configured to receive a zero tile, wherein a logic function of the pipeline skip logic components allows input data across all processing tiles in a row or a column to bypass the multiply and accumulate units pipeline, thus improving performance (Nurvitadhi [0061] and [0234]-[0235] skip logic).
11. As to claim 6, the combination of Nurvitadhi and Rubanovich discloses wherein the apparatus is configured to switch off a processing thread in response to a tile data structure comprised entirely of zero tiles (Rubanovich [0399]).
12. As to claim 18, Nurvitadhi discloses a computing system for manipulating tile data structures (abstract), the computer structure comprising:
one or more computer processors ([0064] one or more processors);
one or more computer readable storage devices ([0070] data storage device); and
computer program instructions, the computer program instructions being stored on the one or more computer readable storage devices for execution by the one or more computer processors to perform one or more operations ([0066] process instructions) comprising:
generate a weight-based data structure based on zero weights within the data structure, wherein the weight-based data structure is a matrix comprised of weights associated with a deep learning network ([0199], [0208]-[0210] weight based, [0178]-[0179] matrix, [0197] deep learning);
generate a plurality of empty tile index vectors ([0233]-[0236]; and
generate a data processing program for the data structure, based at least in part on the plurality of tiles and a parallel processing unit ([0107]-[0110]);
execute the processing program on the parallel processing unit, wherein the parallel processing unit receives at least one of the empty tile index vectors that causes the parallel processing unit to switch off a component in a multiply and accumulate unit ([0334] and [0345]).
Nurvitadhi does not disclose zero-tiles. However, Rubanovich discloses zero-tiles and a zero-tile format data structure ([0074]-[0077] and [0158] zero tiles.
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the claimed invention to modify the teachings of Nurvitadhi by implementing the zero-tiles as in Rubanovich, for the benefit of improving power and performance of processor hardware in a machine learning context, as this would reduce the power consumption of the instructions (Rubanovich [0005]).
13. As to claim 19, the combination of Nurvitadhi and Rubanovich discloses wherein the parallel processing unit is comprised of a plurality of processing threads with single instruction multiple data lanes and wherein the plurality of tiles is a data structure with columns corresponding to a number of single instruction multiple data lanes (Nurvitadhi [0109]-[0112] SIMD processing).
14. As to claim 20, the combination of Nurvitadhi and Rubanovich discloses wherein the component in the multiply and accumulate unit is a logic gate ([0279 logic gates).
Allowable Subject Matter
Claim 3 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior art of record teaches apparatus for processing zero-tiles in deep learning models as in claim 1. However, the prior art of record does not teach or suggest at least data gate logic components configured to receive a zero tile, wherein a logic function of the data gate logic components prevents toggling of inputs to the multiply and accumulate units, thus saving power and pass through a sum and an activation from a previous operation as output across at least one of the plurality of single instruction multiple data lanes, of the plurality of single instruction multiple data lanes as in claim 3.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHAEL D YAARY whose telephone number is (571)270-1249. The examiner can normally be reached Mon-Fri 9-5:30.
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/MICHAEL D. YAARY/ Primary Examiner, Art Unit 2151
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