DETAILED ACTION
This office action is in response to the request for continuation filed on December 18, 2025 in application 18/448,406.
Claims 1-20 are presented for examination. Claims 1, 8, 17, 19 are amended.
35 USC 112 for claim 8 is withdrawn based on amendment
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed December 18, 2025 have been fully considered but they are not persuasive.
In regard to the 35 USC 112f, applicant have not provided any response.
In regard to the 35 USC 101 rejections, the limitation of “performing an action for the memory device” is still broad as to what action is being performed and whether that action would overcome the 35 USC 101 rejections. A controller controlling the amount of data for a particular region of memory does not provide significantly more than a practical application of a generic controller.
In regard to the 35 USC 102/103 rejections, applicant’s arguments with respect to claim(s) 1-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
Claim 1 is objected to because of the following informalities: claim 1 recited “stored stores” where a coma between stored and stores is advised. Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims 19-20 in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof. The instant specification states “means for monitoring”, “means for determining” and “means for performing” are implemented by logic hardware of one or more non-volatile memory such as a device controller 126 (para. 31).
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-18 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more. The claim recites a controller configured to monitor, determine and perform a subsequent action.
The limitation of determine, store and perform a subsequent action, as drafted, is a process that, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components. That is, other than reciting “a controller” and “non-volatile memory”, nothing in the claim element precludes the step from practically being performed in the mind. For example, but for the “a controller” and “non-volatile memory” language, monitor, determine and perform a subsequent action in the context of this claim encompasses monitoring and determine the access frequencies. If a claim limitation, under its broadest reasonable interpretation, covers performance of the limitation in the mind but for the recitation of generic computer components, then it falls within the “Mental Processes” grouping of abstract ideas. Accordingly, the claim recites an abstract idea.
This judicial exception is not integrated into a practical application. In particular, the claim only recites one additional element – in communication via a network connection. The “a controller” and “non-volatile memory” is recited at a high-level of generality (i.e., as a generic computer components). The claim is directed to an abstract idea.
The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception. As discussed above with respect to integration of the abstract idea into a practical application, the additional element of using a network connection to perform the communication between devices amounts to no more than mere instructions to apply the exception using a generic network component. Mere instructions to apply an exception using a generic network component cannot provide an inventive concept. Furthermore, the courts have recognized as well-understood, routine, conventional activity (MPEP 2106.05(d)(ii)) for i) receiving or transmitting data over a network (Symantec, 838 F.3d) and ii) perform repetitive calculations … recomputing or readjusting alarm limit values (Flook, 437 U.S. at 594). Therefore, the claims are not patent eligible.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-6, 15, 17 and 19 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bachmutsky et al. (US 2022/0222010).
In regard to claim 1, Bachmutsky et al. teach a data storage device comprising: a controller configured to:
determine, based at least in part, on one or more characteristics associated with received data, an access frequency of the received data (requesting memory from the pool can pass a hint as to the type of memory required … interleaved mode, para. 26);
store the received data in one or more regions of a memory device, wherein at least one region of the one or more regions of the memory device in which the received data is stored stores data having a first access frequency and data having a second access frequency (the switch can use these hints to allocate memory from the memory region that could be disaggregated across multiple memory pools … the threshold size is configurable and will vary depending on the level of interleaving applied for a given memory region, para. 26);
determine an interleave metric of the at least one region of the memory device, the interleave metric indicating: a first amount of data stored in the at least one region of the memory device having the first access frequencies; and a second amount of data stored in the at least one region of the memory device having the second access frequency (memory pools 310, 320 to perform memory interleaving supporting different bandwidth levels, para. 38, fig. 3, 340); and perform a subsequent action for the memory device based, at least in part, on the determined interleave metric (the switch provides a new interface to process Reads and Writes for a particular memory range … the logic is responsible for creating the corresponding unicast or multicast messages, para. 47).
In regard to claim 2, Bachmutsky et al. teach the data storage device of claim 1, wherein the subsequent action comprises displaying, on an electronic display device, a graphical representation of the determined interleave metric for the at least one region (switch also maintains an interleaving configuration table 438, para. 50, fig. 4).
In regard to claim 4, Bachmutsky et al. teach the data storage device of claim 1, wherein the controller is further configured to predict a subsequent interleave metric based, at least in part, on the determined interleave metric (creating a new interleaving class in block 510, the logic select the right amount of endpoints required to meet the request requirements … the selection can be based on the prediction of the expected load, para. 54-57).
In regard to claim 5, Bachmutsky et al. teach the data storage device of claim 4, wherein the subsequent action that is performed on the at least one region of the memory device is based, at least in part, on the predicted subsequent interleave metric (creating a new interleaving class in block 510, the logic select the right amount of endpoints required to meet the request requirements … the selection can be based on the prediction of the expected load, para. 54-57).
In regard to claim 6, Bachmutsky et al. teach the data storage device of claim 5, wherein the subsequent action comprises opening one or more regions of the memory device for writing, the one or more regions being selected based, at least in part, on the predicted subsequent interleave metric (there could be an abundance of memory in the other memory pools that has been allocated but may not be actively used during spike … seasonal or temporally predictable events, para. 24).
In regard to claim 15, Bachmutsky et al. teach the data storage device of claim 1, wherein the controller comprises executable code executing on a computing device and the memory device stores metadata in a location external to the memory device and is accessible to the controller, the metadata enabling the controller to monitor different access frequencies and determine interleave metrics (use transparently smart memory interleaving methods, para. 25, allocation interleaving logic and interleaving configuration table responsible to process reads and writes for a particular memory range, para. 47-50).
In regard to claim 16, Bachmutsky et al. teach the data storage device of claim 1, wherein the controller comprises a device controller disposed on the memory device (switch, fig. 1, 122).
In regard to claim 17, Bachmutsky et al. teach a method comprising:
receiving data (processing new memory allocation requests, para. 43);
store the received data in one or more regions of a memory device, wherein at least one region of the one or more regions of the memory device stores data having a first classification and second data having a second classification (the switch can use these hints to allocate memory from the memory region that could be disaggregated across multiple memory pools … the threshold size is configurable and will vary depending on the level of interleaving applied for a given memory region, para. 26);
tracking an access frequency of data stored in each of the one or more regions of the memory device, the access frequency being based, at least in part, on the first classification and the second classification (network monitoring and QoS logic, para. 59);
determine a ratio of interleaved data of each of the one or more regions of the memory device based, at least in part, on the access frequency (memory pools 310, 320 to perform memory interleaving supporting different bandwidth levels, para. 38, fig. 3, 340); and
performing an action for the memory device based, at least in part, on the determined ratio of interleaved data (the switch provides a new interface to process Reads and Writes for a particular memory range … the logic is responsible for creating the corresponding unicast or multicast messages, para. 47).
In regard to claim 19, Tanaka et al. teach an apparatus comprising:
means for determining an access frequency of received data (requesting memory from the pool can pass a hint as to the type of memory required … interleaved mode, para. 26);
means for storing the received data in one or more regions of a data storage means, wherein at least one region of the one or more regions of the data storage means stores data having a first access frequency and data having a second access frequency (the switch can use these hints to allocate memory from the memory region that could be disaggregated across multiple memory pools … the threshold size is configurable and will vary depending on the level of interleaving applied for a given memory region, para. 26);
means for determining an interleave metric of the at least one region of the data storage means, the interleave metric indicating: a first amount of data stored in the at least one region of the data storage means having the first access frequency; and a second amount of data stored in the at least one region of the data storage means having the second access frequency (memory pools 310, 320 to perform memory interleaving supporting different bandwidth levels, para. 38, fig. 3, 340); and means for performing a subsequent action for the data storage means, at least in part, on the determined interleave metric (the switch provides a new interface to process Reads and Writes for a particular memory range … the logic is responsible for creating the corresponding unicast or multicast messages, para. 47).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 3, 7, 18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bachmutsky et al. (US 2022/0222010) in further view of Tanaka et al. (US 2008/0071939).
In regard to claim 3, Bachmutsky et al. does not explicitly teach but Tanaka et al. teach the data storage device of claim 2, wherein the graphical representation comprises a histogram of the different access frequencies indexed by the at least one region (display histogram by reading frequency distribution of measured memory latency, fig. 3, step 3, para. 93).
It would have been obvious to modify the device of Bachmutsky et al. by adding Tanaka et al. monitoring and reconfiguring computer system. A person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make the modification because it would aid in providing a performance display (para. 85).
In regard to claim 7, Bachmutsky et al. does not explicitly teach but Tanaka et al. teach the data storage device of claim 4, wherein the subsequent action comprises postponing performance of a storage capacity recovery operation for one or more regions of the memory device (setting change may be made through manual tuning by the system administrator, or may be completed automatically by preparing different setting patterns for different hardware configurations, para. 188).
It would have been obvious to modify the device of Bachmutsky et al. by adding Tanaka et al. monitoring and reconfiguring computer system. A person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make the modification because it would aid in implementing changes accordance with the configuration suggestions (para. 184-189).
In regard to claim 18, Bachmutsky et al. does not explicitly teach but Tanaka et al. teach the method of claim 17, wherein the action comprises displaying, on an electronic display device, a graphical representation of the determined ratio of interleaved data for each of the one or more regions of the memory device (display histogram by reading frequency distribution of measured memory latency, fig. 3, step 3, para. 93).
Refer to claim 3 for motivational statement.
In regard to claim 20, Bachmutsky et al. does not explicitly teach but Tanaka et al. teach the apparatus of claim 19, wherein the means for performing the subsequent action comprises means for displaying a graphical representation of the determined interleave metric for each of the at least one region (display histogram by reading frequency distribution of measured memory latency, fig. 3, step 3, para. 93).
Refer to claim 3 for motivational statement.
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Claims 8-14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka et al. (US 2008/0071939) in further view of Meeramohideen Mohamed et al. (US 2023/0393783).
In regard to claim 8, Bachmutsky et al. does not explicitly teach but Meeramohideen Mohamed et al. teach the data storage device of claim 4, wherein the subsequent action comprises:
selecting a first region of the memory device storing a single bit per memory cell in response to the predicted subsequent interleave metric satisfying a threshold (store relatively infrequently accessed data (cold data) in a relatively slower portion of memory, para. 32, heatmap, para. 54);
selecting a second region of the memory device storing multiple bits per cell in response to the predicted subsequent interleave metric failing to satisfy the threshold (storing relatively frequently accessed data (hot data) in a relatively fast portion of memory, para. 32, heatmap, para. 54); and
storing additional data in the selected region (each field of a register indicates a quantity of access operations associated with a respective set of addresses, para. 32).
It would have been obvious to modify the apparatus of Bachmutsky et al. by adding Meeramohideen Mohamed et al. access heatmap generation. A person of ordinary skill in the art before the effective filing date of the claimed invention would have been motivated to make the modification because it would aid in monitoring access operation occurrence at a memory device (para. 32).
In regard to claim 9, Bachmutsky et al. does not explicitly teach but Meeramohideen Mohamed et al. teach the data storage device of claim 4, wherein the subsequent action comprises:
retaining data stored in a region of the regions of the memory device storing a single bit per memory cell in response to the predicted subsequent interleave metric satisfying a threshold (store relatively infrequently accessed data (cold data) in a relatively slower portion of memory, para. 32, a page of data may be interleaved across multiple memory arrays … the results of a mapping function for each portion of an interleaved page, para. 50, heatmap, para. 54); and
copying back the data from the region storing a single bit per memory cell to a different region of the memory device storing multiple bits per cell in response to the predicted subsequent interleave metric failing to satisfy the threshold (storing relatively frequently accessed data (hot data) in a relatively fast portion of memory, para. 32, a page of data may be interleaved across multiple memory arrays … the results of a mapping function for each portion of an interleaved page, para. 50, heatmap, para. 54).
Refer to claim 8 for motivational statement.
In regard to claim 10, Bachmutsky et al. does not explicitly teach but Meeramohideen Mohamed et al. teach the data storage device of claim 1, wherein the subsequent action comprises selecting two or more regions of the memory device for merging in a storage capacity recovery operation based, at least in part, on the determined interleave metric (migrating data to improve matching between data characteristic with memory characteristics, para. 71).
Refer to claim 8 for motivational statement.
In regard to claim 11, Bachmutsky et al. does not explicitly teach but Meeramohideen Mohamed et al. teach the data storage device of claim 1, wherein the subsequent action comprises selecting one region of the memory device for a storage capacity recovery operation based, at least in part, on the determined interleave metric (divide a range of continuous addresses into one or more regions, para. 72).
Refer to claim 8 for motivational statement.
In regard to claim 12, Bachmutsky et al. does not explicitly teach but Meeramohideen Mohamed et al. teach the data storage device of claim 11, wherein the interleave metric for the selected one region is an outlier from other interleave metrics associated with other regions of the memory device (a page of data may be interleaved across multiple memory arrays and the results of a mapping function for each portion of an interleaved page, para. 50).
Refer to claim 8 for motivational statement.
In regard to claim 13, Bachmutsky et al. does not explicitly teach but Meeramohideen Mohamed et al. teach the data storage device of claim 1, wherein the one or more characteristics of the received data are determined by a file system and wherein the access frequency is based, at least in part, on one or more log files of the file system (store relatively infrequently accessed data (cold data) in a relatively slower portion of memory and storing relatively frequently accessed data (hot data) in a relatively fast portion of memory, para. 32).
Refer to claim 8 for motivational statement.
In regard to claim 14, Bachmutsky et al. does not explicitly teach but Meeramohideen Mohamed et al. teach the data storage device of claim 1, wherein the access frequency is an update frequency at which the data is invalidated by subsequent write data (transfer data associated with the addresses based on the access counts, para. 75).
Refer to claim 8 for motivational statement.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See PTO 892.
Duluk, Jr. et al. (US 12,498,979 memory interleave factor
Barmawer et al. (US 12,287,734) interleave size and quantity
Jordan et al. (US 12,079,124) interleave factor associated with memory region
Berke (US 12,001,332) interleave runtime monitoring
Sharma et al. (US 2023/040923) memory geometry (interleave)
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Hornung et al. (US 7,818,508) access latency, hot spots and interleave capabilities.
Keller, Jr. et al. (US 8,010,764) interleave control scheme
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Zhuo et al. (US 2022/0137860) interleave and merged result
Luan et al. (US 2017/0031606) data bank divided into regions
Sah et al. (US 7047374) interleave
Link et al. (US 2005/0036518) merge controller
Cook (US 2004/0222379) construct a result histogram
Wasserman et al. (US 2003/0043158) memory bank interleave with histogram op
Emberling (US 2003/0038810) memory (ready, precharging, non-ready)
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/Loan L.T. Truong/Primary Examiner, Art Unit 2114 HYPERLINK "mailto:Loan.truong@uspto.gov" Loan.truong@uspto.gov