DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 1- 9 and 11 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Lai et al (US 2023/0062140 A1) . Regarding claim 1, Lai et al discloses a n apparatus (Figure 1B) , comprising: a first transistor (Figure 1B, reference 104) formed in a transistor region (Figure 1B, surface of reference s 102 and 104) of an integrated circuit cell structure (Figure 1B, reference 100B) , the first transistor (Figure 1B, reference 104) having a first active region (Figure 1B, reference 106) , a first gate (Figure 1B, reference 110A) , and first source/drain regions (Figure 1B, reference 130A) in the transistor region ( Figure 1B, surface of reference s 102 and 104 ) ; a second transistor (Figure 1B, reference 102) formed in the transistor region ( Figure 1B, surface of reference 10 2) , the second transistor (Figure 1B, reference 102) having a second active region (Figure 1B, reference 108) , a second gate (Figure 1B, reference 110B) , and second source/drain regions (Figure 1B, reference 130B) in the transistor region ( Figure 1B, surface of references 102 and 104 ) , wherein at least a portion of the second active region (Figure 1B, reference 108) is positioned below the first active region (Figure 1B, reference 106) in a vertical dimension perpendicular to the transistor region ( Figure 1B, surface of references 102 and 104 ) ; a first metal layer (Figure 1B, reference 105B) located above the transistor region ( Figure 1B, surface of references 102 and 104 ) in the vertical dimension, wherein the first metal layer (Figure 1B, reference 105B) includes first signal routing (Figure 1B, reference 107B) connected to the first transistor ( Figure 1B, reference 104; paragraph 0030) ; and a second metal layer (Figure 1B, reference 116) located below the transistor region ( Figure 1B, surface of references 102 and 104 ) in the vertical dimension, wherein the second metal layer ( Figure 1B, reference 116 ) includes second signal routing (Figure 1B, reference 134) connected to the second transistor (Figure 1B, reference 102; paragraph 0041) , and wherein the second metal layer (Figure 1B, reference 116) includes power routing (Figure 1B, reference 132B) connected to the second transistor ( Figure 1B, reference 102; pa r agraph 0041) . Regarding claim 2 , Lai et al discloses wherein the first signal routing (Figure 1B, reference 107B) in the first metal layer (Figure 1B, reference 105B) is connected to a signal input (Figure 1B, reference 109D) of the first gate (Figure 1B, reference 110A) in the first transistor (Figure 1B, reference 104). Regarding claim 3 , Lai et al discloses wherein the second signal routing ( Figure 1B, reference 134 ) in the second metal layer (Figure 1B, reference 116) is connected to at least one second source/drain region (Figure 1B, reference 130A) in the second transistor (Figure 1B, reference 102). Regarding claim 4 , Lai et al discloses wherein the power rout routing ( Figure 1B, reference 132B ) in the second metal layer (Figure 1B, reference 116) is connected to at least one second source/drain region (Figure 1B, reference 130B in the second transistor (Figure 1B, reference 102) . Regarding claim 5 , Lai et al discloses wherein a portion of the first active region (Figure 1B, surface of reference 104) forming the first gate (Figure 1B, reference 110 A ) is in contact with a portion of the second active region (Figure 1B, reference surface of reference 102) forming the second gate ( Figure 1B, reference 110 B) . Regarding claim 6 , Lai et al discloses wherein the first signal routing ( Figure 1B, reference 107B ) in the first metal layer ( Figure 1B, reference 105B ) is connected to a signal input (Figure 1B, reference 109D) of the first gate ( Figure 1B, reference 110A ) in the first transistor (Figure 1B, reference 104) . Regarding claim 7 , Lai et al discloses wherein a portion of the first active region (Figure 1B, surface of reference 104) forming the first gate (Figure 1B, reference 110A) is separated (Figure 1B, references 131) from a portion of the second active region (Figure 1B, surface of reference 102) forming the second gate (Figure 1B, reference 110B) . Regarding claim 8 , Lai et al discloses wherein the first signal routing ( Figure 1B, reference 107B ) in the first metal layer ( Figure 1B, reference 105B ) is connected to a signal input ( Figure 1B, reference 109D ) of the first gate ( Figure 1B, reference 110A ) in the first transistor ( Figure 1B, reference 104 ) , and wherein the second signal routing (Figure 1B, reference 134) in the second metal layer (Figure 1B, reference 116) is connected to a signal input ( Figure 1B, reference 190D ) of the second gate ( Figure 1B, reference 110B ) in the second transistor ( Figure 1B, reference 102 ) . Regarding claim 9 , Lai et al discloses wherein the first metal layer ( Figure 1B, reference 105B ) includes power routing (Figure 1B, reference 107B) connected to the first transistor (Figure 1B, reference 104) . Regarding claim 1 1 , Lai et al discloses wherein the first transistor (Figure 1B, reference 104; PMOS) and the second transistor (Figure 1B, reference 102; NMOS) are complementary transistor types (paragraph 0033). Allowable Subject Matter Claims 10 and 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art does not disclose nor fairly suggest an apparatus, comprising: a via connected to the power or signal routing in the second metal layer and positioned outside the first active region and the second active region in a horizontal dimension perpendicular to the vertical dimension, wherein the via connects the power or signal routing in the second metal layer to power or signal routing in the first metal layer; and a contact via coupled between the power or signal routing in the first metal layer and at least one first source/drain region in the first transistor such that the power or signal routing in the second metal layer is connected to the first transistor (claim 10) and a via connected to the power or signal routing in the second metal layer and positioned outside the second active region in a horizontal dimension perpendicular to the vertical dimension; and a source/drain contact connected to at least one second source/drain region, wherein the source/drain contact is positioned above the second active region in the vertical dimension, and wherein at least a portion of the source/drain contact extends outside the second active region in the horizontal dimension such that the source/drain contact connects to the via and the via connects the power or signal routing in the second metal layer to the at least one second source/drain region (claim 12) further incorporated into independent claim 1 and in the context of its recited apparatus, along with its depending claims . Claims 13-20 are allowed over the prior art of record. The following is an examiner’s statement of reasons for allowance: The prior art does not disclose nor fairly suggest apparatuses, comprising: a plurality of via pillars positioned on a perimeter of the integrated circuit cell structure, the via pillars extending through the transistor region in the vertical dimension between the first metal layer and the second metal layer, wherein at least some of the via pillars are positioned on opposing sides of the first active region and the second active region, and wherein alternative via pillars on one side alternate belonging to the at least one integrated circuit cell structure and a neighboring integrated circuit cell structure (claim 13) and a first metal layer located above the transistor region in the vertical dimension, wherein the first metal layer includes: a first set of signal routing paths; and a first set of power routing paths; a second metal layer located below the transistor region in the vertical dimension, wherein the second metal layer includes: a second set of signal routing paths; and a second set of power routing paths; at least one gate contact formed in the transistor region, wherein the at least one gate contact provides a connection between a signal input for one of the first gate or the second gate and a signal routing path from one of the first set of signal routing paths or the second set of signal routing paths; at least one source power contact formed in the transistor region, wherein the at least one source power contact provides a connection between a source region from one of the first source regions or the second source regions and a power routing path from one of the first set of power routing paths or the second set of power routing paths; and at least one drain power contact formed in the transistor region, wherein the at least one drain power contact provides a connection between a drain region from one of the first drain regions or the second drain regions and a power routing path from one of the first set of power routing paths or the second set of power routing paths (claim 20) as described in the independent claims and in the context of their recited apparatuses, along with their depending claims . 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /MONICA D HARRISON/ Primary Examiner, Art Unit 2815 mdh March 26, 2026