DETAILED ACTION
Status of Claims
This action is in reply to the communication filed on 12/03/2025.
Claims 1-3, 7, 9-11, and 15 have been amended.
Claims 5, 6, 8, 13, 14, and 16-22 have been cancelled.
Claims 23-30 have been added.
Claims 1-4, 7, 9-12, 15 and 23-30 are currently pending and have been examined.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 12/03/2025 has been entered.
Response to Arguments
Applicant’s arguments filed 12/03/2025 have been considered but are not persuasive and/or moot in view of the new grounds of rejection as described below.
On pg. 11, -12 of the Remarks, Applicant essentially argues:
“Thus, claim 1 now recites that when the first processor task is paused in response to the first resource being unavailable, the processor can start a second processor task using a second shared resource. When the first shared resource becomes free, the spinlock circuit notifies the
task manager circuit, but the task manager circuit defers from sending a request for the now available first shared resource due to the processor performing the second processor task. Support for these features can be found at least in paragraphs [0095]-[0097]…With respect to the references cited in the instant rejection, Isaacson does not appear to teach or suggest these features. For instance, Isaacson discloses that a processor may request a resource with a "lock r" request. See Isaacson, page 37. If the request is unsuccessful (understood to mean that the requested resource is not available), the task is blocked until the source becomes available. The resource being unavailable is indicated by the resource module interface (see Figure 4-1) receiving an "in Use" signal indicating that the resource is locked by another task. See id. at pages 39-40, 43.
If the resource becomes available (e.g., by another processor that has finished using it sending a "release" signal), this is indicated by the resource module interface communicating the "free" signal to the resource nodes. See id. at pages 43-44. If the resource becomes free to acquire, the lock is immediately granted to the task previously blocked. See id. at 45. However, Isaacson fails to teach that a processor may choose not to acquire the requested resource if it has started another task that is still ongoing.”
Applicant’s arguments are not commensurate with the scope of the claim limitations. Claim 1 recites in response to the fourth notice, not sending from the task manager circuit to the spinlock circuit a fifth notice indicating the processor is requesting use of the first shared resource if the second processor task is still being performed; not sending a request for a shared resource is not equivalent to preventing a shared resource from being acquired as argued. Issacson, In response to the fourth notice that the first resource has become available to the first task arriving while a higher priority second task is being performed, makes the same ‘choice’ as described in Applicant’s Specification ¶0095-0097, i.e. continue running the higher priority second task, and does not send a fifth notice indicating the processor is requesting use of the first shared resource. Regarding the sending the fifth notice when the first task resumes, and the distinction between Isaacson’s lock successor handling and that described in the embodiment in AppSpec ¶0096-0097, FIG. 3A-3B, Examiner refers to the rejections to claims 23 and 27 in view of Dice.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-4, 7, 9-12, 15, 24-26, and 28-30 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Isaacson (“Hardware Support for a Configurable Architecture for Real-Time Embedded Systems on a Programmable Chip”, 2007).
Claim 1:
Isaacson discloses the limitations as shown in the following rejections:
A method comprising: beginning, using a processor, a first processor task that uses a first shared resource (pg. 3-5; pg. 8-9, § 2.1).
sending a first notice (resource control instruction) from a task manager circuit (scheduler + Real Time Processor (RTP) Interface) of the processor to a spinlock circuit (Task-Resource Matrix (TRM)), wherein the spinlock circuit is configured to determine and communicate availability of a plurality of shared resources that includes the first shared resource, and wherein the first notice indicates to the spinlock circuit that the processor is requesting use of the first shared resource; (pg. 4; pg. 5, Fig. 1-1; pg. 10, para. 2; pg. 37, para. 1-2) disclosing tasks request use of resources by executing “resource-specific control instructions in this new architecture include…lock r: Attempt to reserve system resource r.” (pg. 37) which causes the RTP interface to send a request signal to the TRM.
using the spinlock circuit to determine whether the first shared resource is available (free/available or inUse) in response to determining the first shared resource is unavailable (inUse), sending a second notice from the spinlock circuit to the task manager circuit, the second notice indicating the first shared resource is unavailable (pg. 38-40; pg. 43) disclosing in response to the request the TRM determines whether the resource is free/available or inUse, and signals that the task is blocked from resource when it is not available.
in response to receiving the second notice, pausing (blocking) the first processor task on the processor (pg. 4, para. 3; pg. 38, last para; pg. 44) last para: “If the resource lock is granted, the task may continue executing and use the resource. If the lock is not granted, the TRM signals the scheduler to block that task from executing” (pg. 38, last para).
receiving, at the spinlock circuit, a third notice (release signal) indicating the first shared resource has become available (freed/released); sending a fourth notice from the spinlock circuit to the task manager circuit, the fourth notice (grant/ready) indicating the first resource has become available; (pg. 38, para. 1; pg. 43-45), “A release signal releases the lock held by the task by resetting the grant flag” (pg. 45, para. 1); “The ready signal alerts the task module and subsequently the scheduler that there are no outstanding resource requests that block execution” (pg. 43, para. 1).
after the first processor task is paused, using the processor to begin a second processor task (highest priority ready task) associated with a second shared resource…in response to the fourth notice, not sending from the task manager circuit to the spinlock circuit a fifth notice indicating the processor is requesting use of the first shared resource if the second processor task is still being performed (pg. 25-27; pg. 29, para. 2; pg. 33; pg. 47, and 49) disclosing each arbitration cycle the scheduler identifies which of the ready tasks has the highest priority and “[t]he ready task with the highest priority is granted exclusive rights to the processor”. Accordingly, if the processor is running a task (if the second processor task is still being performed) with a higher priority than a task (first task) made ready due to a resource release then it will continue running that task, and thus does not send a fifth notice indicating the processor is requesting use of the first shared resource (this limitation is discussed further below in view of Dice at claim 23).
Claims 2-4:
Isaacson discloses the limitations as shown in the rejections above. Isaacson further discloses the first processor task includes a first operation; the pausing (blocking) of the first processor task occurs at the first operation...wherein the resuming of the first processor task include changing a program counter of the processor to an address associated with the first operation in at least pg. 12-14, § 2.3-2.3.1; pg. 47; pg. 37-39, § 4; pg. 38, last para. – pg. 39, first para.
Claim 7:
Isaacson discloses the limitations as shown in the rejections above. Isaacson further discloses the processor is a first processor; the device further comprises a second processor; and the spinlock circuit is configured to determine whether the first shared resource is available based on whether the first shared resource is currently being used by the second processor (pg. 3; pg. 5; and pg. 42).
Claim 9:
Isaacson discloses the limitations as shown in the following rejections:
A device comprising: a processor; a task manager circuit (scheduler + Real Time Processor (RTP) Interface) coupled to the processor; and a [spinlock circuit] (Task-Resource Matrix (TRM)) coupled to the task manager circuit (pg. 3-5; and pg. 11, Fig. 2-1).
the processor is configured to begin a first processor task associated with a first shared resource (pg. 8-9, § 2.1).
the task manager circuit is configured to send a first notice (resource control instruction) to the spinlock circuit indicating the processor is requesting use of the first shared resource; the spinlock circuit is configured to determine and communicate availability of a plurality of shared resources that includes the first shared resource and, in response to receiving the first notice, to send to the task manager circuit a second notice indicating the first shared resource is unavailable (pg. 4; pg. 5, Fig. 1-1; pg. 10, para. 2; pg. 37, para. 1-2) disclosing tasks request use of resources by executing “resource-specific control instructions in this new architecture include…lock r: Attempt to reserve system resource r.” (pg. 37) which causes the RTP interface to send a request signal to the TRM, which in turn determines whether the resource is free/available or inUse, and signals that the task is blocked from resource when it is not available (pg. 38-40; pg. 43; pg. 5, Fig. 1-1).
the task manager circuit is further configured to, in response to receiving the second notice, cause the processor to pause (block) the first processor task (pg. 4, para. 3; pg. 38, last para; pg. 44) last para: “If the resource lock is granted, the task may continue executing and use the resource. If the lock is not granted, the TRM signals the scheduler to block that task from executing” (pg. 38, last para).
the spinlock circuit is further configured to…receive a third notice (release signal) indicating the first shared resource has become available (freed/released) and send to the task manager circuit a fourth notice (grant/ready) indicating the first shared resource has become available; (pg. 38, para. 1; pg. 43-45), “A release signal releases the lock held by the task by resetting the grant flag” (pg. 45, para. 1); “The ready signal alerts the task module and subsequently the scheduler that there are no outstanding resource requests that block execution” (pg. 43, para. 1).
the processor is further configured to, after pausing the first processor task, begin a second processor task (highest priority ready task) associated with a second shared resource…the task manager circuit is further configured to not send a fifth notice requesting use of the first shared resource to the spinlock circuit in response to receiving the fourth notice if the processor is still performing the second processor task using the second shared resource (pg. 25-27; pg. 29, para. 2; pg. 33; pg. 47, and 49) disclosing each arbitration cycle the scheduler identifies which of the ready tasks has the highest priority and “[t]he ready task with the highest priority is granted exclusive rights to the processor”. Accordingly, if the processor is running a task (if the second processor task is still being performed) with a higher priority than a task (first task) made ready due to a resource release then it will continue running that task, and thus does not send a fifth notice indicating the processor is requesting use of the first shared resource (this limitation is discussed further below in view of Dice at claim 27).
Claims 10-12:
Isaacson discloses the limitations as shown in the rejections above. Isaacson further discloses the limitations of claims 10-12 under the same rationale described in the rejection(s) to claims 2-4 above.
Claims 15:
Isaacson discloses the limitations as shown in the rejections above. Isaacson further discloses the limitations of claim 15 under the same rationale described in the rejection(s) to claim 7 above.
Claims 24 and 28:
Isaacson discloses the limitations as shown in the rejections above. Isaacson further discloses wherein the second processor task has a higher priority level than the first processor task (pg. 25-27; pg. 29, para. 2; pg. 33; pg. 47, and 49).
Claims 25-26 and 29-30:
Isaacson discloses the limitations as shown in the rejections above. Regarding the limitations of claims 25-26 and 29-30 reciting wherein the processor is a first processor, and the third notice is sent to the spinlock circuit by a task manager circuit of a second processor that was performing a third processor task using the first shared resource when the first shared resource was determined to be unavailable responsive to the first notice…wherein the third notice is received after the processor begins the second processor task; as shown in the rejections above, Isaacson discloses all the individual actions recited in the limitations. Isaacson further discloses (pg. 3-5) the system is a multi-processor system that supports up to 16 processors with up to 16 tasks per processor, and the TRM controls sharing of resources between both tasks executing on the same processor and tasks on different processors “Peripherals that can be shared by two or more tasks, whether they are on a single processor or on different processors, need to be synchronized among the competing tasks. This is done using system “resources” in this architecture.” While Isaacson does not explicitly describe the specific sequence of task activations and resource releases between tasks on different processors recited in the claims, the particular sequence involving three tasks on two processors (i.e. [Processor2 – Task3 (P2-T3): Lock R1] -> [P1-T1: TryLock R1] -> [P1-T2 Run] -> [P2-T3 Release R1] represents a species that a person of ordinary skill in the art reading Isaacson would “at once envisage” being performed on Isaacson’s multiprocessor system; “a reference may still anticipate if that reference teaches that the disclosed components or functionalities may be combined and one of skill in the art would be able to implement the combination.” Blue Calypso, LLC v. Groupon, Inc., 815 F.3d 1331, 1344 (Fed. Cir. 2016) (citing Kennametal, Inc. v. Ingersoll Cutting Tool Co., 780 F.3d 1376, 1381, 1383 (Fed. Cir. 2015) (“a reference can anticipate a claim even if it ‘d[oes] not expressly spell out’ all the limitations arranged or combined as in the claim, if a person of skill in the art, reading the reference, would ‘at once envisage’ the claimed arrangement or combination”). See MPEP 2131.02; 2123.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 23 and 27 are rejected under 35 U.S.C. 103 as being unpatentable over Isaacson in view of Dice (“Implementing Fast Java Monitors with Relaxed-Locks”, 2001).
Claims 23 and 27:
Isaacson discloses the limitations as shown in the rejections above. Issacson further discloses ((pg. 25-27; pg. 29, para. 2; pg. 33; pg. 47) in response to receiving the signal readying the task (first task) that whose resource request was blocked and determining all higher priority tasks (e.g. second processor task) have completed (or are not ready), resuming the first processor task on the first processor. But Isaacson does not disclose sending the fifth notice [requesting use of the first shared resource] from the task manager circuit to the spinlock circuit because the TRM (pg. 43-44), in response to a locked resource being freed, hands-off ownership to the waiting task and notifies the scheduler (task manager) that the task’s lock request has been granted, which obviates the need to re-issue the request for the resource when the task resumes.
Dice, however, describes various alternative implementations of locking protocols such as different “policies used to activate a successor thread when a thread unlocks an object” (pg. 8-9, § 3.3) including a “directed handoff” embodiment analogous to Isaacson’s implementation: “In directed handoff the unlocking thread explicitly picks a successor from the list of blocked threads, marks that thread as the owner of the object and then wakes it. The distinguished successor, by virtue of waking, knows that it owns the object” and further discloses a “competitive handoff” embodiment that teaches the limitations of claims 23 and 27: “In competitive handoff, when a thread unlocks an object, it marks the object as available and then makes a potential successor thread (sometimes called the heir apparent) ready. The successor, upon waking up, must compete for the object like other threads.”; see also pg. 5, col. 2: “Consider a thread blocked trying to lock a monitor. After waking, the thread must recontend for a monitor…Waking up doesn’t imply ownership of a lock, but rather grants that thread an opportunity to compete for the lock. Blocking and waking threads is simply a way to avoid spinning.”
It would have been obvious to one of ordinary skill in the art at the time the invention was filed to modify Isaacson to employ Dice’s competitive handoff succession policy and make the waiting task (first task) ready, without granting the lock, upon the lock’s release and recontend/reattempt the resource lock request (fifth notice requesting use of the first shared resource) when it becomes the highest priority task and runs (resuming the first processor task on the first processor) as it represents the substitution of one known succession policy with a known alternative yielding predictable results (e.g. reduced HW logic complexity of the TRM and increased throughput in exchange for reduced fairness and determinism in relation to resource acquisition order and wait times) (Dice pg. 8-9, § 3.3).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure:
“Malthusian Locks”, US 20170039094 A1, and US 6735760 B1 are related to reference Dice cited above.
“Fuss, Futexes and Furwocks: Fast Userlevel Locking in Linux” discusses tradeoffs amongst different lock release and succession policies.
US 7047299 B1 is directed to a distributed locking protocol.
Any inquiry of a general nature or relating to the status of this application or concerning this communication or earlier communications from the Examiner should be directed to Paul Mills whose telephone number is 571-270-5482. The Examiner can normally be reached on Monday-Friday 11:00am-8:00pm. If attempts to reach the examiner by telephone are unsuccessful, the Examiner’s supervisor, April Blair can be reached at 571-270-1014.
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/P. M./
Paul Mills
01/06/2026
/APRIL Y BLAIR/Supervisory Patent Examiner, Art Unit 2196