DETAILED ACTION
This action is in response to the filing of 7-13-2026. Claims 1-16 are pending and have been considered below:
Claim Rejections - 35 USC § 101
35 U.S.C. 101 reads as follows:
Whoever invents or discovers any new and useful process, machine, manufacture, or composition of matter, or any new and useful improvement thereof, may obtain a patent therefor, subject to the conditions and requirements of this title.
Claims 1-16 are rejected under 35 U.S.C. 101 because the claimed invention is directed to an abstract idea without significantly more.
Step 1: Claims 1-16 represent method, system and medium type claims. Therefore claims 1-20 are directed to either a process, machine, manufacture or composition of matter.
Regarding claims 1 and 6:
2A Prong 1:
a conversion recognition learning operation of converting a spike timestep using the kernel computation and one or more activation functions; a PSP computation operation of computing a sum of postsynaptic potentials (PSPs) using the converted spike timestep;
As drafted, under the broadest reasonable interpretation, the claim covers mental processes (concepts performed in the human mind (including an observation, evaluation, judgment, opinion-a conversion recognition and computation of a sum can be mentally performed).
2A Prong 2: This judicial exception is not integrated into a practical application.
Additional elements:
a kernel generation operation of generating a kernel computation for a log computation;
and an SNN learning operation, by a spiking neural network (SNN) model, of training data using a membrane potential value depending on the sum.
(Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea - see MPEP 2106.05(f)).
a kernel generator configured to;
a conversion recognition learning unit configured to;
a PSP computation unit configured to;
and an SNN learning unit configured
(mere instructions to apply the exception using a generic computer component)
2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional elements:
a kernel generation operation of generating a kernel computation for a log computation;
and an SNN learning operation, by a spiking neural network (SNN) model, of training data using a membrane potential value depending on the sum.
(Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea - see MPEP 2106.05(f)).
a kernel generator configured to;
a conversion recognition learning unit configured to;
a PSP computation unit configured to;
and an SNN learning unit configured
(mere instructions to apply the exception using a generic computer component)
Regarding claims 2 and 7:
2A Prong 1:
calculating the sum of the postsynaptic potentials by performing an addition computation on the converted spike timestep and a weight;
classifying the calculated sum value into an integer part and a fractional part;
generating a look-up table of the fractional part;
and calculating the membrane potential value by performing a shift computation based on the look-up table and the integer part and performing an addition computation on the computed result.
As drafted, under the broadest reasonable interpretation, the claim covers mental processes (concepts performed in the human mind (including an observation, evaluation, judgment, opinion-a calculation, classification and generation of a table can be performed mentally).
2A Prong 2: This judicial exception is not integrated into a practical application.
Additional elements:
a PSP calculator configured to;
a classifier configured to;
a look-up table generator configured to;
membrane potential value calculator configured to;
(mere instructions to apply the exception using a generic computer component)
2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional elements:
a PSP calculator configured to;
a classifier configured to;
a look-up table generator configured to;
membrane potential value calculator configured to;
(mere instructions to apply the exception using a generic computer component)
Regarding claims 3 and 9:
2A Prong 1:
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1112
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As drafted, under the broadest reasonable interpretation, the claim covers mathematical concepts because they provide mathematical relationships, mathematical formulas or equations or mathematical calculations.
2A Prong 2: This judicial exception is not integrated into a practical application.
No Additional elements:
2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
No Additional elements:
Regarding claim 4:
2A Prong 1:
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230
1100
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As drafted, under the broadest reasonable interpretation, the claim covers mathematical concepts because they provide mathematical relationships, mathematical formulas or equations or mathematical calculations.
2A Prong 2: This judicial exception is not integrated into a practical application.
No Additional elements
2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
No Additional elements
Regarding claim 5:
2A Prong 1:
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218
1102
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As drafted, under the broadest reasonable interpretation, the claim covers mathematical concepts because they provide mathematical relationships, mathematical formulas or equations or mathematical calculations.
2A Prong 2: This judicial exception is not integrated into a practical application.
No Additional elements
2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
No Additional elements
Regarding claim 8:
2A Prong 1:
No additional abstract idea
2A Prong 2: This judicial exception is not integrated into a practical application.
Additional elements:
wherein the membrane potential value calculator further includes a barrel shifter configured to perform the shift computation.
(Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea - see MPEP 2106.05(f)).
2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional elements:
wherein the membrane potential value calculator further includes a barrel shifter configured to perform the shift computation.
(Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea - see MPEP 2106.05(f)).
Regarding claims 10 and 11:
2A Prong 1:
No additional abstract ideas
2A Prong 2: This judicial exception is not integrated into a practical application.
Additional elements:
wherein, in the conversion recognition learning operation, the one or more activation functions are applied to continuously convert the spike timestep in the sequential order of a ReLU function, followed by a Clip function, and then followed by a Time to First Spike (TTFS) function.
(Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea - see MPEP 2106.05(f)).
2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional elements:
wherein, in the conversion recognition learning operation, the one or more activation functions are applied to continuously convert the spike timestep in the sequential order of a ReLU function, followed by a Clip function, and then followed by a Time to First Spike (TTFS) function.
(Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea - see MPEP 2106.05(f)).
Regarding claim 12:
2A Prong 1:
No additional abstract ideas
2A Prong 2: This judicial exception is not integrated into a practical application.
Additional elements:
wherein the kernel computation uses a uniform time constant and a uniform spike delay time that are identical across all layers of the spiking neural network, and wherein a static random-access memory (SRAM) spike decoder is replaced by a look-up table for decoding spike timesteps in the spiking neural network computation.
(Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea - see MPEP 2106.05(f)).
2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional elements:
wherein the kernel computation uses a uniform time constant and a uniform spike delay time that are identical across all layers of the spiking neural network, and wherein a static random-access memory (SRAM) spike decoder is replaced by a look-up table for decoding spike timesteps in the spiking neural network computation.
(Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea - see MPEP 2106.05(f)).
Regarding claim 13:
2A Prong 1:
No additional abstract ideas
2A Prong 2: This judicial exception is not integrated into a practical application.
Additional elements:
wherein the kernel generator generates the kernel computation using a uniform time constant and a uniform spike delay time that are identical across all layers of the spiking neural network, and wherein a static random- access memory (SRAM) spike decoder of the PE array is replaced by a look-up table, and wherein the PE array is a log-domain PE array.
(Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea - see MPEP 2106.05(f)).
2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional elements:
wherein the kernel generator generates the kernel computation using a uniform time constant and a uniform spike delay time that are identical across all layers of the spiking neural network, and wherein a static random- access memory (SRAM) spike decoder of the PE array is replaced by a look-up table, and wherein the PE array is a log-domain PE array.
(Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea - see MPEP 2106.05(f)).
Regarding claim 14:
2A Prong 1:
No additional abstract ideas
2A Prong 2: This judicial exception is not integrated into a practical application.
Additional elements:
wherein the temporal coding is a coding scheme in which each neuron of the spiking neural network generates a single spike per computation, and a time at which the single spike is generated is inversely proportional to an input value of the neuron such that a greater input value produces an earlier spike generation time.
(Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea - see MPEP 2106.05(f)).
2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional elements:
wherein the temporal coding is a coding scheme in which each neuron of the spiking neural network generates a single spike per computation, and a time at which the single spike is generated is inversely proportional to an input value of the neuron such that a greater input value produces an earlier spike generation time.
(Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea - see MPEP 2106.05(f)).
Regarding claim 15:
2A Prong 1:
No additional abstract ideas
2A Prong 2: This judicial exception is not integrated into a practical application.
Additional elements:
wherein the processing device further comprises an input generator configured to receive input spikes and supply the input spikes to the PE array, the input generator comprising: an input buffer; and one or more minfind units configured to align and merge the input spikes, wherein the input generator supplies the aligned and merged input spikes to the PE array for accumulation as a membrane potential.
(Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea - see MPEP 2106.05(f)).
2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional elements:
wherein the processing device further comprises an input generator configured to receive input spikes and supply the input spikes to the PE array, the input generator comprising: an input buffer; and one or more minfind units configured to align and merge the input spikes, wherein the input generator supplies the aligned and merged input spikes to the PE array for accumulation as a membrane potential.
(Adding the words “apply it” (or an equivalent) with the judicial exception, or mere instructions to implement an abstract idea on a computer, or merely uses a computer as a tool to perform an abstract idea - see MPEP 2106.05(f)).
Regarding claim 16:
2A Prong 1:
No additional abstract ideas
2A Prong 2: This judicial exception is not integrated into a practical application.
Additional elements:
(an output processing device comprising a post-processing unit (PPU) and a spike encoder, the output processing device being configured to process an output of the PE array as output spikes, store the output spikes in an output buffer, and transmit spike information to a dynamic random-access memory (DRAM); and an output control device comprising a direct memory access (DMA) engine configured to manage data access with respect to an off-chip DRAM.
(mere instructions to apply the exception using a generic computer component)
2B: The claim does not include additional elements that are sufficient to amount to significantly more than the judicial exception.
Additional elements:
(an output processing device comprising a post-processing unit (PPU) and a spike encoder, the output processing device being configured to process an output of the PE array as output spikes, store the output spikes in an output buffer, and transmit spike information to a dynamic random-access memory (DRAM); and an output control device comprising a direct memory access (DMA) engine configured to manage data access with respect to an off-chip DRAM.
(mere instructions to apply the exception using a generic computer component)
Claim Interpretation
The claim interpretation has been withdrawn.
Claim Objections
Claims 3-5 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable over prior art if rewritten in independent form including all of the limitations of the base claim and any intervening claims. However, the claims are rejected under 101.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim 15 rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention. The claim recites a minfind unit, however the unit is only recited once within the specification. Further the functionality of aligning and merging utilizing this unit is not clearly disclosed (only a cursory statement that it is performed).
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1, 6 and 10-11 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Efficient Spiking Neural Networks With Logarithmic Temporal Coding, MING ZHANG ET AL. (“Zhang”), Pages 98156-98167 (1-12), 2-2020.
Claim 1: Zhang discloses a method of training a spiking neural network computation based on a temporal coding, the method comprising:
a kernel generation operation of generating a kernel computation for a log computation (Figure 2, Page 98159 (4); Section C; kernel generation);
a conversion recognition learning operation of converting a spike timestep using the kernel computation and one or more activation functions (Figure 2, Page 98159 (4), Section C; Kernel computation with activation function-RELU);
a PSP computation operation of computing a sum of postsynaptic potentials (PSPs) using the converted spike timestep (Figure 2, Page 98159 (4) Section C; PSP computation with time step);
and an SNN learning operation, by a spiking neural network (SNN) model, of training data using a membrane potential value depending on the sum (abstract, Figure 2, Page 98160(5) Section C and Page 98162(7) and Section E; SNN conversion provides training process to minimize loss, utilizing sum runs).
Claim 6 is similar in scope to claim 1 and therefore rejected under the same rationale.
Zhang also provides processing device for structure (Page 98162, IV PC with Nvidia GE forceGTX 1060 GPU)
Claim 10: Zhang discloses a method of claim 1, wherein, in the conversion recognition learning operation, the one or more activation functions are applied to continuously convert the spike timestep in the sequential order of a ReLU function (Page 98159 (4), Section C; ReLU), followed by a Clip function, and then followed by a Time to First Spike (TTFS) function(Page 98159 (4), Section C; ReLU), followed by a Clip function, and then followed by a Time to First Spike (TTFS) function.
Claim 11: Zhang discloses a spiking neural network computation learning system based on the temporal coding of claim 6, wherein the conversion recognition learning unit is configured to apply the one or more activation functions to continuously convert the spike timestep in the sequential order of a ReLU function
(Page 98159 (4), Section C; ReLU), followed by a Clip function, and then followed by a Time to First Spike (TTFS) function.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 2 and 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Efficient Spiking Neural Networks With Logarithmic Temporal Coding, MING ZHANG ET AL. (“Zhang”), Pages 98156-98167 (1-12), 2-2020 in view of Kim et al. (“Kim” 20210312269 A1) and Event-Driven Simulation Scheme for Spiking Neural Networks Using Lookup Tables to Characterize Neuronal Dynamics, Eduardo Ros et al. (“Ros”), 12-2006.
Claim 2: Zhang discloses a method of claim 1, wherein the PSP computation operation includes:
calculating the sum of the postsynaptic potentials by performing an addition computation on the converted spike timestep and a weight (Zhang: Figure 3; sum of spikes with time and weight; Page 98161 (6) Section E, computation provided and Page 98162 (7), Column 1, output activation value);
Zhang may not explicitly disclose classifying the calculated sum value into an integer part and a fractional part (Zhang: Figure 3; provides integer)
Kim is provided because it discloses a neural network that differentiates between integer and floating point (fraction)values (Figure 12 and Paragraphs 128-131). This functionality could be incorporated in the functionality of Zhang to differentiate between computations provided. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to apply a known technique to a known device ready for improvement and incorporate classification of outputs as found in Zhang. One would have been motivated to provide the functionality because it provides a useful mechanism for extracting information more uniformly.
Zhang also may not explicitly disclose generating a look-up table of the fractional part; and calculating the membrane potential value by performing a shift computation based on the look-up table and the integer part and performing an addition computation on the computed result
Ros is provided because it discloses an event driven look up table within a spiking neural network system (abstract). This look-up table could be applied to events provided within the modified Zhang. Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to apply a known technique to a known device ready for improvement and incorporate look-up tables for the output found in Zhang. One would have been motivated to provide a look-up table because it provides a useful mechanism for responses without additional computations.
Claim 7 is similar in scope to claim 2 and therefore rejected under the same rationale.
Zhang also provides processing device for structure (Page 98162, IV PC with Nvidia GE forceGTX 1060 GPU)
Kim also provides structure in Fig 12 with operation circuit.
Claim 8: Zhang, Kim and Ros disclose a spiking neural network computation learning system based on the temporal coding of claim 7, wherein the membrane potential value calculator further includes a barrel shifter configured to perform the shift computation (Kim: Figure 12 and Paragraph 33: Shifter functionality).
Claims 12-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Efficient Spiking Neural Networks With Logarithmic Temporal Coding, MING ZHANG ET AL. (“Zhang”), Pages 98156-98167 (1-12), 2-2020 in view of Paramasivam et al. (“Paramasivam” 20220222513 A1).
Claim 12: Zhang discloses a method of claim 1, however may not explicitly disclose wherein the kernel computation uses a uniform time constant and a uniform spike delay time that are identical across all layers of the spiking neural network, and wherein a static random-access memory (SRAM) spike decoder is replaced by a look-up table for decoding spike timesteps in the spiking neural network computation.
Paramasivam is provided because it discloses SRAM Look up table functionality (Paragraph 100). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to apply a known technique to a known device ready for improvement and provide a SRAM look-up conversion for the output found in Zhang. One would have been motivated to provide a look-up table because it provides a useful decoding mechanism without additional computations.
Claim 13: Zhang discloses a spiking neural network computation learning system based on the temporal coding of claim 6, wherein the kernel generator generates the kernel computation using a uniform time constant and a uniform spike delay time that are identical across all layers of the spiking neural network, and wherein a static random-access memory (SRAM) spike decoder of the PE array is replaced by a look-up table, and wherein the PE array is a log-domain PE array.
Paramasivam is provided because it discloses a matrix and SRAM Look up table functionality (Paragraph 100). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to apply a known technique to a known device ready for improvement and provide a SRAM look-up conversion for the output found in Zhang. One would have been motivated to provide a look-up table because it provides a useful decoding mechanism without additional computations.
Claims 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Efficient Spiking Neural Networks With Logarithmic Temporal Coding, MING ZHANG ET AL. (“Zhang”), Pages 98156-98167 (1-12), 2-2020 in view of Mirhassani et al. (“Mirhassani” 20230153585 A1).
Claim 14: Zhang discloses a method of claim 1, wherein the temporal coding is a coding scheme in which each neuron of the spiking neural network generates a single spike per computation, and a time at which the single spike is generated is inversely proportional to an input value of the neuron such that a greater input value produces an earlier spike generation time.
Mirhassani is provided because it discloses a spiking neural network functionality and further provides a time step inversely proportional to the input (Paragraphs 14 and 41). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filling date of the claimed invention to apply a known technique to a known device ready for improvement and provide the inverse capability with the time coding of Zhang. One would have been motivated to provide the functionality as a method of efficiency allowing uniform equations to be used when determining effects.
Response to Arguments
Applicant's arguments filed have been fully considered but they are not persuasive.
Regarding section A, applicant argues that the kernel generation is not disclosed. Examiner respectfully disagrees. The applicant is reading specific operations and equations into the claim from the specification. The claims can lean on the specification, however unless the feature are explicitly claimed, additional interpretations and mappings can be utilized. The NPL reference clearly speaks to a computation as cited in the rejection and further seen in Zhang’s abstract and Introduction.
Regarding section B, applicant argues conversion recognition is not disclosed. Examiner respectfully disagrees. The applicant is again reading the specification into the claims. The NPL reference speaks to conversion as cited in the rejection through the ReLU activation function.
Regarding section C, applicant argues a converted spike timestamp is not disclosed. Examiner respectfully disagrees.
The encoding with time steps found in Zhang is considered to read on the claimed features. This is also discussed in Zhang pages 98158, Section A.
Applicant is invited to positively recite the features found in the remarks in order to overcome the cited art.
Regarding the 103 rejection, applicant argues improper hindsight and unexpected results.
In response to applicant's argument that the examiner's conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning. But so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant's disclosure, such a reconstruction is proper. See In re McLaughlin, 443 F.2d 1392, 170 USPQ 209 (CCPA 1971).
Conclusion
The prior art made of record and not relied upon is considered pertinent to Applicant’s disclosure:
WO 2023284142 A1
Applicant is required under 37 C.F.R. § 1.111(c) to consider these references fully when responding to this action.
It is noted that any citation to specific pages, columns, lines, or figures in the prior art references and any interpretation of the references should not be considered to be limiting in any way. A reference is relevant for all it contains and may be relied upon for all that it would have reasonably suggested to one having ordinary skill in the art. In re Heck, 699 F.2d 1331, 1332-33, 216 U.S.P.Q. 1038, 1039 (Fed. Cir. 1983) (quoting In re Lemelson, 397 F.2d 1006, 1009, 158 U.S.P.Q. 275, 277 (C.C.P.A. 1968)).
THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to SHERROD KEATON whose telephone number is 571-270-1697. The examiner can normally be reached 9:30am to 5:00pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, Applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
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/SHERROD L KEATON/ Primary Examiner, Art Unit 2148
9-10-2026
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