DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application (claim 27) are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph:
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, except as otherwise indicated in an Office action.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 9, 12, 14-20, 23-25 and 27-29 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saito (US 20240039495) in view of Rattan et al. (US 11601309) and Singh et al. (US 20080054951).
As to claim 1, Saito’s figure 2 shows an apparatus comprising: a voltage-to-current converter (figure 2 except for RD51 and RD52) comprising: a plus input transistor (MN51); a minus input transistor (MN52); a plus current-source (IB51) coupled between the plus input transistor and a power distribution node; a minus current-source (IB52) coupled between the minus input transistor and the power distribution node. Figure 2 fails to show that the plus and minus current sources are configured with transistors. However, transistors used as current sources is well known in the art. It would have been obvious to one having ordinary skill in the art to use transistors for the plus and minus current sources for the purpose of saving space. Saito’s figure 2 further shows; a plus active resistor (MN53 – Rattan et al.’s figure 6 shows that transistor M1 receiving bias voltage is an active resistor and functions equivalent to resistor R2 figure 3 or 7) coupled between and in series with the plus input transistor and the plus current-source transistor; and a minus active resistor (MN54) coupled between and in series with the minus input transistor and the minus current-source transistor. Furthermore, Singh et al.’s ¶0029 teaches that “passive resistor technology allows a smaller resistance value than active resistor technology…less costly circuitry”. Therefore, it would have been obvious to one having ordinary skill in the art to use passive resistors for Saito’s active resistors for the purpose of saving cost. Saito et al.’s figure further shows a first resistor (figure 3 shows RS5X equivalents to plurality of resistors connected in series. Therefore, it would have been obvious to one having ordinary skill in the art to use plurality of series connected resistors for RS5X due to the doctrine of equivalent function, MPEP 2144.06. Therefore, one of the series connected resistors is a first resistor) coupled between a first node between the plus resistor (MN53) and the first current source transistor (IB51) and a second node between the minus resistor (MN54) and the minus current source transistor (IB52); and a second resistor (another one of the series connected resistors) coupled between the first node and the second node; wherein the plus resistor, the first resistor, the second resistor, and the minus resistor are coupled in series between the plus input transistor and the minus input transistor.
As to claim 4, Saito’s figure shows that the plus resistor comprises a plus adjustable resistor; and the minus resistor comprises a minus adjustable resistor (since Vb1 is adjustable).
As to claim 12, the modified Saito’s figure shows that the plus resistor comprises a plus adjustable resistor; the minus resistor comprises a minus adjustable resistor; and the first resistor comprises an adjustable resistor (two or more of the series connected resistors, see figure 3), and the second resistor comprises a second adjustable resistor (another two or more of the series connected resistors. Furthermore, it has been held adjustability, where needed, is not a patentable advance. Therefore, it would have been obvious to one having ordinary skill in the art to use adjustable resistor for each of the first and second resistors for the purpose of achieving desired resistances).
As to claim 14, the modified Saito’s figure shows that the first and second a resistors are coupled between the plus current-source transistor and the minus current-source transistor.
As to claim 15, the modified Saito’s figure shows that the first and second resistors are coupled between a channel terminal of the plus current-source transistor and a channel terminal of the minus current-source transistor.
As to claim 16, the modified Saito’s figure shows that the plus resistor is coupled between a channel terminal of the plus input transistor and the channel terminal of the plus current-source transistor; and the minus resistor is coupled between a channel terminal of the minus input transistor and the channel terminal of the minus current-source transistor.
As to claim 17, the modified Saito’s figures show that the channel terminal of the plus current-source transistor comprises a drain terminal of the plus current-source transistor (when NMOS transistor used as a current source for saving space); the channel terminal of the minus current-source transistor comprises a drain terminal of the minus current-source transistor; the channel terminal of the plus input transistor comprises a source terminal of the plus input transistor; and the channel terminal of the minus input transistor comprises a source terminal of the minus input transistor.
As to claim 18, the modified Saito’s figure shows that the plus input transistor, the plus resistor, and the plus current-source transistor are coupled together in series between the power distribution node and another power distribution node.
As to claim 19, the modified Saito’s figure shows that the power distribution node comprises a ground; and the other power distribution node comprises a voltage supply rail.
As to claim 20, the modified Saito’s figure show that the plus input transistor is configured to convert a voltage-mode signal received at a control terminal of the plus input transistor to produce a current-mode signal at a channel terminal of the plus input transistor.
As to claim 23, the modified Saito’s figure shows that the plus current-source transistor is configured to operate as a current source with respect to at least the plus input transistor.
As to claim 24, the modified Saito’s figure shows that the plus current-source transistor is configured to: produce an output current; and adjust the output current dynamically responsive to voltage swings created by the plus input transistor (it would have been obvious to one having ordinary skill in the art to used adjustable current source for Saito current source for the purpose of providing desired gain, see MPEP 2144.04. V.D).
As to claim 25, the modified Saito’s figure show that the plus current-source transistor is configured to: adjust the output current dynamically to counteract clipping experienced by the plus input transistor.
Claims 27-29 recite similar limitations in claims above. Therefore, they are rejected for the same reasons.
Claim(s) 2-5, 9-25 and 27-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Saito (US 20240039495) in view of Rattan et al. (US 11601309), Singh et al. (US 20080054951) and Hsu et al. (US 20230121521).
As to claim 2, the modified Saito’s figure shows that the plus and minus resistors and RS5X are variable resistors. The figure fails to show the internal structure of the variable resistors. However, Hsu et al.’s figure 5B shows a precise variable resistor. It would have been obvious to one having ordinary skill in the art to use Hsu et al.’s variable resistor for each of Saito’s variable resistors for the purpose of providing more precise output currents. Therefore, the modified Saito’s figure shows that the voltage-to-current converter comprises: a plus switch (Hsu’s CT1 in the pus resistor) coupled in parallel with the plus resistor (Hsu’s RA1).
As to claim 3, the modified Saito’s figure shows that the plus switch is configured to at least one of short or bypass the plus resistor responsive to being in a closed state.
As to claim 4, the modified Saito’s figure shows that the plus resistor comprises a plus adjustable resistor; and the minus resistor comprises a minus adjustable resistor.
As to claim 5, the modified Saito’s figure shows that the voltage-to-current converter comprises: a plus switch (Hsu’s CT1 in the modified plus resistor) coupled in parallel with the plus adjustable resistor (RA1); and a minus switch (Hsu’s CT1 in the modified minus resistor) coupled in parallel with the minus adjustable resistor (RA1).
As to claim 10, the modified Saito’s figure shows that the voltage-to-current converter comprises: a switch (Hsu’s CT1 used in RS5X) coupled in parallel with the resistor (Hsu’s RA1 in RS5X).
As to claim 11, the modified Saito’s figure shows that the voltage-to-current converter comprises: a plus switch coupled in parallel with the plus resistor; and a minus switch coupled in parallel with the minus resistor (see the rejection of claim 5).
As to claim 12, the modified Saito’s figure shows that the plus resistor comprises a plus adjustable resistor; the minus resistor comprises a minus adjustable resistor; and the resistor comprises an adjustable resistor.
As to claim 13, the modified Saito’s figure shows that the voltage-to-current converter comprises: a plus switch coupled in parallel with the plus adjustable resistor; a minus switch coupled in parallel with the minus adjustable resistor; and a switch coupled in parallel with the adjustable resistor (see the rejection of claims 10 and 11).
As to claim 14, the modified Saito’s figure shows that the voltage-to-current converter comprises: a resistor (RS5X) coupled between the plus current-source transistor and the minus current-source transistor.
As to claim 15, the modified Saito’s figure shows that the resistor is coupled between a channel terminal of the plus current-source transistor and a channel terminal of the minus current-source transistor.
As to claim 16, the modified Saito’s figure shows that the plus resistor is coupled between a channel terminal of the plus input transistor and the channel terminal of the plus current-source transistor; and the minus resistor is coupled between a channel terminal of the minus input transistor and the channel terminal of the minus current-source transistor.
As to claim 17, the modified Saito’s figures show that the channel terminal of the plus current-source transistor comprises a drain terminal of the plus current-source transistor (when NMOS transistor used as a current source for saving space); the channel terminal of the minus current-source transistor comprises a drain terminal of the minus current-source transistor; the channel terminal of the plus input transistor comprises a source terminal of the plus input transistor; and the channel terminal of the minus input transistor comprises a source terminal of the minus input transistor.
As to claim 18, the modified Saito’s figure shows that the plus input transistor, the plus resistor, and the plus current-source transistor are coupled together in series between the power distribution node and another power distribution node.
As to claim 19, the modified Saito’s figure shows that the power distribution node comprises a ground; and the other power distribution node comprises a voltage supply rail.
As to claim 20, the modified Saito’s figure show that the plus input transistor is configured to convert a voltage-mode signal received at a control terminal of the plus input transistor to produce a current-mode signal at a channel terminal of the plus input transistor.
As to claim 23, the modified Saito’s figure shows that the plus current-source transistor is configured to operate as a current source with respect to at least the plus input transistor.
As to claim 24, the modified Saito’s figure shows that the plus current-source transistor is configured to: produce an output current; and adjust the output current dynamically responsive to voltage swings created by the plus input transistor (it would have been obvious to one having ordinary skill in the art to used adjustable current source for Saito current source for the purpose of providing desired gain, see MPEP 2144.04. V.D).
As to claim 25, the modified Saito’s figure show that the plus current-source transistor is configured to: adjust the output current dynamically to counteract clipping experienced by the plus input transistor.
Claims 27-29 recite similar limitations in claims above. Therefore, they are is rejected for the same reasons.
Claim(s) 1 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kroebel et al. (US 20050190856) in view of Saito (US 20240039495) in view of Rattan et al. (US 11601309) and Singh et al. (US 20080054951).
Kroebel et al.’s figure 1 shows a digital-to-analog converter (4); a base-band filter (6, figure 1 is a baseband circuit, ¶0032) coupled between the digital-to-analog converter and a voltage-to-current converter (8); and a mixer (10), wherein the voltage-to-current converter is coupled between the base-band filter and the mixer. Figure 1 fails to show the structure of the voltage to current converter. However, the modified Saito’s figure 2 shows a precise voltage to current converter having structure as claimed. It would have been obvious to one having ordinary skill in the art to use the modified Saito’s voltage to current converter for Kroebel et al.’s voltage to current converter for the purpose of providing more precise converted currents.
Claim(s) 1, 4, 9, 12, 14-25 and 27-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Banba et al. (US 7215196) in view of Saito (US 20240039495).
As to claim 30, Banba et al.’s figure 2b or 2c shows an apparatus comprising: a voltage-to-current converter comprising: a plus input transistor (1); a minus input transistor (2); a plus current-source (5) and minus current source (6). The figure fails to show that the plus and minus current sources are transistors. However, it is well known that transistor biased in triode region function as a resistor (see 20 in figure 2b and figure 5). Therefore, it would have been obvious to one having ordinary skill in the art to use transistors for Banba et al.’s resistor current sources for the purpose of saving space. Thus, the modified Banba et al.’s figure further shows a plus current source transistor (the modified 5) coupled between and in series with the plus input transistor and a power distribution node (ground), the plus current-source transistor configured to be biased in a triode region of transistor operation during a voltage-to-current conversion procedure; a minus current-source transistor (the modified 6) coupled between and in series with the minus input transistor and the power distribution node, the minus current-source transistor configured to be biased in the triode region of transistor operation during the voltage-to-current conversion procedure; a plus resistor (51. It would have been obvious to one having ordinary skill in the art to use resistors for resistances 51 and 61 for the purpose of saving cost) coupled between the plus input transistor and the plus current-source transistor; a minus resistor (61) coupled between the minus input transistor and the minus current source transistor; and a conductive path (20 or 9) coupled between the plus input transistor and the minus input transistor and between the plus current-source transistor and the minus current-source transistor. The figure fails to show the internal structure of resistor 20 or 9. However, Saito’s figure 3 shows resistor RS5X comprises plurality of resistors connected in series. Therefore, it would have been obvious to one having ordinary skill in the art to use Saito’s variable resistor for Banba’s resistor (9 or 20) for the purpose of selecting more precise resistance. Therefore, the modified Banba’s figure shows the conductive path comprising a first resistor (one of the series connected resistors) and a second resistor (another one of the series connected resistors), wherein the plus resistor, the first resistor, the second resistor, the minus resistor are couple in series between the plus input transistor and the minus input transistor.
As to claim 1, Banba et al.’s figure 2c shows an apparatus comprising: a voltage-to-current converter comprising: a plus input transistor (1); a minus input transistor (2); a plus current-source transistor (5, see the rejection of claim 30) coupled between the plus input transistor and a power distribution node; a minus current-source transistor (6) coupled between the minus input transistor and the power distribution node; a plus resistor (51. It would have been obvious to one having ordinary skill in the art to use resistors for resistances 51 and 61 for the purpose of saving cost) coupled between and in series with the plus input transistor and the plus current-source transistor; and a minus resistor (61) coupled between and in series with the minus input transistor and the minus current-source transistor; a first resistor (one of the series connected resistors in 9 or 20) and a second resistor (another one of the series connected resistors in 9 or 20) coupled between a first node between the plus resistor (51) and the first current source transistor (5) and a second node between the minus resistor (61) and the minus current source transistor (6).
As to claim 4, Banba et al.’s figure 2c shows fails to show that the plus resistor comprises a plus adjustable resistor and the minus resistor comprises a minus adjustable resistor (it has been held that “adjustability, where needed, is not a patentable advance”, MPEP 2144.04. It would have been obvious to one having ordinary skill in the art to use adjustable resistor for the plus and minus resistors for the purpose of controlling the noise in the amplifier more precisely).
As to claim 12, Banba et al.’s figure 2c shows that the plus resistor comprises a plus adjustable resistor; the minus resistor comprises a minus adjustable resistor; and the resistor comprises first adjustable resistor (two of the series connected resistors); and the second resistor comprises a second adjustable resistor (another two of the series connected resistors).
As to claim 14, Banba et al.’s figure 2c shows that the first and second resistors (in 9 or 20) are coupled between the plus current-source transistor and the minus current-source transistor.
As to claim 15, Banba et al.’s figure 2c shows that the first and second resistors are coupled between a channel terminal of the plus current-source transistor and a channel terminal of the minus current-source transistor.
As to claim 16, Banba et al.’s figure 2c shows that the plus resistor is coupled between a channel terminal of the plus input transistor and the channel terminal of the plus current-source transistor; and the minus resistor is coupled between a channel terminal of the minus input transistor and the channel terminal of the minus current-source transistor.
As to claim 17, Banba et al.’s figure 2c shows that the channel terminal of the plus current-source transistor comprises a drain terminal of the plus current-source transistor (when NMOS transistor used as a current source); the channel terminal of the minus current-source transistor comprises a drain terminal of the minus current-source transistor; the channel terminal of the plus input transistor comprises a source terminal of the plus input transistor; and the channel terminal of the minus input transistor comprises a source terminal of the minus input transistor.
As to claim 18, Banba et al.’s figure 2c shows that the plus input transistor, the plus resistor, and the plus current-source transistor are coupled together in series between the power distribution node and another power distribution node.
As to claim 19, Banba et al.’s figure 2c shows that the power distribution node comprises a ground; and the other power distribution node comprises a voltage supply rail.
As to claim 20, Banba et al.’s figure 2c show that the plus input transistor is configured to convert a voltage-mode signal received at a control terminal of the plus input transistor to produce a current-mode signal at a channel terminal of the plus input transistor.
As to claim 21, it is inherent that current source transistor, i.e. the plus current-source transistor is configured to be biased in a triode region of transistor operation (see the rejection of claim 30).
As to claim 22, Banba et al.’s figure 2c shows a controller (not shown that biases the current source transistor(s) coupled to the voltage-to-current converter, the controller configured to bias the plus current-source transistor in the triode region of transistor operation to reduce nonlinearity of an output signal of the voltage-to-current converter.
As to claim 23, Banba et al.’s figure 2c shows that the plus current-source transistor is configured to operate as a current source with respect to at least the plus input transistor.
As to claim 24, Banba et al.’s figure 2c shows that the plus current-source transistor is configured to: produce an output current; and adjust the output current dynamically responsive to voltage swings created by the plus input transistor (it would have been obvious to one having ordinary skill in the art to used adjustable current source for Banba et al.’s current source for the purpose of providing desired gain, see MPEP 2144.04. V.D).
As to claim 25, Banba et al.’s figure 2c figure show that the plus current-source transistor is configured to: adjust the output current dynamically to counteract clipping experienced by the plus input transistor.
Claims 27-29 recite similar limitations in claims above. Therefore, they are rejected for the same reasons.
Claim(s) 2-5, 9-25 and 27-30 is/are rejected under 35 U.S.C. 103 as being unpatentable over Banba et al. in view of Saito (US 20240039495) and Hsu et al. (US 20230121521).
As to claim 2, the modified Banba et al.’s figure shows that the plus and minus resistors are variable resistors. The figure fails to show the internal structure of the variable resistors. However, Hsu et al.’s figure 5B shows a precise variable resistor. It would have been obvious to one having ordinary skill in the art to use Hsu et al.’s variable resistor for each of Banba et al.’s variable resistors for the purpose of providing more precise output currents. Therefore, the modified Banba et al.’s figure shows that the voltage-to-current converter comprises: a plus switch (Hsu’s CT1 in the pus resistor) coupled in parallel with the plus resistor (Hsu’s RA1).
As to claim 3, the modified Banba et al.’s figure shows that the plus switch is configured to at least one of short or bypass the plus resistor responsive to being in a closed state.
As to claim 4, the modified Banba et al.’s figure shows that the plus resistor comprises a plus adjustable resistor; and the minus resistor comprises a minus adjustable resistor.
As to claim 5, the modified Banba et al.’s figure shows that the voltage-to-current converter comprises: a plus switch (Hsu’s CT1 in the modified plus resistor) coupled in parallel with the plus adjustable resistor (RA1); and a minus switch (Hsu’s CT1 in the modified minus resistor) coupled in parallel with the minus adjustable resistor (RA1).
As to claim 10, the modified Banba et al.’s figure shows that the voltage-to-current converter comprises: a switch (Hsu’s CT1 used in resistor 9) coupled in parallel with the resistor (Hsu’s RA1 in resistor 9).
As to claim 11, the modified Banba et al.’s figure shows that the voltage-to-current converter comprises: a plus switch coupled in parallel with the plus resistor; and a minus switch coupled in parallel with the minus resistor (see the rejection of claim 5).
As to claim 12, the modified Banba et al.’s figure shows that the plus resistor comprises a plus adjustable resistor; the minus resistor comprises a minus adjustable resistor; and the resistor comprises an adjustable resistor.
As to claim 13, the modified Banba et al.’s figure shows that the voltage-to-current converter comprises: a plus switch coupled in parallel with the plus adjustable resistor; a minus switch coupled in parallel with the minus adjustable resistor; and a switch coupled in parallel with the adjustable resistor (see the rejection of claims 10 and 11).
As to claim 14, the modified Banba et al.’s figure shows that the voltage-to-current converter comprises: a resistor (9) coupled between the plus current-source transistor and the minus current-source transistor.
As to claim 15, the modified Banba et al.’s figure shows that the resistor is coupled between a channel terminal of the plus current-source transistor and a channel terminal of the minus current-source transistor.
As to claim 16, the modified Banba et al.’s figure shows that the plus resistor is coupled between a channel terminal of the plus input transistor and the channel terminal of the plus current-source transistor; and the minus resistor is coupled between a channel terminal of the minus input transistor and the channel terminal of the minus current-source transistor.
As to claim 17, the modified Banba et al.’s figure shows that the channel terminal of the plus current-source transistor comprises a drain terminal of the plus current-source transistor (when NMOS transistor used as a current source for saving space); the channel terminal of the minus current-source transistor comprises a drain terminal of the minus current-source transistor; the channel terminal of the plus input transistor comprises a source terminal of the plus input transistor; and the channel terminal of the minus input transistor comprises a source terminal of the minus input transistor.
As to claim 18, the modified Banba et al.’s figure shows that the plus input transistor, the plus resistor, and the plus current-source transistor are coupled together in series between the power distribution node and another power distribution node.
As to claim 19, the modified Banba et al.’s figure shows that the power distribution node comprises a ground; and the other power distribution node comprises a voltage supply rail.
As to claim 20, the modified Banba et al.’s figure shows that the plus input transistor is configured to convert a voltage-mode signal received at a control terminal of the plus input transistor to produce a current-mode signal at a channel terminal of the plus input transistor.
As to claim 23, the modified Banba et al.’s figure shows that the plus current-source transistor is configured to operate as a current source with respect to at least the plus input transistor.
As to claim 24, the modified Banba et al.’s figure shows that the plus current-source transistor is configured to: produce an output current; and adjust the output current dynamically responsive to voltage swings created by the plus input transistor (it would have been obvious to one having ordinary skill in the art to used adjustable current source for Saito current source for the purpose of providing desired gain, see MPEP 2144.04. V.D).
As to claim 25, the modified Banba et al.’s figure shows that the plus current-source transistor is configured to: adjust the output current dynamically to counteract clipping experienced by the plus input transistor.
Claims 27-30 recite similar limitations in claims above. Therefore, they are is rejected for the same reasons.
Claim(s) 1 and 26 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kroebel et al. (US 20050190856) in view of Banba et al. (US 7215196) and Saito (US 20240039495).
Kroebel et al.’s figure 1 shows a digital-to-analog converter (4); a base-band filter (6, figure 1 is a baseband circuit, ¶0032) coupled between the digital-to-analog converter and a voltage-to-current converter (8); and a mixer (10), wherein the voltage-to-current converter is coupled between the base-band filter and the mixer. Figure 1 fails to show the structure of the voltage to current converter. However, the modified Banba et al.’s figure 2c shows a precise voltage to current converter having structure as claimed. It would have been obvious to one having ordinary skill in the art to use the modified Saito’s voltage to current converter for Kroebel et al.’s voltage to current converter for the purpose of providing more precise converted currents.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/QUAN TRA/
Primary Examiner
Art Unit 2842