DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 24 November 2025 has been entered.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3, and 4-9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jones et al. (US 2020/0243794) in view of Kim et al. (US 2019/0197949).
Regarding claim 1:
Jones discloses some but not all of the claim as follows:
Claim 1
Jones
1. (Currently amended) Display circuitry comprising:
a substrate;
Fig. 6: 115. Jones call this a encapsulation layer in the figure but as per, e.g., paragraph 71 it is a glass substrate.
an encapsulation layer over the substrate;
Fig. 6: 140
thin-film transistor routing layers between the substrate and the encapsulation layer;
Paragraph 61: "assorted electrical connections"
first and second lines of display pixels formed in an active area and formed in the thin-film transistor routing layers;
Paragraph 61. Jones doesn't call them pixels here but they are as per, e.g., paragraph 65
an inactive region within the active area and comprising an optical window formed from a portion of the substrate, formed between first and second opposing portions of the thin-film transistor routing layers, and formed from a portion of the encapsulation layer, wherein the portion of the substrate and the portion of the encapsulation layer is configured to pass optical signals;
Shown in Fig. 6, where as can be seen the substrate and encapsulation layers are still present, and the transistor routing layers are routed around as per Fig. 8.
a first routing segment coupled to the first line of display pixels and formed in the first portion of the thin- film transistor routing layers;
Fig. 8
a second routing segment coupled to the second line of display pixels and formed in the first portion of the thin-film transistor routing layers;
Fig. 8
a merged segment into which the first and second routing segments are merged, wherein the merged segment is routed around the portion of the encapsulation layer forming the optical window from the first portion of the thin-film transistor routing layers to the second portion of the thin-film transistor routing layers; and
Jones shows routing segments routed around the portion of the encapsulation layer forming the optical window from the first portion of the thin-film transistor routing layers to the second portion of the thin-film transistor routing layers as shown in Fig. 8, but not merged segments.
display driver circuitry coupled to the first and second routing segments
Not shown in Jones
Therefore Jones does not disclose:
"a merged segment into which the first and second routing segments are merged, wherein the merged segment is routed around the portion of the encapsulation layer forming the optical window from the first portion of the thin-film transistor routing layers to the second portion of the thin-film transistor routing layers; and
"display driver circuitry coupled to the first and second routing segments"
Kim discloses:
a merged segment into which the first and second routing segments are merged (e.g., Fig. 31: CNL1k), wherein the merged segment is routed around the portion of the encapsulation layer forming the optical window from the first portion of the thin-film transistor routing layers to the second portion of the thin-film transistor routing layers (Fig. 31); and
display driver circuitry coupled to the first and second routing segment (Fig. 31: ESTk, ESTk+1, etc.)
It would have been obvious to one of ordinary skill at the time the application was filed to include in Jones the elements taught by Kim.
The rationale is as follows:
Jones and Kim are directed to the same field of art. Kim discloses this can decrease the number of coupling lines required (paragraph 152) and decrease the area of the non-pixel region (paragraph 161). This is a known improvement that one of ordinary skill in the art could have included with predictable results.
Regarding claim 3:
Jone in view of Kim discloses:
wherein the first and second routing segments and the merged segment, and the routing line form gate lines (as per, e.g., Kim paragraph 7151: "gate control line").
Regarding claim 5:
Jones in view of Kim discloses:
wherein the first and second routing segments and the merged segment form power supply lines (these lines may supply, e.g., an initialization power as per Kim paragraph 97).
Regarding claim 6:
Jones in view of Kim discloses:
wherein the first and second lines of display pixels are formed in the first portion of the thin-film transistor routing layers and wherein the display circuitry comprises a third line of display pixels formed in the active area and formed in the second portion of the thin-film transistor routing layers (shown in Kim, e.g., as per Fig. 31 there are rows of display portion on either side).
Regarding claim 7:
Jones in view of Kim discloses:
wherein the display circuitry comprises a third routing segment coupled to the third line of display pixels and formed in the second portion of the thin-film transistor routing layers and wherein the merged segment is coupled to the third routing segment (as per, e.g., Kim Fig. 31 there are routing segments on either side).
Regarding claim 8:
Jones in view of Kim discloses:
wherein the display circuitry comprises a fourth line of display pixels formed in the active area and formed in the second portion of the thin-film transistor routing layers, wherein the display circuitry comprises a fourth routing segment coupled to the fourth line of display pixels and formed in the second portion of the thin-film transistor routing layers, and wherein the merged segment is coupled to the third and fourth routing segments at a fanout node (shown in Kim Fig. 31).
Regarding claim 9:
Jones in view of Kim discloses:
wherein the inactive region comprises a border region between the optical window and the active area and wherein the merged segment overlaps the border region (Kim Fig. 31).
Claim(s) 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Jones in view of Kim, and further in view of Ryoo et al. (US 2017/0154566).
Regarding claim 4:
Jones in view of Kim discloses display circuitry as discussed above.
Jones in view of Kim Kim does not disclose:
“wherein the first and second routing segments, the merged segment, and the routing line form data lines.”
However, Ryoo discloses that data lines may also need to be routed around a hole (Fig. 5).
It would have been obvious to one of ordinary skill in the art at the time the application was filed to include in Jones in view of Kim wherein the first and second routing segments, the merged segment, and the routing line form data lines, as suggested by Ryoo.
The rationale is as follows:
Jones, Kim and Ryoo are directed to the same field of art.
This is just applying the invention of Jones and Kim to data lines. Kim does not need to route the data lines around the hole because the hole is on the upper edge of the display. Ryoo shows it could be elsewhere and data lines need to be routed in that case as well. One of ordinary skill in the art could have included this with predictable results.
Allowable Subject Matter
Claims 11-12, 14-20, and 22 are allowed.
Claims 23-24 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 11:
The closest prior art of record, Ryoo et al. (US 2017/0154566), does not teach or suggest every element of the claim in combination as follows.
Claim 11
Ryoo
11. (Currently amended) A display comprising:
an array of pixels formed within an active area;
Paragraph 37: active area AA
an inactive region at least partially surrounded by the active area, wherein the inactive region has a hole and a border region between the hole and the active area;
Paragraph 38: opening area HLA, as per the embodiments of Figs. 5-7
first routing lines that extend in a first direction across the display, wherein the first routing lines have portions that are routed around the hole, wherein the portions of the first routing lines do not extend into the border region, wherein the portions of the first routing lines that are routed around the hole comprises comprise a buried conductive layer that is overlapped by a transistor of a given pixel in the array of pixels, and wherein the buried conductive layer is between the transistor and a substrate on which the array of pixels is formed; and
Fig. 5: gate lines G2-G5, but Ryoo does not disclose that the portions of the first routing lines that are routed around the hole comprises comprise a buried conductive layer that is overlapped by a transistor of a given pixel in the array of pixels, and wherein the buried conductive layer is between the transistor and a substrate on which the array of pixels is formed
second routing lines that extend in a second direction across the display and that have portions that are routed around the hole to overlap the border region between the hole and the active area.
Fig. 5: data lines D3-D8, where they are in the border region as seen in Fig. 6
Therefore that the portions of the first routing lines that are routed around the hole comprises comprise a buried conductive layer that is overlapped by a transistor of a given pixel in the array of pixels, and wherein the buried conductive layer is between the transistor and a substrate on which the array of pixels is formed, in combination with the other elements of the claim, render it allowable over the prior art of record.
Regarding claims 12, 14-15, and 22:
They are dependent on claim 11.
Regarding claim 16:
The closest prior art of record, Wu in view of Kim, as applied in the Office Action mailed 02 September 2025, does not teach or suggest every element of the claim in combination as follows:
Claim 16
Wu in view of Kim
16. (Currently amended) A display comprising:
an array of pixels formed within an active area;
Paragraph 23
an inactive region at least partially surrounded by the active area and having first and second opposing sides;and
For example, as per Fig. 8
touch sensor circuitry configured to detect touch input over the active area, the touch sensor circuitry comprising:
Fig. 8: 40
first and second touch sensing circuits, wherein the inactive region is between the first and second touch sensing circuits;
In Wu there is only one touch sensing circuit
first and second parallel routing lines coupled to the first touch sensing circuit, wherein the first routing line is shorted to the second routing line at a node;
Paragraph 51, as per paragraphs 33-34
a merged routing line segment that is connected to the node and routed across the inactive region along the first side of the inactive region;
As per paragraphs 26-28, each merged segment is for at least two main lines
third and fourth parallel routing lines coupled to the second touch sensing circuit, wherein the third routing line is shorted to the fourth routing line at an additional node; and
As per, e.g., paragraphs 33-34 there are multiple sets of merged lines -- but they are not coupled to a second touch sensing circuit
an additional merged routing line segment that is connected to the additional node and routed across the inactive region along the second side of the inactive region.
Not disclosed in Wu, but shown in Kim Fig. 31
Therefore Wu in view of Kim does not disclose first and second touch sensing circuits, wherein the inactive region is between the first and second touch sensing circuits, where the first and second parallel routing lines are coupled to the first touch sensing circuit and the third and fourth parallel routing lines are coupled to the second touch sensing circuit.
Wu only has one touch sensing circuit, and the point of Wu's merged segments is to allow all the lines to be connected to that one touch circuit. Wu briefly mentions a second driving circuit (paragraph 52) but this is for the gate lines, and in this situation the gate lines are not merged because of the additional gate drive circuit. While first and second touch driving circuits are in and of themselves known in the art, that the first and second lines are connected to the first and the third and fourth connected to the second in the way detailed in the claims, in combination with the other elements of the claim, does not appear to be taught or suggested by the prior art of record.
Regarding claims 17-20:
They are dependent on claim 16.
Regarding claims 23 and 24:
The closest prior art of record, Jones in view of Kim, as applied above, does not teach or suggest wherein the merged segment overlaps the active area, or wherein the merged segment overlaps a display pixel transistor. These elements in combination with the other elements of the claim render it allowable over the prior art of record.
Response to Arguments
Applicant's arguments filed 24 November 2025 have been fully considered.
With respect to claim 1 and its dependent claims, these arguments are addressed by the new ground of rejection above.
With respect to claim 11, this claim is now in allowable form as discussed above.
With respect to claim 16, applicant’s arguments are persuasive and this claim has now been indicated as allowable.
Conclusion
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/CHRISTOPHER R LAMB/ Primary Examiner, Art Unit 2622