DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The prior art documents submitted by applicant in the Information Disclosure Statement filed on February 19, 2025 have all been considered and made of record (note the attached copy of form PTO-1449).
Drawings
Five (5) sheets of drawings were filed on August 15, 2023.
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: Reference number 201 in Figure 1. Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Inventorship
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Objections
Claim 11 is objected to because of the following informalities: “the second surface” in line 3 of claim 11 should be – a second surface—for the purpose of providing proper antecedent basis. Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 11-14 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lim et al. (US 2020/0249540 A1).
Regarding claim 11-14; Lim discloses a method for suppressing electrical coupling in a photonics integrated circuit (a 3D ground cage is provided as a shield for stray EM radiation; see the abstract; see Figures 1A, 1B, 2A, 2B), the method comprising:
providing a substrate (see Figures 2A, the substrate interface material layer 233 and PIC substrate 200) comprising a first surface and a second surface (see Figure 2A), the second surface being opposite to the first surface (see Figure 2A);
packaging a first photonic component (EO signal converter 108) and a second photonic component ( OE signal converter 124) on the first surface, the first photonic component comprising at least a light transmitter (EO signal converter, optical modulator; see paragraphs 2 and 41), the second photonic component comprising at least a light detector (OE signal converter, PD; see paragraphs 2 and 41);
forming an electrical reference net based on at least one metal layer (ground electrodes 112, 122) positioned in a dielectric (electrical insulating filler 233), the dielectric at least partially covering the light transmitter (108) and the light detector (124);
forming a first plurality of vias (212) through the substrate from the second surface to couple to the electrical reference net (112, 122), the first plurality of vias (212) being disposed to at least partially surround the light transmitter (108); and
forming a conductive layer (310) on the second surface of the substrate, the conductive layer being coupled to the first plurality of vias (212) and the electrical reference net (112) to form an electrical shield for the first photonic component (108);
further comprising forming a second plurality of vias (222) through the substrate from the second surface to couple to the electrical reference net (122), the second plurality of vias (222) being disposed to at least partially surround the light detector (124);
further comprising forming a second conductive layer (320) on the second surface of the substrate to couple to the second plurality of vias (222) and the electrical reference net (122) to form an electrical shield for the second photonic component (124);
wherein forming the electrical reference net (112, 122) comprises forming a first reference net (112) at least partially covering an area associated with the light transmitter (108), and forming a second reference net (122) at least partially covering an area associated with the light detector (124), the first reference net and the second reference net being isolated from each other and separately grounded (see Figure 1A, 1B, 2A, 2B).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Yoo et al. (US 2019/0310433 A1), hereafter Yoo, in view of Chao et al. (US 2008/0073747 A1), hereafter Chao.
Regarding claims 1-3; Yoo discloses an integrated circuit device (see Figure 2A) comprising:
a printed circuit board (PCB) (OE-PCB 204);
a first circuit (Electronic IC 206) on a first substrate comprising a first surface and a second surface (first surface and second surface; see annotated Figure 2A below), the first surface being coupled to the PCB (OE-PCB 204), the second surface comprising a first plurality of contacts coupled to the first circuit (Electronic IC 206);
a second circuit (Silicon-photonic interposer 202) on a second substrate comprising a third surface and a fourth surface (third surface and fourth surface; see annotated Figure 2A below), the second circuit (202) being disposed on the first circuit (206), the second circuit (202) comprising at least a first component (Mod) and a second component (PD), the third surface comprising a second plurality of contacts (second contacts) coupled to the first component (Mod) and the second component (PD), the second plurality of contacts being coupled to the first plurality of contacts (see annotated Figure 2A below);
wherein the first component (Mod) comprises at least one of optical transmitter, laser, optical amplifier, and optical modulator (Mod);
wherein the second component (PD) comprises at least one of photodetector, optical receiver, and optical sensor (PDs are photodiodes which are photodetectors/optical receivers).
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Yoo does not disclose:
a layer of conductive material disposed on the fourth surface;
a metal layer disposed in a dielectric between the first component and the third surface;
a first plurality of vias extended from the fourth surface through the second substrate to at least partially surround the first component, the first plurality of vias being coupled to the layer of conductive material and the metal layer; and
a second plurality of vias extended from the fourth surface through the second substrate to at least partially surround the second component, the second plurality of vias being coupled to the layer of conductive material and the metal layer.
Chao teaches that integrated circuit substrates (dies 10 in Figures 4A-4D, wherein the dies 10 may be provided in a stacked arrangement as illustrated in 5A-5B) may include electromagnetic shielding using through-silicon vias provided around components (12, 14) of integrated circuits (10, 27, 28) to provide an isolation structure and prevent unwanted electromagnetic interference (see paragraphs 2-9), where Chao et al. discloses: first and second integrated circuit substrate (28 and 27, stacked ICs 10; see Figure 5A) connected via contact pads (30), the first IC substrate (28) having first and second surfaces, the second IC substrate (27) having third and fourth surfaces, the third surface of the second IC substrate (27) being connected to the second surface of the first IC substrate (28), the second IC (27) having first and second components (12, 14; see IC 10 in Figures 4A-4D, wherein Figures 5A-5D illustrated ICs 10 in a stacked arrangement), wherein:
a layer of conductive material (20) is disposed on the fourth surface;
a metal layer (16/26/24; see Figures 4A-4D, 5A-5B; see paragraph 25) disposed in a dielectric between the first component (12) and the third surface (see Figures 4A-4D and 5A-5B);
a first plurality of vias (16, 161; see Figures 4A and 5A) extended from the fourth surface through the second substrate to at least partially surround the first component (12), the first plurality of vias (16, 161) being coupled to the layer of conductive material (20) and the metal layer (16/26/24) ; and
a second plurality of vias (16, 162) extended from the fourth surface through the second substrate to at least partially surround the second component (14), the second plurality of vias (16, 162) being coupled to the layer of conductive material (16/26/24) and the metal layer (20).
Chao et al. further teaches that since the through-silicon vias (16) extend from the top surface to the bottom surface, EM noise isolation is significantly more effective than with isolation structures that only extend int a portion of the substrate (see paragraph 41).
Therefore, before the effective filing date of the present invention, a person of ordinary skill in the art would have found it obvious to incorporate into the device of Yoo, a layer of conductive material disposed on the fourth surface; a metal layer disposed in a dielectric between the first component and the third surface; a first plurality of vias extended from the fourth surface through the second substrate to at least partially surround the first component, the first plurality of vias being coupled to the layer of conductive material and the metal layer; and a second plurality of vias extended from the fourth surface through the second substrate to at least partially surround the second component, the second plurality of vias being coupled to the layer of conductive material and the metal layer for the purpose of providing an electromagnetic shielding using through-silicon vias that provides effective electromagnetic noise isolation.
Regarding claim 4; Chao teaches that an electrical reference net based on the metal layer with a single ground connection (backside electrode 20 is grounded; see paragraphs 28 or 39, thereby providing a single ground connection).
Regarding claim 5; Yoo and Chao teach and/or suggest the device of claim 1 as applied above.
Chao does teach that the electromagnetic shielding vias are connected to ground via the metal layer (20). Chao further discloses an embodiment where a metal layer comprises a first grounded layer (24; see Figure 4C) at least partially covering an area of the first component (12) and a second grounded layer (24; see Figure 4C) at least partially covering an area of the second component. Yoo and Chao fail to disclose that the first grounded layer and the second grounded layer are isolated and having independent ground connections.
There are only two possibilities that exist for coupling the first and second ground layers (24) of Chao to ground, the first possibility is that the first and second ground layers (24) are connected to the same ground (Chao discloses a same grounded layer 20) that they are connected to through vias (26, 16, 161, 162), and the second possibility is that the first and second ground layers (24) are isolated from one another and have independent ground connections. One of ordinary skill in the art, before the effective filing date of the claimed invention, would have found it obvious to provide first and second ground layers coupled independently to ground in the invention of Yoo, since this is one of only two possible choices for connection, one of ordinary skill could have combined the elements by known coupling methods with no change in their respective functions to yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Regarding claim 6; Yoo and Chao teach and/or suggest the device of claim 1 as applied above, but fail to specify that a barrier layer is disposed between the fourth surface and the layer of conductive material (layer 20 as suggested by the teachings of Chao). The examiner takes Official notice that barrier layers are commonly provided between underlying substrates and metal layers for the purpose of preventing metal from diffusing into the substrate resulting in degraded circuit performance. Before the effective filing date of the present invention, a person of ordinary skill in the art would have found it obvious to include a barrier layer disposed between the fourth surface and the layer of conductive material in the invention of Yoo for the purpose of preventing unwanted diffusion from the metal layer into the substrate of Yoo.
Regarding claim 7; Chao teaches that the layer (20) of conductive material comprises a layer of Cu or Al or an alloy of Cu and Al or a layer of heavily doped silicon (see paragraph 28).
Regarding claim 8; Chao teaches that the first plurality of vias (16, 161) or the second plurality of vias (16, 162) comprises a via-to-via pitch separation (d; see Figure 3A) smaller than 1 mm (5 micrometers) for achieving at least -125dB isolation between the first component (12) and the second component (14) from the electromagnetic interference with a characteristic frequency up to 30 GHz (the examiner notes that the pitch of less than about 5 micrometers will inherently provide at least -125dB isolation for characteristics frequencies within the claimed range).
Claims 15 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al. (US 2020/0249540 A1), hereafter Lim, in view of Yoo et al. (US 2019/0310433 A1), hereafter Yoo.
Regarding claims 15 and 16; Lim discloses the method of claim 11 as discussed above, but does not disclose that the method further comprises forming at least one first metal contact and at least one second metal contact on the first surface, the at least one first metal contact being arranged to couple to the light transmitter and the at least one second metal contact being arranged to couple to the light detector, and coupling the at least one first metal contact and the at least one second metal contact respectively to corresponding contacts of an electronic integrated circuit.
Yoo teaches that a modulator (Mod) and a photodetector (PD) may be connected to an electronic integrated circuit (electronic IC 206) by forming metallic contacts on a surface of the photonic substrate (202) on which the modulator and photodetector are formed (see Figure 2A) for electrical connection to the electronic integrated circuit (206).
Thus, before the effective filing date of the present invention, a person of ordinary skill in the art would have found it obvious to further include, in the method of Lim, the steps of forming at least one first metal contact and at least one second metal contact on the first surface, the at least one first metal contact being arranged to couple to the light transmitter (modulator 108) and the at least one second metal contact being arranged to couple to the light detector (photodetector 124), and coupling the at least one first metal contact and the at least one second metal contact respectively to corresponding contacts of an electronic integrated circuit for the purpose of routing electronic control signals to the modulator and receiving electrical detection signals from the photodetector with a known arrangement of elements of prior art, since one of ordinary skill could have combined the elements by known coupling methods with no change in their respective functions to yield predictable results. KSR International Co. v. Teleflex Inc., 550 U.S. 398, 82 USPQ2d 1385 (2007).
Claims 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Lim et al. (US 2020/0249540 A1), hereafter Lim, in view of Chao et al. (US 2008/0073747 A1), hereafter Chao.
Regarding claims 17-20; Lim discloses a photonics integrated device with electromagnetic shielding (see the abstract, Figures 1A-1B and Figures 2A-2B) comprising:
a substrate (the substrate including interface material layer 233 and PIC layers 200) with a first surface and a second surface, the second surface being opposite to the first surface (see Figure 2A);
a circuit formed on the first surface, the circuit comprising at least a first component (108) and a second component (124), the first component comprising at least a light transmitter (modulator), the second component comprising at least a light detector (photodetector);
a metal layer (112, 122) disposed in a dielectric (233), the metal layer (112, 122) being an electrical reference with a grounded connection;
a first plurality of vias (212) from the second surface through the substrate, the first plurality of vias being configured to couple to the electrical reference and to at least partially surround the first component (108);
a second plurality of vias (222) from the second surface through the substrate, the second plurality of vias being configured to couple to the electrical reference and to at least partially surround the second component (124); and
a conductive layer (310, 320) disposed on the second surface of the substrate, the conductive layer (310, 320) being coupled to the first plurality of vias (212) and the second plurality of vias (222) to form a first electromagnetic shield and a second electromagnetic shield respectively for the first component (108) and the second component (124);
wherein the first plurality of vias and the second plurality of vias comprise a via-to-via pitch separation smaller than 1 mm to achieving -125dB isolation between the light transmitter and the light detector from the electromagnetic interference with characteristic frequencies up to 30GHz (see paragraph 70);
wherein the metal layer (112, 122) comprises a first section (112) and a second section (122) being separately grounded and respectively coupled with the first plurality of vias (212) and the second plurality of vias (222); and
wherein the conductive layer (310, 320) comprises a first portion (310) and a second portion (320) respectively coupled with the first section (112) and the second section (122) to be associated with the first electromagnetic shield and the second electromagnetic shield respectively, the first electromagnetic shield being decoupled from the second electromagnetic shield (see Figures 1A, 1B, 2A, and 2B).
Lim disclose that the metal layer (112, 122). Lim does not disclose the metal layer (112, 122) on the first surface. Chao teaches that a circuit comprising a first component (12) and a second component (14) may include a grounded metal layer (20) on a first surface coupled to conductive layers (24) on a second surface by a plurality of vias (16, 161, 162) for form an EM shield. Chao teaches that since the through-silicon vias (16, 161, 162) extends from the top surface to the bottom surface, electromagnetic noise isolation is significantly more effective than with isolation structures that only extend in a portion of the substrate (see paragraph 41). Thus, before the effective filing date of the present invention, a person of ordinary skill in the art would have found it obvious to form the metal layers (112, 122) on the bottom surface instead of in the middle of the substrate structure in the invention of Lim and to extend the vias (212, 222) from the top surface to the bottom surface between the conductive layer (310, 320) and the metal layer (112, 122) for the purpose of providing a significantly more effective electromagnetic shield by extending the isolation structures between the first and second surfaces in view of the teachings of Chao.
Allowable Subject Matter
Claims 9 and 10 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: The prior art of record, which is the most relevant prior art known, does not disclose or render obvious the device defined by claim 9, further comprising a metal plate coupled onto the layer of conductive material on the fourth surface and electrically grounded in combination with all of the limitations of base claim 1, or the device defined by claim 10, further comprising a first metal plate on a first portion of the fourth surface coupled to the first plurality of vias and the first grounded layer for shielding the first component, and a second metal plate on a second portion of the fourth surface coupled to the second plurality of vias and the second grounded layer for shielding the second component, the second metal plate being decoupled from the first metal plate in combination with all of the limitations of base claim 1 and all of the limitations of intervening claim 5.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Barth et al. (US 9,390,973 B2) teaches that barrier layers are typically used to prevent metal from diffusing into underlying substrates (see column 8, lines 52-63).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MICHELLE R CONNELLY whose telephone number is (571)272-2345. The examiner can normally be reached Monday-Friday, 9 AM to 5 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Uyen-Chau Le can be reached at 571-272-2397. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MICHELLE R CONNELLY/Primary Examiner, Art Unit 2874