DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
Applicant’s amendments to the claims, filed 03/06/2026, are accepted and appreciated by the
Examiner.
Response to Arguments
Applicant’s arguments, see Remarks, filed 03/06/2026, with respect to the rejection(s) of claim 1 under 35 U.S.C. 102 have been fully considered and are persuasive. Matsuo does not explicitly teach “each of the plurality of second resistors being directly connected to the first resistors and constantly grounded;” Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Matsuo.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 11 are rejected under 35 U.S.C. 103 as being unpatentable over Matsuo (US 20040051509 A1) as modified by Herkel (US 20170261541 A1).
With respect to claim 1,
Matsuo teaches,
An electronic device comprising: a voltage divider circuit including a plurality of first resistors connected in series between a first node and a second node, (Para. [0007] teaches “The voltage divider may include a first resistor circuit, a first switch circuit, a second resistor circuit, a second switch circuit, and a switch control circuit. The first resistor circuit includes a plurality of resistors connected in series between the output terminal and the output point of the voltage divider.” See Fig. 3.)
and a plurality of second resistors connected in parallel between the second node and a ground line; (Para. [0007] teaches “The second resistor circuit includes a plurality of resistors. The second switch circuit is configured to connect in parallel at least one of the plurality of resistors included in the second resistor circuit between the output point of the voltage divider and a common ground of the direct current power source in response to the input control signal.” See Fig. 3.)
and a voltage level detection circuit connected to the second node and to detect a voltage level of a divisional voltage generated at the second node. (Para. [0009] teaches “The voltage control circuit may include an error amplifier, a control circuit, and a smoothing circuit. The error amplifier amplifies an error of the divided voltage output from the output point of the voltage divider relative to the reference voltage. The control circuit is configured to generate the control signal in accordance with an output signal from the error amplifier to control the switching operation of the switching transistor.” (i.e. voltage See fig.6 where the control circuit encompasses the op amp 6.)
Matsuo does not explicitly teach,
each of the plurality of second resistors being directly connected to the first resistors and constantly grounded;
Herkel teaches,
A voltage dividing circuit with a first resistor directly connected to two second resistors in parallel directly connected to the first resistor. (Fig. 2 shows R2 which viewed is viewed as the first resistor and R1 and RD which are viewed as the second resistors.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify Matsuo with each of the plurality of second resistors being directly connected to the first resistors and constantly grounded such as that of Herkel.
One of ordinary skill would have been motivated to modify Matsuo, because R2 of Herkel could be replaced with two resistors to increase the resistance of the circuit and manipulate the voltage at the second node or the sum of the resistance of the two resistors could be equivalent to R2. Furthermore, directly connecting first resistors and the second resistors would make the resistance within the voltage divider fixed. Keeping the resistance at a fixed value would make it easier to determine when the voltage divider has degraded as the only reason the output voltage at the node would change is if there is a fault or degradation of one of the resistors in the voltage divider.
With respect to claim 11,
Matsuo further teaches,
The electronic device according to claim 1, wherein the plurality of first resistors and the plurality of second resistors have respective resistance values set such that the divisional voltage is lower than a rated input voltage of the voltage level detection circuit even in a case where a single fault occurs in any of the plurality of first resistors or the plurality of second resistors. (Fig. 3 teaches a voltage dividing circuit. In voltage dividing circuit it is inherent that the divisional voltage is less than the input voltage. Since Matsuo teaches a plurality of first and second resistors if one of the resistors is faulted the circuit would still be a voltage dividing circuit because of this redundancy. Therefore, Matsuo reads on the claim.
Claims 2, 3, and 12 are rejected under 35 U.S.C. 103 as being unpatentable over Matsuo (US 20040051509 A1) and Herkel (US 20170261541 A1) as applied to claim 1 above, and further in view of Iwao (JP 2014062879 A).
With respect to claim 2,
Matsuo further teaches,
The electronic device according to claim 1, wherein the first node is set to have a first voltage or a second voltage that is lower than the first voltage, (Para. [0028 teaches “The smoothing circuit 3 smoothes the signal output from the switching transistor 2 and outputs the signal having a voltage Vo to an output terminal OUT.” (i.e. Vo is voltage at the first terminal. Fig. 2 shows output point going into the voltage divider would be at some voltage.)
the voltage level detection circuit is to operate according to a first power supply voltage lower than the first voltage, (Para. [0028] teaches “a divided voltage Vd. The error amplifier 6 amplifies an error of the divided voltage Vd relative to the reference voltage Vr. The control circuit 7 controls the switching of the switching transistor 2 in accordance with the signal output from the error amplifier 6.” (i.e. the divided voltage would be lower.))
and output a value based on the voltage level of the divisional voltage, the value being determined to be either a high level or a low level in accordance with a threshold value, (Para. [0003] teaches “And to compare the divided voltage Vd with a predetermined reference voltage Vr.” (i.e. reference voltage is seen as threshold. Para. [0029] teaches “In accordance with a result of the comparison, the comparator controls a time that the switching transistor 2 is being turned on. The signal output from the switching transistor 2 is smoothed and output as the voltage Vo, Para. [0034] teaches “The switching controller 12 raises one of the control signals SP1-SPn to a predetermined high level (hereinafter referred to as a level H) and drops the rest down to a predetermined low level (hereinafter referred to as a level L) in accordance with the externally supplied input voltage switching signal Sc” (i.e. high level))
and the plurality of first resistors and the plurality of second resistors have respective resistance values that are set such that the divisional voltage when the first node is set to have the first voltage is between a voltage based on the threshold value and a rated input voltage of the voltage level detection circuit, each in a case where the plurality of first resistors and the plurality of second resistors are all normal and in a case where any of the plurality of first resistors or the plurality of second resistors has a fault. (Para. [0040] teaches “In other words, a desirable value of the output voltage Vo can be obtained from the voltage divider 11 by suitably selecting the voltage switching signal Sc.” (i.e. Therefore the resistors can be set to any value by selecting the appropriate signal and the signal can be adjusted to the same values if the resistors are degraded.)
Matsuo does not explicitly teach,
a digital value.
Iwao further teaches,
a digital value (Para. [0014] teaches “The CPU 12 uses this ADC to convert the analog output signal Vo, which is the output signal of the ground fault detection circuit 10, and calculates a digital output signal indicating the value of the current flowing from either the positive supply line 20 or the negative supply line 30 to the ground (hereinafter sometimes referred to as GND), i.e., the degree of ground fault in the supply line. The CPU 12 also directly displays this digital output signal on a display unit (not shown in FIG. 1), or transmits it to a signal processing device such as a PC (Personal Computer).”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Matsuo and Herkel with a digital value such as that of Iwao.
One of ordinary skill would have been motivated to modify the combination of Matsuo and Herkel, because it would allow the system to display the signal to better monitor the circuit as seen in Para. [0014] above. Furthermore, the invention of Iwao promotes a smaller and less expensive device as seen in Para. [0005].
With respect to claim 3,
Matsuo further teaches,
the electronic device according to claim 2, further comprising:
an electrical component including a load, the load being connected through a first connector to a power supply line supplied with a second power supply voltage, and connected through a second connector to the first node; (Load L in figure 3. Powered by battery 10 with voltage vbatt.)
a drive transistor to set the first node to have a voltage lower than the second power supply voltage during when the load is driven by the drive transistor; (Para. [0031] teaches PMOS transistors QP1)
wherein the first node is set to have the first voltage in accordance with a current from the load during when the load is not driven by the drive transistor. (Voltage at the first node will be higher as seen in Fig. 3.)
Matsuo does not explicitly teach,
and an anomaly determination circuit to determine an anomaly in any of the first connector, the second connector, the drive transistor, the plurality of first resistors, or the plurality of second resistors, in accordance with the voltage level determined by the voltage level detection circuit and a drive state of the drive transistor,
Iwao teaches,
and an anomaly determination circuit to determine an anomaly in any of the first connector, the second connector, the drive transistor, the plurality of first resistors, or the plurality of second resistors, in accordance with the voltage level determined by the voltage level detection circuit and a drive state of the drive transistor, (Para. [0011] teaches “According to the present invention, even if the resistance values of the resistors constituting the voltage divider circuit are increased and the steady-state current value is reduced, a difference current occurs between the currents flowing through the two voltage divider circuits during detection, ensuring the input voltage difference of the differential amplifier. Therefore, slight deterioration in insulation resistance can be detected by a smaller change in current than when a photocoupler is used (sensitivity is improved).” (i.e. anomaly in resistor) Para. [0015] teaches “ground fault detection circuit 10, and calculates a digital output signal indicating the value of the current flowing from either the positive supply line 20 or the negative supply line 30 to the ground” (i.e. Where the ground fault detection circuit is viewed as an anomaly determination circuit))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Matsuo and Herkel with an anomaly determination circuit to determine an anomaly in any of the first connector, the second connector, the drive transistor, the plurality of first resistors, or the plurality of second resistors, in accordance with the voltage level determined by the voltage level detection circuit and a drive state of the drive transistor such as that of Iwao. One of ordinary skill would have been motivated to modify the combination of Matsuo and Herkel, because it allows for higher sensitivity in the device as seen in Para. [0011] of Iwao above.
With respect to claim 12,
Matsuo further teaches,
The electronic device according to claim 1, wherein the electronic device further comprises a drive transistor connected to the first node; (Also see figure 3. Para. [0031] teaches PMOS transistors QP1)
Matsuo does not explicitly teach,
an anomaly determination circuit configured to determine an anomaly in the electronic device in accordance with the voltage level detected by the voltage level detection circuit and a drive state of the drive transistor.
Iwao teaches,
an anomaly determination circuit configured to determine an anomaly in the electronic device in accordance with the voltage level detected by the voltage level detection circuit and a drive state of the drive transistor. (Para. [0011] teaches “According to the present invention, even if the resistance values of the resistors constituting the voltage divider circuit are increased and the steady-state current value is reduced, a difference current occurs between the currents flowing through the two voltage divider circuits during detection, ensuring the input voltage difference of the differential amplifier. Therefore, slight deterioration in insulation resistance can be detected by a smaller change in current than when a photocoupler is used (sensitivity is improved).” (i.e. anomaly in resistor) Para. [0015] teaches “ground fault detection circuit 10, and calculates a digital output signal indicating the value of the current flowing from either the positive supply line 20 or the negative supply line 30 to the ground” (i.e. Where the ground fault detection circuit is viewed as an anomaly determination circuit))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Matsuo and Herkel with an anomaly determination circuit configured to determine an anomaly in the electronic device in accordance with the voltage level detected by the voltage level detection circuit and a drive state of the drive transistor such as that of Iwao. One of ordinary skill would have been motivated to modify the combination of Matsuo and Herkel, because it allows for higher sensitivity in the device as seen in Para. [0011] of Iwao above.
Claims 4-8, and 10 are rejected under 35 U.S.C. 103 as being unpatentable over Matsuo (US 20040051509 A1), Herkel (US 20170261541 A1), and Iwao (JP 2014062879 A) as applied to claim 3 above, and further in view of Hata (US 11316337 B2).
With respect to claim 4,
Matsuo further teaches, the electronic device according to claim 3, further comprising: an integrated circuit including the voltage level detection circuit and the anomaly determination circuit,
Matsuo does not explicitly teach,
wherein the anomaly determination circuit is to receive a base voltage of the drive transistor and determine the drive state of the drive transistor.
Hata teaches,
wherein the anomaly determination circuit is to receive a base voltage of the drive transistor and determine the drive state of the drive transistor. (Col. 6 ln(s). [14-24] teach “When the peak hold output Vpeak becomes 3.3V, an npn type digital transistor 71 connected to the subsequent stage of the peak hold circuit changes from the off state to the on state. When the digital transistor 71 enters the on state, a pnp type digital transistor 72 located at the subsequent stage enters the on state from the off state. When the digital transistor 72 enters the on state, a voltage generated by dividing 3.3V by resistors R1 and R2 is outputted as the detection signal Verr. The resistor R1 is a current-limiting resistor. The resistor R2 is a pull-down resistor.” (I.e. Voltage determines state of the transistor.))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Matsuo, Herkel, and Iwao wherein the anomaly determination circuit is to receive a base voltage of the drive transistor and determine the drive state of the drive transistor such as that of Hata. One of ordinary skill would have been motivated to modify the combination of Matsuo, Herkel, and Iwao, because it allows the system to identify abnormalities in a drive signal of an image forming device as seen in Col. 1 ln(s). [24-32] of Hata.
With respect to claim 5,
Matsuo does not explicitly teach,
The electronic device according to claim 4, wherein the integrated circuit includes an analog port to which the divisional voltage generated at the second node is input, and the voltage level detection circuit is an analog-to-digital converter to convert the divisional voltage input to the analog port into the digital value and output the digital value to the anomaly determination circuit.
Iwao teaches,
wherein the integrated circuit includes an analog port to which the divisional voltage generated at the second node is input, and the voltage level detection circuit is an analog-to-digital converter to convert the divisional voltage input to the analog port into the digital value and output the digital value to the anomaly determination circuit. (Para. [0014] “The CPU 12 includes, for example, an A/D converter (Analog-to-Digital Converter; not shown in FIG. 1). Hereinafter, this may be referred to as ADC.) is composed of. The CPU 12 uses this ADC to convert the analog output signal Vo, which is the output signal of the ground fault detection circuit 10, and calculates a digital output signal indicating the value of the current flowing from either the positive supply line 20 or the negative supply line 30 to the ground (hereinafter sometimes referred to as GND), i.e., the degree of ground fault in the supply line. The CPU 12 also directly displays this digital output signal on a display unit (not shown in FIG. 1), or transmits it to a signal processing device such as a PC (Personal Computer) that is provided separately from the CPU.” (i.e. where the ground fault detection circuit is viewed as a second node,)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Matsuo, Herkel, Iwao, and Hata wherein the integrated circuit includes an analog port to which the divisional voltage generated at the second node is input, and the voltage level detection circuit is an analog-to-digital converter to convert the divisional voltage input to the analog port into the digital value and output the digital value to the anomaly determination circuit such as that of Iwao. One of ordinary skill would have been motivated to modify the combination of Matsuo, Herkel, Iwao, and Hata, because it would allow the system to display the signal to better monitor the circuit as seen in Para. [0014] above. Furthermore, the system of Iwao promotes a smaller and less expensive device as seen in Para. [0005].
With respect to claim 6,
Matsuo further teaches,
The electronic device according to claim 4, wherein the voltage level detection circuit is a general-purpose input/output port to receive the divisional voltage generated at the second node. (Fig. 2 shows input into the control circuit 7 which is viewed as a port.)
Matsuo does not explicitly teach,
and output the digital value based on the received divisional voltage to the anomaly determination circuit.
Iwao teaches,
and output the digital value based on the received divisional voltage to the anomaly determination circuit. (Para. [0034] teaches “The ADC outputs an n-bit digital output signal (n bits arranged from the most significant to the least significant binary number, such as "00...00") between the maximum and minimum values of the input analog output signal Vo, centered around the reference voltage Vref x (1/2).”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Matsuo, Herkel, Iwao, and Hata with output the digital value based on the received divisional voltage to the anomaly determination circuit such as that of Iwao. One of ordinary skill would have been motivated to modify the combination of Matsuo, Herkel, Iwao, and Hata, because it would allow the system to analyze the voltage to determine anomalies. Furthermore, the system of Iwao promotes a smaller and less expensive device as seen in Para. [0005].
With respect to claim 7,
Matsuo does not explicitly teach,
The electronic device according to claim 3, further comprising: an error information memory that stores error information, the error information indicating an error that has occurred in an apparatus in which the electronic device is installed, wherein the anomaly determination circuit is to further perform at least one of analysis of a cause of an anomaly or prediction of occurrence of an anomaly, in the apparatus in which the electronic device is installed, based on the determined anomaly and the error information stored in the error information memory.
Hata teaches,
an error information memory that stores error information, the error information indicating an error that has occurred in an apparatus in which the electronic device is installed, wherein the anomaly determination circuit is to further perform at least one of analysis of a cause of an anomaly or prediction of occurrence of an anomaly, in the apparatus in which the electronic device is installed, based on the determined anomaly and the error information stored in the error information memory. (Col. 5 Ln(s).6-13 teach “The CPU 11 executes control programs stored in the ROM area of a memory 62, thereby realizing various functions (for example, an error detection functional section 61). Based on the detection signal Verr, the error detection functional section 61 determines the presence or absence of a fault related to the drive signal Vdrv, the control signal Vset, or the power supply circuits.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Matsuo, Herkel, and Iwao wherein an error information memory that stores error information, the error information indicating an error that has occurred in an apparatus in which the electronic device is installed, wherein the anomaly determination circuit is to further perform at least one of analysis of a cause of an anomaly or prediction of occurrence of an anomaly, in the apparatus in which the electronic device is installed, based on the determined anomaly and the error information stored in the error information memory such as that of Hata. One of ordinary skill would have been motivated to modify the combination of Matsuo, Herkel, and Iwao, because saving the values allows the system to identify future errors as seen in Col. 5 Ln(s). [60-67] of Hata.
With respect to claim 8,
Matsuo does not explicitly teach,
The electronic device according to claim 3, further comprising: an error notifying unit configured to provide a notification of the anomaly determined by the anomaly determination circuit to an extraneous source.
Hata teaches,
The electronic device according to claim 3, further comprising: an error notifying unit configured to provide a notification of the anomaly determined by the anomaly determination circuit to an extraneous source. (Col. 8 Ln(s). [17-24] teach “In step S114, the CPU 11 makes a notification of an abnormality. For example, the CPU 11 outputs to the display device 63 a notification indicating that an anomaly has been detected. In step S115, the CPU 11 stops the photosensitive drum 2. If an anomaly is not detected in step S104, the CPU 11 advances the processing to step S105.” (i.e. CPU 11 is error notifying unit and display device is the extraneous source.))
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Matsuo, Herkel, and Iwao an error notifying unit configured to provide a notification of the anomaly determined by the anomaly determination circuit to an extraneous source such as that of Hata. One of ordinary skill would have been motivated to modify the combination of Matsuo and Iwao, because notifying users of error would allow the system to be fixed before further damage is caused.
With respect to claim 10,
Matsuo does not explicitly teach,
An image forming apparatus comprising: the electronic device according to claim 8; and an image forming unit to form an image.
Kata teaches,
an image forming unit to form an image. (Col. 1 Ln(s). [13-16] teach “A power supply apparatus used in an electrophotographic image forming apparatus generates various high voltages (charging voltage, developing voltage, transfer voltage, and the like) according to an electrophotographic process.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Matsuo, Herkel, and Iwao with an image forming unit to form an image such as that of Kata. One of ordinary skill would have been motivated to modify the combination of Matsuo, Herkel, and Iwao, because as seen in Col. 1 Ln(s). [13-16] “If these voltages cease to be appropriate, the quality of an image to be output by the image forming apparatus may deteriorate.” Therefore, it would be advantageous to monitor the voltage of an image forming apparatus.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Matsuo (US 20040051509 A1) and Herkel (US 20170261541 A1) as applied to claim 1 above, and further in view of Hata (US 11316337 B2).
With respect to claim 9,
Matsuo does not explicitly teach,
An image forming apparatus comprising: the electronic device according to claim 1; and an image forming unit to form an image.
Hata teaches,
an image forming unit to form an image. (Col. 1 Ln(s). [13-16] teach “A power supply apparatus used in an electrophotographic image forming apparatus generates various high voltages (charging voltage, developing voltage, transfer voltage, and the like) according to an electrophotographic process.”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Matsuo and Herkel with an image forming unit to form an image such as that of Hata. One of ordinary skill would have been motivated to modify the combination of Matsuo and Herkel, because as seen in Col. 1 Ln(s). [13-16] “If these voltages cease to be appropriate, the quality of an image to be output by the image forming apparatus may deteriorate.” Therefore, it would be advantageous to monitor the voltage of an image forming apparatus.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/JOSHUA L FORRISTALL/Examiner, Art Unit 2857
/ANDREW SCHECHTER/Supervisory Patent Examiner, Art Unit 2857
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