DETAILED ACTION
This action is responsive to the communication filed 18 May 2026.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of Applicant' s Information Disclosure Statement(s) (IDS). The IDS(es) has/have been considered.
Response to Arguments
Applicant’s arguments with respect to claims 1-3, 5-11, and 13-15 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Objections
The Non-Final Rejection mailed 18 February 2026 advised Applicant that should claim 4 be found allowable, claim 15 will be objected to under 37 CFR 1.75 as being a substantial duplicate thereof.
Applicant canceled claim 4, obviating the potential issue.
Claim Rejections - 35 USC § 112
The rejections of claims 11 and 15 under § 112(b) are withdrawn, responsive to Applicant’s amendment of the claims.
The rejections of claims 4 and 12 under § 112(d) are withdrawn, responsive to Applicant’s cancelation of the claims.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-3, 5-11, and 13-15 are rejected under 35 U.S.C. § 102(a)(2) as being anticipated by U.S. Patent Publication No. 2021/0391346 (filed Jan. 27, 2021) (hereinafter “Kim”).
Regarding independent claim 1, Kim discloses: A three-dimensional memory device, comprising:
at least one alternating stack of insulating layers (FIGS. 3/4, interlayer insulating layers 120, [0039]) and electrically conductive layers (FIGS. 3/4, gate electrodes 130, [0039]) having a first lengthwise sidewall and a second lengthwise sidewall that laterally extend along a first horizontal direction (FIGS. 3/4, depicting wherein the interlayer insulating layers 120 and gate electrodes 130 have a first and second lengthwise sidewall the laterally extend along a first horizontal direction);
memory openings vertically extending through the at least one alternating stack (FIGS. 3/4, depicting wherein channel structures CH penetrate through openings in the alternating stack of interlayer insulating layers 120 and gate electrodes 130);
memory opening fill structures located in the memory openings, wherein each of the memory opening fill structures comprises a vertical semiconductor channel (FIGS. 3/4, depicting wherein the channel structures CH comprise a channel layer 140, [0063]) and a respective vertical stack of memory elements located at levels of the electrically conductive layers (FIGS. 3/4, depicting e.g., gate dielectric layer 145, [0065]);
a first laterally-extending trench fill structure contacting the first lengthwise sidewall of the at least one alternating stack (FIGS. 3/4, separation regions MS1/MS2 and separation group SG1/SG2, [0083], [0089]) and comprising:
a first-type dielectric bridge structure having a first volume (FIGS. 3/4, depicting, e.g., a leftmost capping insulating layer 171 between conductive layer portions 109 in the first or second region R1/R2, which has a first volume, [0096]);
a second-type dielectric bridge structure having a second volume greater than the first volume (FIGS. 3/4, depicting, e.g., a leftmost or second or third from leftmost capping insulating layer 171 in the second region R2 between conductive layer portions 109, which has a second volume that is greater than the first volume, [0096]); and
a first trench dielectric material portion extending below the first-type and the second-type dielectric bridge structures (FIGS. 3/4, depicting a first portion comprising a conductive layer 109 and a separation insulating layer 107, which extend below the capping insulating layers 171, [0089]), and comprising a dielectric liner (FIGS. 3/4, separation insulating layer 107, [0089], [0096]) embedding an electrically conductive trench fill via structure (FIGS. 3/4, conductive layer 109);
a source region located below the first laterally-extending trench fill structure (FIGS. 3/4, active structure ACT including active patterns 111-114, located below the separation regions MS1/MS2 and separation group SG1/SG2, [0043]) and contacting electrically conductive trench fill via structure (FIGS. 3/4, depicting wherein the active patterns 111-114 contact the conductive layer 109).
Regarding claim 2, Kim further discloses wherein the second-type dielectric bridge structure (FIGS. 3/4, depicting, e.g., second or third from leftmost capping insulating layer 171, which has a first vertical thickness) has a greater vertical thickness than the first-type dielectric bridge structure (FIGS. 3/4, depicting, e.g., leftmost capping insulating layer 171, which has a second vertical thickness that is less than the first vertical thickness).
Regarding claim 3, Kim further discloses wherein the first-type dielectric bridge structure has a first top surface located within a first horizontal plane and has a first bottom surface that is vertically spaced from the first horizontal plane by a first vertical distance (FIGS. 3/4, depicting, e.g., leftmost capping insulating layer 171, which has a first bottom surface vertically spaced from a first top surface in a first horizontal plane by a first vertical distance); the second-type dielectric bridge structure has a second top surface located within the first horizontal plane and having a second bottom surface that is vertically spaced from the first horizontal plane by a second vertical distance greater than the first vertical distance (FIGS. 3/4, depicting, e.g., second or third from leftmost capping insulating layer 171, which has a second bottom surface vertically spaced from a second top surface in the first horizontal plane by a second vertical distance that is greater than the first vertical distance); and the first trench dielectric material portion comprises a topmost surface segment located within the first horizontal plane between the first-type dielectric bridge structure and the second-type dielectric bridge structure (FIGS. 3/4, depicting wherein the first portion comprising a conductive layer 109 and a separation insulating layer 107 comprises a topmost surface segment in the first horizontal plane located between the leftmost and second or third from leftmost capping insulating layers 171), a first recessed surface segment contacting the first bottom surface (FIGS. 3/4, depicting wherein the first portion comprising a conductive layer 109 and a separation insulating layer 107 includes a first recessed surface segment contacting the bottom surface of the leftmost capping insulating layer), and a second recessed surface segment contacting the second bottom surface (FIGS. 3/4, depicting wherein the first portion comprising a conductive layer 109 and a separation insulating layer 107 includes a second recessed surface segment contacting the bottom surface of the second or third from leftmost capping insulating layer).
Regarding claim 5, Kim further discloses wherein the second-type dielectric bridge structure has at least one of a greater horizontal length along the first horizontal direction or a greater horizontal width along a second horizontal direction perpendicular to the first horizontal direction than the first-type dielectric bridge structure (FIGS. 3/4, depicting wherein, e.g., the second or third from leftmost capping insulating layer 171 has a length in the first horizontal direction that is greater than a width of the width of the leftmost capping insulating layer 171 in a second horizontal direction perpendicular to the first horizontal direction).
Regarding claim 6, Kim further discloses at least one retro- stepped dielectric material portion embedded within the at least one alternating stack and comprising a respective dielectric material (FIGS. 3/4/13-17, depicting wherein a stepped dielectric material portion comprising the capping insulating layer 171 is embedded in the interlayer insulating layers 120 and gate electrodes 130, [0040], [0057]), wherein one of the at least one retro-stepped dielectric material portion contacts each of the first-type dielectric bridge structure, the second-type dielectric bridge structure, and the first trench dielectric material portion (FIGS. 3/4/13-17, depicting wherein the stepped dielectric material portion comprising the capping insulating layer 171 contacts the leftmost capping insulating layer 171, second or third from leftmost capping insulating layer 171, and first portion comprising a conductive layer 109 and a separation insulating layer 107).
Regarding claim 7, Kim further discloses the at least one alternating stack comprises a staircase having stepped surfaces (FIGS. 3/4/13-17, depicting wherein the interlayer insulating layers 120 and gate electrodes 130 form a staircase having stepped surfaces); the stepped surfaces contact stepped bottom surfaces of the at least one retro-stepped dielectric material portion (FIGS. 3/4/13-17, depicting wherein the interlayer insulating layers 120 and gate electrodes 130 forming a staircase having stepped surfaces contact bottom surfaces of the stepped dielectric material portion comprising the capping insulating layer 171); the staircase comprises a respective lengthwise sidewall that contacts the first laterally-extending trench fill structure (FIGS. 3/4/13-17, depicting wherein the interlayer insulating layers 120 and gate electrodes 130 forming a staircase having stepped surfaces comprise a lengthwise sidewall that contacts the first portion comprising a conductive layer 109 and a separation insulating layer 107); the memory opening fill structures are located in a first memory array region and in a second memory array region (FIGS. 3/4, depicting, e.g., leftmost regions including contact structures CH forming first array regions); the staircase is located between the first and the second memory array regions (FIGS. 3/4, depicting, e.g., rightmost regions including contact structures CH forming first array regions, and further wherein the interlayer insulating layers 120 and gate electrodes 130 forming a staircase having stepped surfaces is formed between the first and second array regions); the electrically conductive layers extend continuously from the first memory array region to the second memory array region (FIGS. 3/4/13-17, depicting wherein the gate electrodes 130 extend continuously from the first array region to the second array region); the first-type dielectric bridge structure is located laterally adjacent to an upper portion of the staircase (FIGS. 3/4/13-17, depicting wherein the leftmost capping insulating layer 171 between conductive layer portions corresponds to and is laterally adjacent to an upper portion of the interlayer insulating layers 120 and gate electrodes 130 forming a staircase having stepped surfaces); and the second-type bridge structure is located laterally adjacent to a lower portion of the staircase (FIGS. 3/4/13-17, depicting wherein the second or third from the leftmost capping insulating layer 171 between conductive layer portions corresponds to and is laterally adjacent to a lower portion of the interlayer insulating layers 120 and gate electrodes 130 forming a staircase having stepped surfaces).
Regarding claim 8, Kim further discloses layer contact via structures (FIGS. 3/4/13-17, contact plugs MC, [0095]) vertically extending through the at least one retro-stepped dielectric material portion and contacting a top surface of a respective electrically conductive layer within the at least one alternating stack (FIGS. 3/4/13-17, depicting wherein the contact plugs MC extend through the stepped dielectric material portion comprising the capping insulating layer 171 and contact the uppermost gate electrodes 130 within the stack of interlayer insulating layers 120 and gate electrodes 130, [0095]).
Regarding claim 9, Kim further discloses wherein the at least one retro-stepped dielectric material portion (FIGS. 3/4/13-17, depicting a stepped dielectric material portion comprising the capping insulating layer 171) is laterally spaced from the second lengthwise sidewall (FIGS. 3/4/13-17, depicting wherein the stepped dielectric material portion comprising the capping insulating layer 171 is laterally spaced from the second lengthwise sidewall laterally extending along a first horizontal direction).
Regarding claim 10, Kim further discloses wherein the first laterally-extending trench fill structure further comprises an additional first-type dielectric bridge structure (FIGS. 3/4, depicting, e.g., a leftmost capping insulating layer 171 in the first region R1, [0039]) that is laterally spaced from the first-type dielectric bridge structure and from the second-type dielectric bridge structure (FIGS. 3/4, depicting, e.g., leftmost capping insulating layer 171 in the first region R1 is laterally spaced from the leftmost capping insulating layer 171 and second or third from leftmost capping insulating layer 171), and does not directly contact any electrically conductive layer within the at least one alternating stack or the at least one retro-stepped dielectric material portion (FIGS. 3/4, depicting wherein the leftmost capping insulating layer 171 in the first region R1 does not contact the interlayer insulating layers 120 and gate electrodes 130).
Regarding claim 11, Kim further discloses wherein the at least one retro-stepped dielectric material portion (FIGS. 3/4/13-17, stepped dielectric material portion comprising the capping insulating layer 171) comprises a bottommost retro-stepped dielectric material portion (FIGS. 3/4/13-17, depicting wherein the stepped dielectric material portion comprising the capping insulating layer 171 comprises a portion that is closer to the substrate 101); and a topmost retro-stepped dielectric material portion that overlies the bottommost retro- stepped dielectric material portion (FIGS. 3/4/13-17, depicting wherein the stepped dielectric material portion comprising the capping insulating layer 171 comprises a portion that is further from the substrate 101), and the topmost retro-stepped dielectric material portion contacts each of the first-type dielectric bridge structure, the second-type dielectric bridge structure, and the first trench dielectric material portion (FIGS. 3/4/13-17, depicting wherein the stepped dielectric material portion comprising the capping insulating layer 171 comprises a portion that is further from the substrate 101 and contacts the leftmost capping insulating layer 171, the second or third from leftmost capping insulating layer 171, and the first portion comprising a conductive layer 109 and a separation insulating layer 107).
Regarding claim 13, Kim further discloses wherein the first laterally-extending trench fill structure further comprises a third-type dielectric bridge structure having a third volume greater than the second volume (FIGS. 3/4, depicting wherein, when the leftmost capping insulating layer 171 in the first region R1 is a “first-type dielectric bridge structure,” the leftmost capping insulating layer 171 is a “first-type dielectric bridge structure,” then the second or third from leftmost capping insulating layer 171 between conductive layer 109 portions is a “third-type dielectric bridge structure,” having a third volume greater than a second volume).
Regarding claim 14, Kim further discloses a second laterally-extending trench fill structure contacting the second lengthwise sidewall of the at least one alternating stack and comprising additional dielectric bridge structures (FIGS. 3/4, depicting, e.g., wherein the separation regions MS1/MS2 and separation group SG1/SG2 comprise further structures beyond those depicted in portion “A”, [0083], [0089]), wherein each of the additional dielectric bridge structures within the second laterally-extending trench fill structure has that first volume (FIGS. 3/4, depicting wherein those capping insulating layer 171 between conductive layer portions 109 not in portion “A” would have that first volume, [0096]), wherein: each of the additional dielectric bridge structures has a same vertical thickness, horizontal length and horizontal width as each of the first-type dielectric bridge structures (FIGS. 3/4, depicting wherein those capping insulating layer 171 between conductive layer portions 109 not in portion “A” would have that same vertical thickness, horizontal length, and horizontal width, [0096]); and the second laterally-extending trench fill structure comprises a second trench dielectric material portion (FIGS. 3/4, depicting a second portion comprising a conductive layer 109 and a separation insulating layer 107) contacting each of the additional dielectric bridge structures and having a same material composition as the first trench dielectric material portion (FIGS. 3/4, depicting wherein the second portion contacts those capping insulating layers 171 between conductive layer portions 109 not in portion “A”).
Regarding independent claim 15, Kim discloses: A three-dimensional memory device, comprising:
at least one alternating stack of insulating layers (FIGS. 3/4, interlayer insulating layers 120, [0039]) and electrically conductive layers (FIGS. 3/4, gate electrodes 130, [0039]) having a first lengthwise sidewall and a second lengthwise sidewall that laterally extend along a first horizontal direction (FIGS. 3/4, depicting wherein the interlayer insulating layers 120 and gate electrodes 130 have a first and second lengthwise sidewall the laterally extend along a first horizontal direction);
memory openings vertically extending through the at least one alternating stack (FIGS. 3/4, depicting wherein channel structures CH penetrate through openings in the alternating stack of interlayer insulating layers 120 and gate electrodes 130);
memory opening fill structures located in the memory openings, wherein each of the memory opening fill structures comprises a vertical semiconductor channel (FIGS. 3/4, depicting wherein the channel structures CH comprise a channel layer 140, [0063]) and a respective vertical stack of memory elements located at levels of the electrically conductive layers (FIGS. 3/4, depicting e.g., gate dielectric layer 145, [0065]); and
a first laterally-extending trench fill structure contacting the first lengthwise sidewall of the at least one alternating stack (FIGS. 3/4, separation regions MS1/MS2 and separation group SG1/SG2, [0083], [0089]) and comprising:
a first trench dielectric material portion (FIGS. 3/4, depicting a first portion comprising a conductive layer 109 and a separation insulating layer 107);
a plurality of first-type dielectric bridge structures having the first volume and a first pitch (FIGS. 3/4, depicting, e.g., a plurality of leftmost capping insulating layer 171 between conductive layer portions 109 in the first or second region R1/R2, which have a first volume and a first pitch, [0096]); and
a plurality of second-type dielectric bridge structures having a second volume greater than the first volume, and a second pitch different from the first pitch (FIGS. 3/4, depicting, e.g., a plurality of capping insulating layers 171 including a leftmost or second or third from leftmost capping insulating layer 171 in the second region R2 between conductive layer portions 109, which have a second volume that is greater than the first volume and a second pitch that is different from a first pitch, [0096]),
wherein the first trench dielectric material portion extends below the plurality of the first-type and the second-type dielectric bridge structures (FIGS. 3/4, depicting a first portion comprising a conductive layer 109 and a separation insulating layer 107, which extend below the capping insulating layers 171, [0089]), and comprising a dielectric liner (FIGS. 3/4, separation insulating layer 107, [0089], [0096]) embedding an electrically conductive trench fill via structure (FIGS. 3/4, conductive layer 109); and
a source region located below the first laterally-extending trench fill structure (FIGS. 3/4, active structure ACT including active patterns 111-114, located below the separation regions MS1/MS2 and separation group SG1/SG2, [0043]) and contacting electrically conductive trench fill via structure (FIGS. 3/4, depicting wherein the active patterns 111-114 contact the conductive layer 109).
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM D WEILAND whose telephone number is (703)756-4760. The examiner can normally be reached Monday - Friday 9am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Steven Gauthier can be reached at (571)270-0373. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ADAM D WEILAND/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813
Prosecution Insights