DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-15, 17-24, 26, and 27 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US Pub. No. 2022/0222160), hereinafter referred to as Lee, in view of Choi et al. (US Pub. No. 2013/0132648), hereinafter referred to as Choi.
Referring to claim 1, Lee discloses a device control method, configured for a memory storage device (fig. 1, Memory device 100), wherein the memory storage device comprises a connection interface unit (memory controller 110, fig. 1), the connection interface unit is configured to be coupled to a host system (fig. 2, transmission interface circuit 118 of memory controller coupled to host device 50), and the device control method comprises: obtaining device status information of the memory storage device (control unit 420 can send the temperature signal TEMPERATURE carrying the latest value of the temperature T to the microprocessor 112, for being read by the microprocessor 112, [0031]; FIG. 5 illustrates a speed-down control scheme of the data accessing method according to an embodiment of the present invention, where the power consumption POWER of the memory controller 110 (e.g. the transmission interface circuit 118) may vary with respect to time, and may be measured in unit of Watt (W), [0033]); and adjusting a connection interface standard adopted by the connection interface unit itself (the memory controller 110 can perform dynamic speed adjustment during data accessing, [0023]) from a first connection interface standard to a second connection interface standard, wherein the first connection interface standard is different from the second connection interface standard (In Step S16, the microprocessor 112 can calculate the increment ΔT1 such as the difference (T12−T11) between the second temperature value T12 and the first temperature value T11, [0042]; In Step S17, based on the at least one first predetermined rule, the microprocessor 112 can determine the target communications speed according to the increment ΔT1. For example, in a situation where an original communications speed such as the higher speed represents the PCIe Generation (Gen) 4 Speed Gen_4_Speed (e.g. 16 GT/s), the microprocessor 112 can determine the target communications speed TARGET_SPEED such as the lower speed to be a first communications speed among a first set of predetermined communications speeds, such as one of the PCIe Gen 1 Speed Gen_1_Speed (e.g. 2.5 GT/s), the PCIe Gen 2 Speed Gen_2_Speed (e.g. 5 GT/s) and the PCIe Gen 3 Speed Gen_3_Speed (e.g. 8 GT/s) that are less than the PCIe Gen 4 Speed Gen_4_Speed, [0043]).
While Lee teaches discusses the adjustment a connection interface standard and corresponding data transfer speed according to device status information, the adjustment is according to monitored temperature, and therefore Lee does not appear to explicitly disclose monitoring a data transfer speed of the connection interface unit with the host system and making the adjustment according to the monitored data transfer speed of the connection interface being less than an upper limit of data transfer speed corresponding to the first connection interface standard.
However, Choi discloses monitoring a data transfer speed of the connection interface unit with the host system and making the adjustment according to the monitored data transfer speed of the connection interface less than an upper limit of data transfer speed corresponding to the first connection interface standard (when the data transmission speed between the host access interface 13 and the host 2 is slow, [0024]; detecting the communication protocol of the host 2 and fetching the transmission bandwidth of the host 2…judging whether the transmission bandwidth of the host 2 is smaller than the set transmission bandwidth of the flash memory interface 12…if the transmission bandwidth of the host 2 is smaller than the set transmission bandwidth of the flash memory interface 12 of the portable storage device 1, the control unit 11 changes the operation mode of the flash memory interface 12 to lower the transmission bandwidth of the flash memory interface [0028-0029]).
Lee and Choi are analogous art because they are from the same field of endeavor, interface management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lee and Choi before him or her, to modify the device status information of Lee to include the data transfer speed consideration of Choi because the performance information would facilitate optimal configuration of the connection.
The suggestion/motivation for doing so would have been to reduce power consumption (Choi: [0032]).
Therefore, it would have been obvious to combine Lee and Choi to obtain the invention as specified in the instant claim.
As to claims 2, 11, and 20, Lee discloses the device status information further comprises temperature information and power consumption information, temperature information reflects a temperature of the memory storage device, and the power consumption information reflects a power consumption per unit time of the memory storage device (fig. 4, Thermal sensor 430; FIG. 5 illustrates a speed-down control scheme of the data accessing method according to an embodiment of the present invention, where the power consumption POWER of the memory controller 110 (e.g. the transmission interface circuit 118) may vary with respect to time, and may be measured in unit of Watt (W), [0033]).
As to claims 3, 12, and 21, Lee discloses when the connection interface unit adopts the first connection interface standard, the memory storage device has a first upper limit of data transfer per unit time, when the connection interface unit adopts the second connection interface standard, the memory storage device has a second upper limit of data transfer per unit time, wherein the first upper limit of data transfer per unit time is different from the second upper limit of data transfer per unit time (In Step S17, based on the at least one first predetermined rule, the microprocessor 112 can determine the target communications speed according to the increment ΔT1. For example, in a situation where an original communications speed such as the higher speed represents the PCIe Generation (Gen) 4 Speed Gen_4_Speed (e.g. 16 GT/s), the microprocessor 112 can determine the target communications speed TARGET_SPEED such as the lower speed to be a first communications speed among a first set of predetermined communications speeds, such as one of the PCIe Gen 1 Speed Gen_1_Speed (e.g. 2.5 GT/s), the PCIe Gen 2 Speed Gen_2_Speed (e.g. 5 GT/s) and the PCIe Gen 3 Speed Gen_3_Speed (e.g. 8 GT/s) that are less than the PCIe Gen 4 Speed Gen_4_Speed, 0043]).
As to claims 4, 13, and 22, Lee discloses adjusting an upper limit of data transfer per unit time of the memory storage device from the first upper limit of data transfer per unit time to a third upper limit of data transfer per unit time according to the device status information when the connection interface unit adopts the first connection interface standard, wherein the second upper limit of data transfer per unit time is different from the third upper limit of data transfer per unit time (In Step S17, based on the at least one first predetermined rule, the microprocessor 112 can determine the target communications speed according to the increment ΔT1. For example, in a situation where an original communications speed such as the higher speed represents the PCIe Generation (Gen) 4 Speed Gen_4_Speed (e.g. 16 GT/s), the microprocessor 112 can determine the target communications speed TARGET_SPEED such as the lower speed to be a first communications speed among a first set of predetermined communications speeds, such as one of the PCIe Gen 1 Speed Gen_1_Speed (e.g. 2.5 GT/s), the PCIe Gen 2 Speed Gen_2_Speed (e.g. 5 GT/s) and the PCIe Gen 3 Speed Gen_3_Speed (e.g. 8 GT/s) that are less than the PCIe Gen 4 Speed Gen_4_Speed” in paragraph 0043; “In some examples, the first communications speed such as the lower speed may represent any communications speed among the PCIe Gen 1 Speed Gen_1_Speed, the PCIe Gen 2 Speed Gen_2_Speed, the PCIe Gen 3 Speed Gen_3_Speed, the PCIe Gen 4 Speed Gen_4_Speed, the PCIe Gen 5 Speed Gen_5_Speed, etc. except the highest communications speed available (e.g. the PCIe Gen 6 Speed Gen_6_Speed such as 64 GT/s), and the target communications speed TARGET_SPEED such as the higher speed may represent one of another set of predetermined communications speeds greater than the any communications speed, [0057]).
As to claims 5, 14, and 23, Lee discloses wherein the connection interface standard adopted by the connection interface unit comprises at least two of a first generation, a second generation, a third generation, a fourth generation, and a fifth generation of a PCI Express standard (In Step S17, based on the at least one first predetermined rule, the microprocessor 112 can determine the target communications speed according to the increment ΔT1. For example, in a situation where an original communications speed such as the higher speed represents the PCIe Generation (Gen) 4 Speed Gen_4_Speed (e.g. 16 GT/s), the microprocessor 112 can determine the target communications speed TARGET_SPEED such as the lower speed to be a first communications speed among a first set of predetermined communications speeds, such as one of the PCIe Gen 1 Speed Gen_1_Speed (e.g. 2.5 GT/s), the PCIe Gen 2 Speed Gen_2_Speed (e.g. 5 GT/s) and the PCIe Gen 3 Speed Gen_3_Speed (e.g. 8 GT/s) that are less than the PCIe Gen 4 Speed Gen_4_Speed, [0043]).
As to claims 6, 15, and 24, Lee does not appear to explicitly disclose wherein the performance information further reflects a data transfer per unit time between the memory storage device and the host system.
However, Choi discloses the performance information further reflects a data transfer per unit time between the memory storage device and the host system (high bandwidth means high operation frequency and high data latching rate, [0006]; DDR…SDR…133MHz…100MHz, [0020]).
The motivation/suggestion to combine remains as indicated above.
As to claims 8, 17, and 26, Lee discloses wherein the step of adjusting the connection interface standard adopted by the connection interface unit from the first connection interface standard to the second connection interface standard according to the device status information comprises: adjusting a coding rule adopted by the connection interface unit according to the device status information (In Step S17, based on the at least one first predetermined rule, the microprocessor 112 can determine the target communications speed according to the increment ΔT1. For example, in a situation where an original communications speed such as the higher speed represents the PCIe Generation (Gen) 4 Speed Gen_4_Speed (e.g. 16 GT/s), the microprocessor 112 can determine the target communications speed TARGET_SPEED such as the lower speed to be a first communications speed among a first set of predetermined communications speeds, such as one of the PCIe Gen 1 Speed Gen_1_Speed (e.g. 2.5 GT/s), the PCIe Gen 2 Speed Gen_2_Speed (e.g. 5 GT/s) and the PCIe Gen 3 Speed Gen_3_Speed (e.g. 8 GT/s) that are less than the PCIe Gen 4 Speed Gen_4_Speed, [0043]).
As to claims 9, 18, and 27, Lee discloses wherein the device status information also reflects whether the memory storage device is performing a default operation, and the step of adjusting the connection interface standard adopted by the connection interface unit from the first connection interface standard to the second connection interface standard according to the device status information comprises: adjusting the connection interface standard adopted by the connection interface unit from the first interface standard to the second interface standard in response to the memory storage device performing the default operation, wherein the default operation comprises at least one of a data merging operation, a wear leveling operation, and a data refreshing operation wherein the step of adjusting the connection interface standard adopted by the connection interface unit from the first connection interface standard to the second connection interface standard according to the device status information comprises: adjusting a coding rule adopted by the connection interface unit according to the device status information (Steps S30 and S31 can be performed in a default speed phase PHASE(0), Steps S40-S42 can be performed in a speed-down phase PHASE(1), and Steps S50-S52 can be performed in a speed-up phase PHASE(2), [0061]; a first partial working flow comprising Steps S40-S42 may be repeated (e.g. by executing Steps S40-S42 multiple times) to speed down multiple times in the speed-down phase PHASE(1), and a second partial working flow comprising Steps S50-S52 may be repeated (e.g. by executing Steps S50-S52 multiple times) to speed up multiple times in the speed-up phase PHASE(2), [0072]).
Referring to claims 10 and 19, Lee discloses memory storage device (fig. 1, Memory device 100), comprising: a connection interface unit (memory controller 110, fig. 1) configured to be coupled to a host system (fig. 2, transmission interface circuit 118 of memory controller coupled to the host device 50); a rewritable non-volatile memory module (fig. 1, NV memory 120); a memory control circuit unit coupled to the connection interface unit and the rewritable non-volatile memory module, wherein the memory control circuit unit is configured to: obtain device status information of the memory storage device (control unit 420 can send the temperature signal TEMPERATURE carrying the latest value of the temperature T to the microprocessor 112, for being read by the microprocessor 112, [0031]; FIG. 5 illustrates a speed-down control scheme of the data accessing method according to an embodiment of the present invention, where the power consumption POWER of the memory controller 110 (e.g. the transmission interface circuit 118) may vary with respect to time, and may be measured in unit of Watt (W), [0033]); and adjust a connection interface standard adopted by the connection interface unit itself (the memory controller 110 can perform dynamic speed adjustment during data accessing, [0023]) from a first connection interface standard to a second connection interface standard, wherein the first connection interface standard is different from the second connection interface standard (In Step S16, the microprocessor 112 can calculate the increment ΔT1 such as the difference (T12−T11) between the second temperature value T12 and the first temperature value T11, [0042]; In Step S17, based on the at least one first predetermined rule, the microprocessor 112 can determine the target communications speed according to the increment ΔT1. For example, in a situation where an original communications speed such as the higher speed represents the PCIe Generation (Gen) 4 Speed Gen_4_Speed (e.g. 16 GT/s), the microprocessor 112 can determine the target communications speed TARGET_SPEED such as the lower speed to be a first communications speed among a first set of predetermined communications speeds, such as one of the PCIe Gen 1 Speed Gen_1_Speed (e.g. 2.5 GT/s), the PCIe Gen 2 Speed Gen_2_Speed (e.g. 5 GT/s) and the PCIe Gen 3 Speed Gen_3_Speed (e.g. 8 GT/s) that are less than the PCIe Gen 4 Speed Gen_4_Speed, [0043]).
While Lee teaches discusses the adjustment of a connection interface standard and corresponding data transfer speed according to device status information, the adjustment is according to monitored temperature, and therefore Lee does not appear to explicitly disclose monitoring a data transfer speed of the connection interface unit with the host system and making the adjustment according to the monitored data transfer speed of the connection interface being less than an upper limit of data transfer speed corresponding to the first connection interface standard.
However, Choi discloses monitoring a data transfer speed of the connection interface unit with the host system and making the adjustment according to the monitored data transfer speed of the connection interface less than an upper limit of data transfer speed corresponding to the first connection interface standard (when the data transmission speed between the host access interface 13 and the host 2 is slow, [0024]; detecting the communication protocol of the host 2 and fetching the transmission bandwidth of the host 2…judging whether the transmission bandwidth of the host 2 is smaller than the set transmission bandwidth of the flash memory interface 12…if the transmission bandwidth of the host 2 is smaller than the set transmission bandwidth of the flash memory interface 12 of the portable storage device 1, the control unit 11 changes the operation mode of the flash memory interface 12 to lower the transmission bandwidth of the flash memory interface [0028-0029]).
Lee and Choi are analogous art because they are from the same field of endeavor, interface management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lee and Choi before him or her, to modify the device status information of Lee to include the data transfer speed consideration of Choi because the performance information would facilitate optimal configuration of the connection.
The suggestion/motivation for doing so would have been to reduce power consumption (Choi: [0032]).
Therefore, it would have been obvious to combine Lee and Choi to obtain the invention as specified in the instant claim.
Claims 7, 16, and 25 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee in view of Choi, as applied to claims 1-6, 8-15, 17-24, 26, and 27 above, further in view of Srivastava et al (US Pub. No. 2024/0111700), hereinafter referred to as Srivastava.
As to claims 7, 16, and 25, while Lee discloses the step of adjusting the connection interface standard adopted by the connection interface unit from the first connection interface standard to the second connection interface standard, Lee does not appear to explicitly disclose enabling or disabling at least one circuit in the connection interface unit.
However Srivastava discloses enabling or disabling at least one circuit in the connection interface unit (figs. 5A-5D, 8A-8D; The controller is configured to receive a request at the controller to change a data rate of the data link to a requested data rate, change the second set of lanes from an idle state to an active state, train the second set of lanes to the requested data rate, transfer data traffic from the first set of lanes to the second set of lanes after the training, and transmit the data traffic on the second set of lanes, see the ABSTRACT; FIG. 5B shows a multiple lane data link 542 between the host 502 and the EP 506 training to a new data rate. In one aspect, when a controller at the host 502 or EP 504 receives a request to change the data rate of the data link 542, e.g., from GEN2 to GEN3, the data link 542 is changed, [0070]; FIG. 8B shows a multiple lane data link 842 between the host 802 and the EP 806 training to a new data rate. In one aspect, a controller at the host 802 or EP 804 receives a request to change the data rate of the data link 842, from GEN4 to GEN3 and to change the link width from x1 to x2. This is an example and other combinations are possible. The data link 842 is changed by changing the idle state lanes of the second set of lanes to an active state through a recovery state and a configuration state. The first set of lanes 810 continue to transmit data traffic as before. This is changing the second set of lanes from the idle state to an active state and training the second set of lanes to the requested data rate, [0087]).
Lee, Choi, and Srivastava are analogous art because they are from the same field of endeavor, interface management.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lee, Choi, and Srivastava before him or her, to modify the interface circuitry of Lee to include the activation technique Srivastava to maintain availability of the communication links.
The suggestion/motivation for doing so would have been avoid interrupting data traffic through the communication link (Srivastava: [0033]).
Therefore, it would have been obvious to combine Lee, Choi, and Srivastava to obtain the invention as specified in the instant claim.
Response to Arguments
Applicant's arguments filed 11/14/2025, which address the teachings of the prior art of Fuxa, have been fully considered but they are moot in view of the new grounds of rejection necessitated by the amendments.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
The examiner has cited particular column, line, and/or paragraph numbers in the references as applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in its entirety as potentially teaching of all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
The examiner requests, in response to this office action, support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line number(s) in the specification and/or drawing figure(s). This will assist the examiner in prosecuting the application. When responding to this office action, applicant is advised to clearly point out the patentable novelty which he or she thinks the claims present, in view of the state of art disclosed by the references cited or the objections made. He or she must also show how the amendments avoid such references or objections. See 37 C.F.R. 1.111(c).
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Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC T OBERLY whose telephone number is (571)272-6991. The examiner can normally be reached on M-F 800am-430pm (MT).
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dr. Henry Tsai can be reached on (571) 272-4176. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC T OBERLY/ Primary Examiner, Art Unit 2184