Prosecution Insights
Last updated: August 18, 2026
Application No. 18/450,417

DISPLAY DEVICE

Final Rejection §103
Filed
Aug 16, 2023
Priority
Feb 18, 2021 — JP 2021-024456 +1 more
Examiner
CROSS, XIA L
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Magnolia White Corporation
OA Round
2 (Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
0m
Est. Remaining
91%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
386 granted / 468 resolved
+14.5% vs TC avg
Moderate +9% lift
Without
With
+8.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
18 currently pending
Career history
480
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
50.0%
+10.0% vs TC avg
§102
25.6%
-14.4% vs TC avg
§112
17.2%
-22.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 468 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification Examiner acknowledges the amendment to the title filed on May 19, 2026. The objection to specification in the previous Office Action filed on February 19, 2026 is hereby withdrawn. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1 and 4-8 are rejected under 35 U.S.C. 103 as being unpatentable over ITO et al. (US PG-Pub No.: 2015/0060832 A1, hereinafter, “ITO”), prior art of record, in view of Sakakibara et al. (US PG-Pub No.: 2023/0180532 A1, hereinafter, “Sakakibara”), prior art of record. Regarding claim 1, ITO discloses a display device (see ITO, FIG. 3) comprising: a base (102, FIG. 3); a plurality of pixel circuits (130+146+142c, FIG. 3; FIG. 3 shows one typical pixel and FIG. 1 shows a plurality of pixels) disposed on the base (102); an insulating layer (150, FIG. 3) which covers the base (102) and each of the pixel circuits (130+146+142c); a plurality of apertures (apertures for 156, FIG. 3) formed in the insulating layer (150), at respective locations overlapping of the pixel circuits (130+146+142c. overlapping 146); a plurality of display elements (126, FIGs. 1 and 3) driven and controlled respectively by the pixel circuits (130+146+142c, FIGs. 2 and 3); and a partition (152, FIG. 3) disposed on the insulating layer (150) to partition the display elements (126) from each other (FIGs. 1 and 3), wherein each of the display elements (126) comprises: a lower electrode (148, ¶ [0041]) disposed above the insulating layer (150) and connected to the pixel circuit (130+146+142c) through the aperture (FIG. 3); an organic layer (162, ¶ [0048]) disposed in the aperture and covering the lower electrode (148, FIG. 3); and an upper electrode (164, ¶ [0049]) covering the organic layer (162, FIG. 3), the lower electrode (148) and the organic layer (162) are in contact over an entire surface of the aperture (FIG. 3), the organic layer (162) and the upper electrode (164) are in contact over the entire surface of the aperture (FIG. 3), and a peripheral portion of the lower electrode (148) is covered by the partition (152, FIG. 3). ITO is silent regarding that the partition partitions the organic layer of one of the display elements from the organic layer of an adjacent one of the display elements. Sakakibara, however, discloses a display device (see Sakakibara, FIG. 5), comprising a partition (BK, FIG. 5) partitions an organic layer (REML, ¶¶ [0002] and [0069]) of one of the display elements (R, FIG. 5) from an organic layer (GEML, FIG. 5) of an adjacent one of the display elements (G, FIG. 5). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form ITO’s organic emitting layer in segments and the partition partitions the organic layer of one of the display elements from the organic layer of an adjacent one of the display elements, as taught by Sakakibara, since it is an alternative design to minimize crosstalk among the display elements. Regarding claim 4, ITO discloses a display device (see ITO, FIG. 3) comprising: a base (102, FIG. 3); a plurality of pixel circuits (130+146+142c, FIG. 3; FIG. 3 shows one typical pixel and FIG. 1 shows a plurality of pixels) disposed on the base (102); an insulating layer (150, FIG. 3) which covers the base (102) and each of the pixel circuits (130+146+142c); a plurality of apertures (apertures for 156, FIG. 3) formed in the insulating layer (150), at respective locations overlapping of the pixel circuits (130+146+142c. overlapping 146); and a plurality of display elements (126, FIGs. 1 and 3) driven and controlled respectively by the pixel circuits (130+146+142c, FIGs. 2 and 3), wherein each of the display elements (126) comprises: a lower electrode (148, ¶ [0041]) disposed above the insulating layer (150) and connected to the respective pixel circuit (130+146+142c) through the aperture (FIG. 3); an organic layer (162, ¶ [0048]) disposed in the aperture and covering the lower electrode (148, FIG. 3); and an upper electrode (164, ¶ [0049]) covering the organic layer (162, FIG. 3), the lower electrode (148) and the organic layer (162) are in contact over an entire surface of the aperture (FIG. 3), and the organic layer (162) and the upper electrode (164) are in contact over the entire surface of the aperture (FIG. 3). ITO is silent regarding that the organic layer of one of the display elements is spaced apart from the organic layer of an adjacent one of the display elements, and a peripheral edge of the lower electrode is covered by and in contact with the organic layer. Sakakibara, however, discloses a display device (see Sakakibara, FIG. 5), wherein an organic layer (REML, ¶¶ [0002] and [0069]) of one of the display elements (R, FIG. 5) is spaced apart from the organic layer (GEML, FIG. 5) of an adjacent one of the display elements (G, FIG. 5), and a peripheral edge of a lower electrode (C, ¶ [0093]) is covered by and in contact with the organic layer (REML/GEML, FIG. 5). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form ITO’s organic layer of one of the display elements spaced apart from the organic layer of an adjacent one of the display elements, and a peripheral edge of the lower electrode covered by and in contact with the organic layer, as taught by Sakakibara, since it is an alternative design to minimize crosstalk among the display elements. Regarding claim 5, ITO in view of Sakakibara discloses the display device of claim 4, wherein a peripheral portion of the lower electrode (148) is covered by the organic layer (162, FIG. 3), and the lower electrode (148) and the upper electrode (164) are not in contact with each other (FIG. 3). Regarding claim 6, ITO in view of Sakakibara discloses the display device of claim 5, wherein the organic layer (162) includes at least a first organic layer (a light emitting layer, ¶ [0048]) and a second organic layer (a hole transport layer, ¶ [0048]) including at least one functional layer (the light emitting layer). ITO is silent regarding that the peripheral portion of the lower electrode (148), a peripheral portion of the first organic layer (the light emitting layer of 162) and a peripheral portion of the second organic layer (the hole transport layer of 162) each has a forward tapered shape. Sakakibara, however, discloses a display device (see Sakakibara, FIG. 5), wherein a peripheral portion of a lower electrode (C, FIG. 5), a peripheral portion of a first organic layer (EML, FIG. 5) and a peripheral portion of a second organic layer (HTL, FIG. 5) each has a forward tapered shape (FIG. 5). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form ITO’s peripheral portion of the lower electrode, a peripheral portion of the first organic layer and a peripheral portion of the second organic layer each has a forward tapered shape, as taught by Sakakibara, since it is an alternative design to separate the pixels and minimize crosstalk. Regarding claim 7, ITO in view of Sakakibara discloses the display device of claim 6, wherein the peripheral portion of the lower electrode (Sakakibara’s C) is covered by at least the peripheral portion of the second organic layer (covered from plan view, Sakakibara’s FIG. 5). Regarding claim 8, ITO in view of Sakakibara discloses the display device of claim 7, wherein the upper electrode (ITO’s 164 in FIG. 3 and Sakakibara’s A in FIG. 5) is disposed over the plurality of display elements (ITO’s 126 in FIG. 3 and Sakakibara’s R/G/B in FIG. 5). Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over ITO et al. (US PG-Pub No.: 2015/0060832 A1, hereinafter, “ITO”), prior art of record, in view of Sakakibara et al. (US PG-Pub No.: 2023/0180532 A1, hereinafter, “Sakakibara”), prior art of record, as applied to claim 1 above, and further in view of Nishimura et al. (US PG-Pub No.: 2018/0294428 A1, hereinafter, “Nishimura”), prior art of record. Regarding claim 2, ITO in view of Sakakibara discloses the display device of claim 1. ITO is silent regarding that the partition (152) is formed into a grid pattern in plan view. However, it is well-known that partition is formed into a grid pattern since pixels are in a matrix in a display. For example, Nishimura discloses a display device (see Nishimura, FIG. 3), wherein partition (122X+522Y, ¶ [0133]) is formed into a grid pattern in plan view (¶ [0133] and FIG. 3). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form ITO’s partition into a grid pattern, as taught by Nishimura, in order to separate the matrix of pixels and minimize crosstalk. Regarding claim 3, ITO in view of Sakakibara discloses the display device of claim 1. ITO is silent regarding that the partition is formed into a stripe shape in plan view. However, it is well-known that partition is formed into a stripe shape. For example, Nishimura discloses a display device (see Nishimura, FIG. 3), wherein partition (122X+522Y, ¶ [0133]) is formed into a stripe shape in plan view (¶ [0133] and FIG. 3). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form ITO’s partition into a stripe shape, as taught by Nishimura, in order to separate the matrix of pixels and minimize crosstalk. Response to Arguments Applicant’s arguments with respect to claim 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIA L. CROSS whose telephone number is (571)270-3273. The examiner can normally be reached 9 am-5:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /XIA L CROSS/Primary Examiner, Art Unit 2892
Read full office action

Prosecution Timeline

Aug 16, 2023
Application Filed
Feb 19, 2026
Non-Final Rejection mailed — §103
May 19, 2026
Response Filed
Jul 29, 2026
Final Rejection mailed — §103 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

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PHOTOELECTRIC CONVERSION DEVICE AND DISPLAY DEVICE COMPRISING THE SAME
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2y 9m to grant Granted Jul 28, 2026
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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
91%
With Interview (+8.9%)
2y 4m (~0m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 468 resolved cases by this examiner. Grant probability derived from career allowance rate.

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