Prosecution Insights
Last updated: April 19, 2026
Application No. 18/450,417

DISPLAY DEVICE

Non-Final OA §102§103
Filed
Aug 16, 2023
Examiner
CROSS, XIA L
Art Unit
2892
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Magnolia White Corporation
OA Round
1 (Non-Final)
82%
Grant Probability
Favorable
1-2
OA Rounds
2y 6m
To Grant
92%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allow Rate
376 granted / 458 resolved
+14.1% vs TC avg
Moderate +10% lift
Without
With
+9.7%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
14 currently pending
Career history
472
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
44.4%
+4.4% vs TC avg
§102
25.8%
-14.2% vs TC avg
§112
21.2%
-18.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 458 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Specification The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1, 4-5, and 10-12 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by ITO et al. (US PG-Pub No.: 2015/0060832 A1, hereinafter, “ITO”). Regarding claim 1, ITO discloses a display device (see ITO, FIG. 3) comprising: a base (102, FIG. 3); a plurality of pixel circuits (130+146+142c, FIG. 3; FIG. 3 shows one typical pixel and FIG. 1 shows a plurality of pixels) disposed on the base (102); an insulating layer (150, FIG. 3) which covers the base (102) and each of the pixel circuits (130+146+142c); a plurality of apertures (apertures for 156, FIG. 3) formed in the insulating layer (150), at respective locations overlapping of the pixel circuits (130+146+142c. overlapping 146); a plurality of display elements (126, FIGs. 1 and 3) driven and controlled respectively by the pixel circuits (130+146+142c, FIGs. 2 and 3); and a partition (152, FIG. 3) disposed on the insulating layer (150) to partition the display elements (126) from each other (FIGs. 1 and 3), wherein each of the display elements (126) comprises: a lower electrode (148, ¶ [0041]) disposed above the insulating layer (150) and connected to the pixel circuit (130+146+142c) through the aperture (FIG. 3); an organic layer (162, ¶ [0048]) disposed in the aperture and covering the lower electrode (148, FIG. 3); and an upper electrode (164, ¶ [0049]) covering the organic layer (162, FIG. 3), the lower electrode (148) and the organic layer (162) are in contact over an entire surface of the aperture (FIG. 3), the organic layer (162) and the upper electrode (164) are in contact over the entire surface of the aperture (FIG. 3), and a peripheral portion of the lower electrode (148) is covered by the partition (152, FIG. 3). Regarding claim 4, ITO discloses a display device (see ITO, FIG. 3) comprising: a base (102, FIG. 3); a plurality of pixel circuits (130+146+142c, FIG. 3; FIG. 3 shows one typical pixel and FIG. 1 shows a plurality of pixels) disposed on the base (102); an insulating layer (150, FIG. 3) which covers the base (102) and each of the pixel circuits (130+146+142c); a plurality of apertures (apertures for 156, FIG. 3) formed in the insulating layer (150), at respective locations overlapping of the pixel circuits (130+146+142c. overlapping 146); and a plurality of display elements (126, FIGs. 1 and 3) driven and controlled respectively by the pixel circuits (130+146+142c, FIGs. 2 and 3), wherein each of the display elements (126) comprises: a lower electrode (148, ¶ [0041]) disposed above the insulating layer (150) and connected to the respective pixel circuit (130+146+142c) through the aperture (FIG. 3); an organic layer (162, ¶ [0048]) disposed in the aperture and covering the lower electrode (148, FIG. 3); and an upper electrode (164, ¶ [0049]) covering the organic layer (162, FIG. 3), the lower electrode (148) and the organic layer (162) are in contact over an entire surface of the aperture (FIG. 3), and the organic layer (162) and the upper electrode (164) are in contact over the entire surface of the aperture (FIG. 3). Regarding claim 5, ITO discloses the display device of claim 4, wherein a peripheral portion of the lower electrode (148) is covered by the organic layer (162, FIG. 3), and the lower electrode (148) and the upper electrode (164) are not in contact with each other (FIG. 3). Regarding claim 10, ITO discloses the display device of claim 4, further comprising: an insulating film (152, FIG. 3) which covers the peripheral portion of the lower electrode (148) and is covered by the organic layer (162), wherein the lower electrode (148) and the upper electrode (164) are not in contact with each other (FIG. 3). Regarding claim 11, ITO discloses the display device of claim 4, further comprising: a carrier blocking layer (a hole transport layer in 162, ¶ [0048] and FIG. 3) which covers the peripheral portion of the lower electrode (148, covering from plan view) and is covered by the organic layer (a light emitting layer in 162, ¶ [0048]), wherein the lower electrode (148) and the upper electrode (164) are not in contact with each other (FIG. 3). Regarding claim 12, ITO discloses the display device of claim 11, wherein the carrier blocking layer (a hole transport layer in 162) includes at least one of a hole blocking layer and an electron blocking layer. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over ITO et al. (US PG-Pub No.: 2015/0060832 A1, hereinafter, “ITO”), as applied to claim 1 above, and in view of Nishimura et al. (US PG-Pub No.: 2018/0294428 A1, hereinafter, “Nishimura”). Regarding claim 2, ITO discloses the display device of claim 1. ITO is silent regarding that the partition (152) is formed into a grid pattern in plan view. However, it is well-known that partition is formed into a grid pattern since pixels are in a matrix in a display. For example, Nishimura discloses a display device (see Nishimura, FIG. 3), wherein partition (122X+522Y, ¶ [0133]) is formed into a grid pattern in plan view (¶ [0133] and FIG. 3). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form ITO’s partition into a grid pattern, as taught by Nishimura, in order to separate the matrix of pixels and minimize crosstalk. Regarding claim 3, ITO discloses the display device of claim 1. ITO is silent regarding that the partition is formed into a stripe shape in plan view. However, it is well-known that partition is formed into a stripe shape. For example, Nishimura discloses a display device (see Nishimura, FIG. 3), wherein partition (122X+522Y, ¶ [0133]) is formed into a stripe shape in plan view (¶ [0133] and FIG. 3). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form ITO’s partition into a stripe shape, as taught by Nishimura, in order to separate the matrix of pixels and minimize crosstalk. Claims 6-9 are rejected under 35 U.S.C. 103 as being unpatentable over ITO et al. (US PG-Pub No.: 2015/0060832 A1, hereinafter, “ITO”), as applied to claim 1 above, and in view of Sakakibara et al. (US PG-Pub No.: 2023/0180532 A1, hereinafter, “Sakakibara”). Regarding claim 6, ITO discloses the display device of claim 5, wherein the organic layer (162) includes at least a first organic layer (a light emitting layer, ¶ [0048]) and a second organic layer (a hole transport layer, ¶ [0048]) including at least one functional layer (the light emitting layer). ITO is silent regarding that the peripheral portion of the lower electrode (148), a peripheral portion of the first organic layer (the light emitting layer of 162) and a peripheral portion of the second organic layer (the hole transport layer of 162) each has a forward tapered shape. Sakakibara, however, discloses a display device (see Sakakibara, FIG. 5), wherein a peripheral portion of a lower electrode (C, FIG. 5), a peripheral portion of a first organic layer (EML, FIG. 5) and a peripheral portion of a second organic layer (HTL, FIG. 5) each has a forward tapered shape (FIG. 5). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to form ITO’s peripheral portion of the lower electrode, a peripheral portion of the first organic layer and a peripheral portion of the second organic layer each has a forward tapered shape, as taught by Sakakibara, since it is an alternative design to separate the pixels and minimize crosstalk. Regarding claim 7, ITO in view of Sakakibara discloses the display device of claim 6, wherein the peripheral portion of the lower electrode (Sakakibara’s C) is covered by at least the peripheral portion of the second organic layer (covered from plan view, Sakakibara’s FIG. 5). Regarding claim 8, ITO in view of Sakakibara discloses the display device of claim 7, wherein the upper electrode (ITO’s 164 in FIG. 3 and Sakakibara’s A in FIG. 5) is disposed over the plurality of display elements (ITO’s 126 in FIG. 3 and Sakakibara’s R/G/B in FIG. 5). Regarding claim 9, ITO in view of Sakakibara discloses the display device of claim 8, wherein the second organic layer (the hole transport layer in ITO’s 162 in FIG. 3 and Sakakibara’s HTL in FIG. 5) is disposed over the plurality of display elements (ITO’s 126 and Sakakibara’s R/G/B). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIA L. CROSS whose telephone number is (571)270-3273. The examiner can normally be reached 9 am-5:30 pm. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at 571-272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /XIA L CROSS/Primary Examiner, Art Unit 2892
Read full office action

Prosecution Timeline

Aug 16, 2023
Application Filed
Jan 24, 2026
Non-Final Rejection — §102, §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
82%
Grant Probability
92%
With Interview (+9.7%)
2y 6m
Median Time to Grant
Low
PTA Risk
Based on 458 resolved cases by this examiner. Grant probability derived from career allow rate.

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