Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Note: The Examiner notes that no claim amendments were filed after the Non-Final rejection filed 1/16/2026, so the rejection is the same as before.
Claim(s) 1-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 20240021586 A1) hereafter referred to as Li in view of Liaw (US 20230411468 A1)
In regard to claim 1 Li teaches a semiconductor [see Fig. 8, Fig. 6, Fig. 1 “FIG. 8 is a cross-sectional view of a CFET 800, which includes a first GAA FET 802 formed on a first insulator layer 804, and a second GAA FET 806 formed on a second insulator layer 808” “In an example in which the first GAA FET 102 is an N-type FET and the second GAA FET 104 is a P-type FET, the source/drain 114A is coupled to the reference voltage V.sub.SS by the via VIA(2), and the contact CON(2) and the source/drain 122A are coupled to the supply voltage VDD by the vias VIA(7) and VIA(1) and the contacts CON(5) and CON(1). A binary output OUT.sub.100 having a binary state that is the inverse of the binary input IN.sub.100 is provided through one of the source/drain 114B or 122B to the contacts CON(4) and CON(7), which are coupled by vias VIA(4), VIA(6), and VIA(8)”] apparatus, comprising:
a transistor element layer [see including the first and second FET layers] having a plurality of transistors which are multi-gate transistors [see Fig. 8 GAA with plurality of semiconductor slabs] of a floating body structure;
a first wiring layer having at least [“CFET 600 also includes contact layers 632 and 634 firmed on the bottom base layer 628 and the top base layer 630, respectively” “CFET 100 also includes a first contact layer 140 and a second contact layer 142, which include contacts CON(1)-CON(7), which are electrically coupled to one or both of the first GAA FET 102 to the second GAA FET 1.04 by vias VIA(1)-VIA(9)”] one signal line, the first wiring layer being laminated on a side of one surface [i.e. top or bottom] of the transistor element layer; and
a second wiring layer having at least [“CFET 600 also includes contact layers 632 and 634 firmed on the bottom base layer 628 and the top base layer 630, respectively” “CFET 100 also includes a first contact layer 140 and a second contact layer 142, which include contacts CON(1)-CON(7), which are electrically coupled to one or both of the first GAA FET 102 to the second GAA FET 1.04 by vias VIA(1)-VIA(9)”] one signal line, the second wiring layer being laminated on a side of another surface [i.e. the other of top or bottom] of the transistor element layer,
but does not teach that the first wiring layer is “which electrically connects between a source and a gate or between a drain and a gate of at least one pair of transistors among the plurality of transistors” and that the second wiring layer is “which electrically connects between a source and a gate or between a drain and a gate of at least another pair of transistors among the plurality of transistors”.
See Fig. 1 see above “inverse of the binary input”, see “In this configuration, the CFET 100 may be coupled to an external circuit by way of the contacts CON(1)-CON(4) in the first contact layer 140, but in an alternative arrangement of contacts, the CFET 100 could be coupled to an external circuit by way of the second contact layer 142”.
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See other standard logic circuits, see Liaw Figs. 2A-2E, see in Fig. 2D see PD9 connected to the gates on the left, similarly see PD7 connected to the gates on the right, see the plurality of connections in the circuit to be made.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Li to include that the first wiring layer is “which electrically connects between a source and a gate or between a drain and a gate of at least one pair of transistors among the plurality of transistors” and that the second wiring layer is “which electrically connects between a source and a gate or between a drain and a gate of at least another pair of transistors among the plurality of transistors”.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to more easily make complex circuits by making interconnects both at the top and the bottom.
In regard to claim 2 Li and Liaw as combined teaches wherein the transistor element layer has [see Li “In an example in which the first GAA FET 102 is an N-type FET and the second GAA FET 104 is a P-type FET, the source/drain 114A is coupled to the reference voltage V.sub.SS by the via VIA(2), and the contact CON(2) and the source/drain 122A are coupled to the supply voltage VDD by the vias VIA(7) and VIA(1) and the contacts CON(5) and CON(1)” ] a P-type transistor element layer having each P-type transistor among the plurality of transistors, and an N-type transistor element layer having each N-type transistor among the plurality of transistors, the N-type transistor element layer being laminated [see Fig. 8] on one side of the P-type transistor element layer.
In regard to claim 3 Li and Liaw as combined teaches wherein the transistor element layer has a Complementary FET (CFET) structure in which a P-type transistor and an N-type transistor laminated [see Li “FIG. 8 is a cross-sectional view of a CFET 800, which includes a first GAA FET 802 formed on a first insulator layer 804, and a second GAA FET 806 formed on a second insulator layer 808” “In an example in which the first GAA FET 102 is an N-type FET and the second GAA FET 104 is a P-type FET, the source/drain 114A is coupled to the reference voltage V.sub.SS by the via VIA(2), and the contact CON(2) and the source/drain 122A are coupled to the supply voltage VDD by the vias VIA(7) and VIA(1) and the contacts CON(5) and CON(1). A binary output OUT.sub.100 having a binary state that is the inverse of the binary input IN.sub.100 is provided through one of the source/drain 114B or 122B to the contacts CON(4) and CON(7), which are coupled by vias VIA(4), VIA(6), and VIA(8)”] on a same region in a laminated direction among the plurality of transistors function as a CMOS.
In regard to claim 4 Li and Liaw as combined teaches wherein the first wiring layer has [see Li Fig. 1, Fig. 8 see VSS provided at bottom, see VDD provided both bottom and top, see “In an example in which the first GAA FET 102 is an N-type FET and the second GAA FET 104 is a P-type FET”] at least one power supply line, the second wiring layer has at least one ground line, the P-type transistor element layer is positioned on the side of the one surface of the transistor element layer, and the N-type transistor element layer is positioned on the side of the another surface of the transistor element layer.
In regard to claim 5 Li and Liaw as combined teaches wherein the transistor element layer has one pair of gate electrodes disposed opposite [see Li Fig. 1, Fig. 8 , see GAA with plurality of semiconductor slabs , see “In an example in which the first GAA FET 102 is an N-type FET and the second GAA FET 104 is a P-type FET”, see the gate contacts and vias to the N-type and P-type extend down and up to respective contacts in the top and bottom wiring layers] to each other, which are common to the P-type transistor element layer and the N-type transistor element layer, one gate electrode of the one pair of gate electrodes is connected to a first contact extending from a signal line of the first wiring layer, and another gate electrode of the one pair of gate electrodes is connected to a second contact extending from a signal line of the second wiring layer.
In regard to claim 6 Li and Liaw as combined teaches wherein the transistor element layer has one pair of gate electrodes disposed opposite [see Li Fig. 1, Fig. 8 see GAA with plurality of semiconductor slabs , see “In an example in which the first GAA FET 102 is an N-type FET and the second GAA FET 104 is a P-type FET”, see the gate contacts and vias to the N-type and P-type extend down and up to respective contacts in the top and bottom wiring layers] to each other in the P-type transistor element layer, and another pair of gate electrodes disposed opposite to each other in the N-type transistor element layer, the one pair of gate electrodes are connected to a first contact extending from a signal line of the first wiring layer, and the another pair of gate electrodes are connected to a second contact extending from a signal line of the second wiring layer.
In regard to claim 7 Li and Liaw as combined teaches wherein the transistor element layer has a [see Li “first GAA FET 102 includes three 3D semiconductor slabs 106 but may have fewer or more. A first gate structure 110 surrounds the 3D semiconductor slabs 106 (e.g., on all sides) in a channel region 112” “second GAA FET 104 includes three 3D semiconductor slabs 108 but may have fewer or more”] nanosheet structure.
In regard to claim 8 Li and Liaw as combined does not teach wherein the transistor element layer has a FinFET structure.
See Li teaches “Whether the PFET and NFET of a CFET are vertical stack, Fin-type, or gate-all-around (GAA) FETs, each CFET in a circuit includes the area occupied by at least one PFET and at least one NFET”, see method see Figs. 4A-4F, Figs. 5A-5F,
See Liaw teaches see Fig. 3 see paragraph 0036 “Each of the circuit cells discussed above is constructed by transistors. The transistors may be planar transistors, fin field-effect transistor (FinFET) transistors, gate-all-around (GAA) transistors, nano-wire transistors, nano-sheet transistors, or a combination thereof. For the sake of providing an example, an exemplary GAA transistor is illustrated in FIG. 3. However, it should be understood that the application should not be limited to a particular type of device, except as specifically claimed”, see Fig. 4C see that the channel stack has a base well “As shown in FIGS. 4C and 4D, the nanostructures 314 are suspended over the n-type well NW and p-type wells PW. In some embodiments, three nanostructures 314 are vertically stacked (or vertically arranged) from each other in the Z-direction for one transistor”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Li to include wherein the transistor element layer has a FinFET structure.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that a Fin-type transistors are simple and known to give excellent performance for switching.
Claim(s) 9-12, 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li et al. (US 20240021586 A1) hereafter referred to as Li in view of Liaw (US 20230411468 A1)
In regard to claim 9 Li teaches a manufacturing method of a semiconductor [see Fig. 8, Fig. 6, Fig. 1, see Figs. 4A-4F, Figs. 5A-5F, “FIG. 8 is a cross-sectional view of a CFET 800, which includes a first GAA FET 802 formed on a first insulator layer 804, and a second GAA FET 806 formed on a second insulator layer 808” “In an example in which the first GAA FET 102 is an N-type FET and the second GAA FET 104 is a P-type FET, the source/drain 114A is coupled to the reference voltage V.sub.SS by the via VIA(2), and the contact CON(2) and the source/drain 122A are coupled to the supply voltage VDD by the vias VIA(7) and VIA(1) and the contacts CON(5) and CON(1). A binary output OUT.sub.100 having a binary state that is the inverse of the binary input IN.sub.100 is provided through one of the source/drain 114B or 122B to the contacts CON(4) and CON(7), which are coupled by vias VIA(4), VIA(6), and VIA(8)”] apparatus, comprising:
forming a transistor element layer [see including the first and second FET layers, see Fig. 4B first and second transistor layers] having a plurality of transistors which are multi-gate transistors [see Fig. 8 GAA with plurality of semiconductor slabs] of a floating body structure;
laminating, on a side of one surface [see Fig. 4C-4F, “In accordance with stage 400D, the method 500 includes forming vias MA(1), VIA(7)-VIA(9)) in the second layer 134 (block 522) and form second contact layer 142, including contacts CON(5)-CON(7) on the second base layer 136 (block 524)” “FIG. 4F includes stage 400F in the fabrication of the CFET 100, and the method in FIG. 5F includes forming vias VIA(1)-VIA(4) in the first GAA FET 1.02 (block 528) and adding first contact layer 140, including the contacts CON(1)-CON(4) (block 530)”] of the transistor element layer, a first wiring layer having at least [“CFET 600 also includes contact layers 632 and 634 firmed on the bottom base layer 628 and the top base layer 630, respectively” “CFET 100 also includes a first contact layer 140 and a second contact layer 142, which include contacts CON(1)-CON(7), which are electrically coupled to one or both of the first GAA FET 102 to the second GAA FET 1.04 by vias VIA(1)-VIA(9)”] one signal line; and
laminating, on a side of another surface [see Fig. 4C-4F, “In accordance with stage 400D, the method 500 includes forming vias MA(1), VIA(7)-VIA(9)) in the second layer 134 (block 522) and form second contact layer 142, including contacts CON(5)-CON(7) on the second base layer 136 (block 524)” “FIG. 4F includes stage 400F in the fabrication of the CFET 100, and the method in FIG. 5F includes forming vias VIA(1)-VIA(4) in the first GAA FET 1.02 (block 528) and adding first contact layer 140, including the contacts CON(1)-CON(4) (block 530)”] of the transistor element layer, a second wiring layer having at least [“CFET 600 also includes contact layers 632 and 634 firmed on the bottom base layer 628 and the top base layer 630, respectively” “CFET 100 also includes a first contact layer 140 and a second contact layer 142, which include contacts CON(1)-CON(7), which are electrically coupled to one or both of the first GAA FET 102 to the second GAA FET 1.04 by vias VIA(1)-VIA(9)”] one signal line
but does not teach that the first wiring layer is “which electrically connects between a source and a gate or between a drain and a gate of at least one pair of transistors among the plurality of transistors” and the second wiring layer is “which electrically connects between a source and a gate or between a drain and a gate of at least another pair of transistors among the plurality of transistors”.
See Fig. 1 see above “inverse of the binary input”, see “In this configuration, the CFET 100 may be coupled to an external circuit by way of the contacts CON(1)-CON(4) in the first contact layer 140, but in an alternative arrangement of contacts, the CFET 100 could be coupled to an external circuit by way of the second contact layer 142”.
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See other standard logic circuits, see Liaw Figs. 2A-2E, see in Fig. 2D see PD9 connected to the gates on the left, similarly see PD7 connected to the gates on the right, see the plurality of connections in the circuit to be made.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Li to include that the first wiring layer is “which electrically connects between a source and a gate or between a drain and a gate of at least one pair of transistors among the plurality of transistors” and the second wiring layer is “which electrically connects between a source and a gate or between a drain and a gate of at least another pair of transistors among the plurality of transistors”.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is to more easily make complex circuits by making interconnects both at the top and the bottom.
In regard to claim 10 Li and Liaw as combined teaches wherein the forming the transistor element layer comprises:
forming a first insulating film [“first insulator layer 204 may be formed of an oxide, such as silicon dioxide (SiO.sub.2) or another suitable insulator material, and the substrate may be a semiconductor substrate (e.g., silicon)” “FIG. 2 is an illustration of a first GAA FET 202 formed on a first insulator layer 204 and a second GAA FET 206 firmed on a second insulator layer 208”, see Figs. 4A-4F “bottom substrate 402 is an insulator layer, which may be an oxide layer (e.g., SiO.sub.2). The bottom substrate 402 may be formed on a support substrate (not shown), such as a semiconductor substrate, before formation of the first GAA FET 102, and the semiconductor substrate is later removed. Alternatively, in some examples, the first GAA FET 102 may be a bulk silicon transistor, where the bottom substrate 402 is a semiconductor (e.g., silicon) substrate, and the first GAA FET 102 is formed on an STI layer”] on a substrate, and forming a laminated body having a nanosheet [“first GAA FET 202 and the second GAA FET 206 in FIG. 2 are shown in a perspective view prior to formation of epitaxial regions (epitaxial source/drains) at either end of the 3D semiconductor slabs 210 and 218 to more clearly present features of the cross-sectional view in FIG. 1”] structure or FinFET structure on the first insulating film, or forming a crystal structure layer having a crystal structure on the substrate and forming the laminated body on the crystal structure layer and then selectively remove the crystal structure layer for replacement with an insulating substance, thereby forming the first insulating film;
forming an epitaxial layer [“first GAA FET 202 and the second GAA FET 206 in FIG. 2 are shown in a perspective view prior to formation of epitaxial regions (epitaxial source/drains) at either end of the 3D semiconductor slabs 210 and 218”] doped into P-type or N-type in at least both end parts of the laminated body, thereby doping [“In an N-type device, the semiconductor source and drain are doped with a pentavalent dopant, and a voltage applied to a gate in the channel region creates an N-channel in which electrons are the majority carrier. In a P-type or P-channel device, the semiconductor source and drain are doped with a trivalent dopant, and an applied gate voltage creates a P-channel in the channel region, wherein holes are the majority carriers”] the at least both end parts into P-type or N-type;
surrounding, with a second insulating film [see Fig. 4A see “first gate structure 110 is insulated from the 3D semiconductor slabs 106 by insulator layers 124, and the second gate structure 118 is insulated from the 3D semiconductor slabs 108 by insulator layers 126”], entire circumferences of each of a non-doped region excluding the at least both end parts doped into P-type in a laminated body for a P-type channel among the laminated body and a non-doped region excluding the at least both end parts doped into N-type in a laminated body for an N-type channel among the laminated body, and forming at least one gate electrode [“the first gate structure 110 (block 504)” “second gate structure 118 (block 512)”] enclosing an entire circumference of the second insulating film, thereby forming a transistor having a P-type channel and an N-type channel; and
forming an insulating layer which entirely protects [see Fig. 4A “fill material 130, such as an inter-layer dielectric (ILD)”] the P-type channel, the N-type channel, and the at least one gate electrode on the substrate,
but does not state “non-doped” however see Fig. 3 see first and second channel region mentions crystal but does not mention doping, however see the doping of source/drain regions is mentioned.
It is noted that a person of ordinary skill in the art is aware of threshold voltage of a FET i.e. controlling the voltage required for inversion.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to use “non-doped ”, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233
In regard to claim 11 Li and Liaw as combined teaches wherein the forming the transistor element layer comprises forming [see Li “method further includes forming vias VIA(5), VIA(6) through the third layer (138) (block 508)” “method 500 includes forming vias MA(1), VIA(7)-VIA(9)) in the second layer 134 (block 522) and form second contact layer 142, including contacts CON(5)-CON(7) on the second base layer 136 (block 524). Forming the vias VIA(1), VIA(7)-VIA(9)) includes forming vias (e.g., etching and filling with a conductive metal) through the second base layer 136 of the second GAA FET 104” “the method in FIG. 5F includes forming vias VIA(1)-VIA(4) in the first GAA FET 1.02 (block 528) and adding first contact layer 140, including the contacts CON(1)-CON(4) (block 530)”], from the insulating layer side, at least one first contact to be connected to at least either of the epitaxial layer formed in the P-type channel or the epitaxial layer formed in the N-type channel, and the laminating the first wiring layer on the side of the one surface of the transistor element layer comprises forming, on the insulating layer, the first wiring layer [“In an example in which the first GAA FET 102 is an N-type FET and the second GAA FET 104 is a P-type FET, the source/drain 114A is coupled to the reference voltage V.sub.SS by the via VIA(2), and the contact CON(2) and the source/drain 122A are coupled to the supply voltage VDD by the vias VIA(7) and VIA(1) and the contacts CON(5) and CON(1). A binary output OUT.sub.100 having a binary state that is the inverse of the binary input IN.sub.100 is provided through one of the source/drain 114B or 122B to the contacts CON(4) and CON(7), which are coupled by vias VIA(4), VIA(6), and VIA(8)”] comprising at least one signal line to be connected to the at least one first contact.
In regard to claim 12 Li and Liaw as combined teaches wherein the forming the transistor element layer comprises: in a state where the first wiring layer side is retained by a support substrate, removing the substrate to expose the first insulating film formed on the substrate; and forming [see Li “method further includes forming vias VIA(5), VIA(6) through the third layer (138) (block 508)” “method 500 includes forming vias MA(1), VIA(7)-VIA(9)) in the second layer 134 (block 522) and form second contact layer 142, including contacts CON(5)-CON(7) on the second base layer 136 (block 524). Forming the vias VIA(1), VIA(7)-VIA(9)) includes forming vias (e.g., etching and filling with a conductive metal) through the second base layer 136 of the second GAA FET 104” “the method in FIG. 5F includes forming vias VIA(1)-VIA(4) in the first GAA FET 1.02 (block 528) and adding first contact layer 140, including the contacts CON(1)-CON(4) (block 530)”], from the exposed first insulating film side, at least one second contact to be connected to at least either of the epitaxial layer formed in the P-type channel or the epitaxial layer formed in the N-type channel, and the laminating the second wiring layer on the side of the another surface of the transistor element layer comprises forming, on the exposed first insulating film, a second wiring layer comprising at least one signal line to be connected to the at least one second contact.
In regard to claim 14 Li and Liaw as combined teaches wherein the forming the transistor comprises surrounding, with the second insulating film [see Fig. 4A see “first gate structure 110 is insulated from the 3D semiconductor slabs 106 by insulator layers 124, and the second gate structure 118 is insulated from the 3D semiconductor slabs 108 by insulator layers 126”], each of entire circumferences of two different non-doped regions excluding the at least both end parts doped into P-type in the laminated body for the P-type channel among the laminated body and two different non-doped regions excluding the at least both end parts doped into N-type in the laminated body for the N-type channel among the laminated body, and forming two of the gate electrodes [“the first gate structure 110 (block 504)” “second gate structure 118 (block 512)”] enclosing an entire circumference of each second insulating film, thereby forming the transistor [“In an N-type device, the semiconductor source and drain are doped with a pentavalent dopant, and a voltage applied to a gate in the channel region creates an N-channel in which electrons are the majority carrier. In a P-type or P-channel device, the semiconductor source and drain are doped with a trivalent dopant, and an applied gate voltage creates a P-channel in the channel region, wherein holes are the majority carriers”] having the P-type channel and the N-type channel, the forming the at least one first contact comprises forming [see Li “method further includes forming vias VIA(5), VIA(6) through the third layer (138) (block 508)” “method 500 includes forming vias MA(1), VIA(7)-VIA(9)) in the second layer 134 (block 522) and form second contact layer 142, including contacts CON(5)-CON(7) on the second base layer 136 (block 524). Forming the vias VIA(1), VIA(7)-VIA(9)) includes forming vias (e.g., etching and filling with a conductive metal) through the second base layer 136 of the second GAA FET 104” “the method in FIG. 5F includes forming vias VIA(1)-VIA(4) in the first GAA FET 1.02 (block 528) and adding first contact layer 140, including the contacts CON(1)-CON(4) (block 530)”], from the insulating layer side, a first contact to be connected to one of the two gate electrodes, and the forming the at least one second contact comprises forming [see Li Fig. 8], from the exposed first insulating film side, a second contact [see Li Fig. 8] to be connected to another of the two gate electrodes.
Claim(s) 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Li and Liaw as combined and further in view of Liaw (US 20220384456 A1) hereafter referred to as Liaw-456
In regard to claim 13 Li and Liaw as combined does not teach wherein the forming the laminated body comprises forming, on the substrate, the first insulating film made of a particular material having a different etching rate from a surrounding region in a particular region where the at least one second contact is formed, and the forming the at least one second contact comprises forming a through hole by selectively etching the particular region among the exposed first insulating film, and forming the at least one second contact in the through hole.
See Li “method further includes forming vias VIA(5), VIA(6) through the third layer (138) (block 508)” “method 500 includes forming vias MA(1), VIA(7)-VIA(9)) in the second layer 134 (block 522) and form second contact layer 142, including contacts CON(5)-CON(7) on the second base layer 136 (block 524). Forming the vias VIA(1), VIA(7)-VIA(9)) includes forming vias (e.g., etching and filling with a conductive metal) through the second base layer 136 of the second GAA FET 104” “the method in FIG. 5F includes forming vias VIA(1)-VIA(4) in the first GAA FET 1.02 (block 528) and adding first contact layer 140, including the contacts CON(1)-CON(4) (block 530)”.
However a person of ordinary skill in the art is aware that this is how photolithography works, see Liaw-456 “fabrication process may include forming a masking element including a photoresist layer, lithographically patterning the masking element, and subsequently etching the multi-layer stack (and portions of the substrate 12) using the patterned masking element as an etch mask. The etching process may include dry etching, wet etching, reactive ion etching (RIE), other suitable processes, or combinations thereof”.
Thus, it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Li to include masking i.e. to include wherein the forming the laminated body comprises forming, on the substrate, the first insulating film made of a particular material having a different etching rate from a surrounding region in a particular region where the at least one second contact is formed, and the forming the at least one second contact comprises forming a through hole by selectively etching the particular region among the exposed first insulating film, and forming the at least one second contact in the through hole.
Thus it would be obvious to combine the references to arrive at the claimed invention.
The motivation is that lithography and masking are known methods giving good results to form holes to form contacts, vias and metallization.
Response to Arguments
Applicant's arguments filed 4/5/2026 have been fully considered but they are not persuasive.
On page 3, 4, 5 the Applicant argues that primary reference Li does not teach the source/drain to gate connections, and that “From a visual inspection of Figures 2A-2C of Liaw '468, there clearly is no disclosure, teaching, or suggestion of the emphasized claim recitations of "... a first wiring layer having at least one signal line which electrically connects between a source and a gate or between a drain and a gate of at least one pair of transistors among the plurality of transistors ..." and "... a second wiring layer having at least one signal line which electrically connects between a source and a gate or between a drain and a gate of at least another pair of transistors among the plurality of transistors ..." ” and that “From a visual inspection of Figures 2D-2E of Liaw '468, there clearly is no disclosure, teaching, or suggestion of the emphasized claim recitations of "... a first wiring layer having at least one signal line which electrically connects between a source and a gate or between a drain and a gate of at least one pair of transistors among the plurality of transistors ..." and "... a second wiring layer having at least one signal line which electrically connects between a source and a gate or between a drain and a gate of at least another pair of transistors among the plurality of transistors ..."” and “The Office Action attempts to alleviate the deficiencies of Li and Liaw '468 by asserting on pages 4 and 9 that "... it would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains to modify Li to include that the first wiring layer is 'which-6- electrically connects between a source and a gate or between a drain and a gate of at least one pair of transistors among the plurality of transistors' and that the second wiring layer is 'which electrically connects between a source and a gate or between a drain and a gate of at least another pair of transistors among the plurality of transistors'." However, the disclosure, teachings, and suggestions of both Li and Liaw '468 do not support these assertions. This is evident and apparent, as neither Li nor Liaw '468 teach or suggest (alone or in combination) the emphasized claim recitations, as discussed above. Further, there is no disclosure in either Li or Liaw '468 that supports the combination of these references in a way that accommodates for the deficiencies in the disclosure”.
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The Examiner responds that see the rejection above, see in Liaw Fig. 2D reproced above, see the drain outputs connections to gate inputs, see PD9 connected to the gates on the left, similarly see PD7 connected to the gates on the right, see the plurality of connections in the circuit to be made. The Examiner responds that this is standard connection of Logic gates i.e. the output is from the drains of NMOS and PMOS and the input is to the gates of NMOS and PMOS, this is how a logic circuit is made in order to perform logic computation, and this is good motivation to combine because the purpose of logic gates is to make a logic circuit to perform logic computation to perform .
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SITARAMARAO S YECHURI whose telephone number is (571)272-8764. The examiner can normally be reached M-F 8:00-4:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt D Hanley can be reached at 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SITARAMARAO S YECHURI/ Primary Examiner, Art Unit 2893
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